diff --git a/compiler/src/iree/compiler/Codegen/Common/BubbleUpOrdinalOps.cpp b/compiler/src/iree/compiler/Codegen/Common/BubbleUpOrdinalOps.cpp
index db15b087a2ab..d9e375727d6a 100644
--- a/compiler/src/iree/compiler/Codegen/Common/BubbleUpOrdinalOps.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/BubbleUpOrdinalOps.cpp
@@ -43,7 +43,7 @@ namespace {
 /// `iree_tensor_ext.dispatch.workload.ordinal` ops.
 template <typename CastOpTy>
 struct BubbleUpAcrossCastOp
-    : public OpRewritePattern<IREE::TensorExt::DispatchWorkloadOrdinalOp> {
+    : OpRewritePattern<IREE::TensorExt::DispatchWorkloadOrdinalOp> {
   using Base::Base;
   LogicalResult
   matchAndRewrite(IREE::TensorExt::DispatchWorkloadOrdinalOp ordinalOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/CPU/CPUPrepareUkernels.cpp b/compiler/src/iree/compiler/Codegen/Common/CPU/CPUPrepareUkernels.cpp
index bc81200af604..e54a703fcb57 100644
--- a/compiler/src/iree/compiler/Codegen/Common/CPU/CPUPrepareUkernels.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/CPU/CPUPrepareUkernels.cpp
@@ -173,7 +173,7 @@ dropBatchTileSize(IREE::CPU::LoweringConfigAttr config) {
 
 /// Pattern to convert linalg.batch_mmt4d with batch dim = 1 into mmt4d.
 struct ConvertBatchMmt4DtoMmt4DPattern
-    : public OpRewritePattern<linalg::BatchMmt4DOp> {
+    : OpRewritePattern<linalg::BatchMmt4DOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(linalg::BatchMmt4DOp op,
@@ -252,7 +252,7 @@ struct ConvertBatchMmt4DtoMmt4DPattern
   }
 };
 
-struct Convert3DPackto2DPackPattern : public OpRewritePattern<linalg::PackOp> {
+struct Convert3DPackto2DPackPattern : OpRewritePattern<linalg::PackOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(linalg::PackOp packOp,
@@ -326,8 +326,7 @@ struct Convert3DPackto2DPackPattern : public OpRewritePattern<linalg::PackOp> {
   }
 };
 
-struct Convert5DUnPackto4DUnPackPattern
-    : public OpRewritePattern<linalg::UnPackOp> {
+struct Convert5DUnPackto4DUnPackPattern : OpRewritePattern<linalg::UnPackOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(linalg::UnPackOp unpackOp,
@@ -409,7 +408,7 @@ struct Convert5DUnPackto4DUnPackPattern
 };
 
 struct CPUPrepareUkernelsPass
-    : public impl::CPUPrepareUkernelsPassBase<CPUPrepareUkernelsPass> {
+    : impl::CPUPrepareUkernelsPassBase<CPUPrepareUkernelsPass> {
   void getDependentDialects(DialectRegistry &registry) const override {
     registry.insert<linalg::LinalgDialect, arith::ArithDialect,
                     tensor::TensorDialect, scf::SCFDialect>();
diff --git a/compiler/src/iree/compiler/Codegen/Common/CPU/CPUPropagateDataLayout.cpp b/compiler/src/iree/compiler/Codegen/Common/CPU/CPUPropagateDataLayout.cpp
index 1930f6e36185..11c2eef401bf 100644
--- a/compiler/src/iree/compiler/Codegen/Common/CPU/CPUPropagateDataLayout.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/CPU/CPUPropagateDataLayout.cpp
@@ -33,7 +33,7 @@ namespace {
 /// introducing tensor.expand_shape op on the destination tensor. However, it is
 /// not common in practice, so it is not supported now.
 struct SinkDownCollapsingUnitDimsAcrossUnpack final
-    : public OpRewritePattern<linalg::UnPackOp> {
+    : OpRewritePattern<linalg::UnPackOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(linalg::UnPackOp op,
                                 PatternRewriter &rewriter) const override {
@@ -147,7 +147,7 @@ struct SinkDownCollapsingUnitDimsAcrossUnpack final
 };
 
 struct CPUPropagateDataLayoutPass final
-    : public impl::CPUPropagateDataLayoutPassBase<CPUPropagateDataLayoutPass> {
+    : impl::CPUPropagateDataLayoutPassBase<CPUPropagateDataLayoutPass> {
   void getDependentDialects(DialectRegistry &registry) const override {
     registry.insert<linalg::LinalgDialect, tensor::TensorDialect>();
   }
diff --git a/compiler/src/iree/compiler/Codegen/Common/CombineLayoutTransformation.cpp b/compiler/src/iree/compiler/Codegen/Common/CombineLayoutTransformation.cpp
index c3773e4afe01..ba7666c0ab71 100644
--- a/compiler/src/iree/compiler/Codegen/Common/CombineLayoutTransformation.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/CombineLayoutTransformation.cpp
@@ -656,7 +656,7 @@ shouldDoReshapesByExpansion(IREE::Codegen::RelayoutCombinationScope scope) {
 /// the leaves of the chain. The leaves are simply relayout ops that have non
 /// relayout op users. The `controlFn` is a callback on the leaf OpResult that
 /// provides control over whether or not to insert a map_store op.
-struct InsertMapStoreOpPattern : public RewritePattern {
+struct InsertMapStoreOpPattern : RewritePattern {
   InsertMapStoreOpPattern(MLIRContext *context,
                           CombineRelayoutOpsControlFnRef controlFn = nullptr,
                           PatternBenefit benefit = 1)
@@ -1193,7 +1193,7 @@ FailureOr<MapLoadOp> foldIntoMapLoad(RewriterBase &rewriter, Operation *op,
 
 /// Pattern to fold consumer relayout ops into a producer map_load.
 struct FoldConsumerRelayoutIntoMapLoadPattern
-    : public OpRewritePattern<IREE::LinalgExt::MapLoadOp> {
+    : OpRewritePattern<IREE::LinalgExt::MapLoadOp> {
   using OpRewritePattern::OpRewritePattern;
 
   LogicalResult matchAndRewrite(IREE::LinalgExt::MapLoadOp mapLoadOp,
@@ -1249,7 +1249,7 @@ insertIdentityMapLoad(RewriterBase &rewriter, OpResult root,
 /// op consumers. The identity map_load can then be used to fold consumer
 /// relayout ops into it iteratively.
 struct InsertMapLoadOpPattern
-    : public OpRewritePattern<IREE::Codegen::LoadFromBufferOp> {
+    : OpRewritePattern<IREE::Codegen::LoadFromBufferOp> {
   InsertMapLoadOpPattern(MLIRContext *context, bool combineNonComplexChains)
       : OpRewritePattern(context),
         combineNonComplexChains(combineNonComplexChains) {}
diff --git a/compiler/src/iree/compiler/Codegen/Common/ConcretizePadResultShape.cpp b/compiler/src/iree/compiler/Codegen/Common/ConcretizePadResultShape.cpp
index 6458cb6f2702..c7f2f425bb3c 100644
--- a/compiler/src/iree/compiler/Codegen/Common/ConcretizePadResultShape.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/ConcretizePadResultShape.cpp
@@ -47,7 +47,7 @@ namespace {
 
 /// Concretizes tensor.pad op's result shape if its source op implements
 /// OffsetSizeAndStrideOpInterface. For example, pad(extract_slice).
-struct ConcretizePadResultShape final : public OpRewritePattern<tensor::PadOp> {
+struct ConcretizePadResultShape final : OpRewritePattern<tensor::PadOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(tensor::PadOp padOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/ConvertBf16ArithToF32.cpp b/compiler/src/iree/compiler/Codegen/Common/ConvertBf16ArithToF32.cpp
index b7941bcb2b7e..764110883f4f 100644
--- a/compiler/src/iree/compiler/Codegen/Common/ConvertBf16ArithToF32.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/ConvertBf16ArithToF32.cpp
@@ -63,7 +63,7 @@ Value convertRankedFloat(OpBuilder &builder, Type type, ValueRange inputs,
 
 // Converts from |SourceType| to |TargetType|.
 template <typename SourceType, typename TargetType>
-struct PrimitiveTypeConverter : public TypeConverter {
+struct PrimitiveTypeConverter : TypeConverter {
   explicit PrimitiveTypeConverter() {
     addConversion([](Type type) { return type; });
     addConversion([&](SourceType type) -> Type {
@@ -102,8 +102,7 @@ struct PrimitiveTypeConverter : public TypeConverter {
 };
 
 template <typename SourceType, typename TargetType>
-struct FloatTypeConverter
-    : public PrimitiveTypeConverter<SourceType, TargetType> {
+struct FloatTypeConverter : PrimitiveTypeConverter<SourceType, TargetType> {
   explicit FloatTypeConverter() {
     this->addSourceMaterialization(convertRankedFloat);
     this->addTargetMaterialization(convertRankedFloat);
@@ -112,7 +111,7 @@ struct FloatTypeConverter
 
 // Tries to completely convert a generic Operation.
 // This will process attributes, result types, and nested regions.
-struct GenericTypeConversionPattern : public ConversionPattern {
+struct GenericTypeConversionPattern : ConversionPattern {
   GenericTypeConversionPattern(MLIRContext *context,
                                TypeConverter &typeConverter)
       : ConversionPattern(typeConverter, MatchAnyOpTypeTag(), 0, context) {}
@@ -163,7 +162,7 @@ struct GenericTypeConversionPattern : public ConversionPattern {
 // unsigned integer values.
 template <typename OpTy, typename TypeTy,
           typename OperandToResultWidthLegalityRelation>
-struct ConvertTypeSensitiveArithCastOp : public OpConversionPattern<OpTy> {
+struct ConvertTypeSensitiveArithCastOp : OpConversionPattern<OpTy> {
   using OpConversionPattern<OpTy>::OpConversionPattern;
   LogicalResult
   matchAndRewrite(OpTy op, typename OpTy::Adaptor adaptor,
@@ -231,7 +230,7 @@ class PropagateCastF : public OpRewritePattern<SrcOp> {
 
 // Converts BF16s to F32s.
 struct PromoteBF16ToF32Converter
-    : public FloatTypeConverter<BFloat16Type, Float32Type> {
+    : FloatTypeConverter<BFloat16Type, Float32Type> {
   Type getTargetType(BFloat16Type type) override {
     return Float32Type::get(type.getContext());
   }
diff --git a/compiler/src/iree/compiler/Codegen/Common/ConvertToDestinationPassingStylePass.cpp b/compiler/src/iree/compiler/Codegen/Common/ConvertToDestinationPassingStylePass.cpp
index 96c1fb09d5f8..2117765d1dd7 100644
--- a/compiler/src/iree/compiler/Codegen/Common/ConvertToDestinationPassingStylePass.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/ConvertToDestinationPassingStylePass.cpp
@@ -512,8 +512,7 @@ replaceUnpackEmptyWithAllocTensor(OpBuilder &b,
 }
 
 namespace {
-struct RemoveCstOutsDependency
-    : public OpInterfaceRewritePattern<linalg::LinalgOp> {
+struct RemoveCstOutsDependency : OpInterfaceRewritePattern<linalg::LinalgOp> {
   using OpInterfaceRewritePattern<linalg::LinalgOp>::OpInterfaceRewritePattern;
 
   LogicalResult matchAndRewrite(linalg::LinalgOp op,
@@ -577,7 +576,7 @@ struct RemoveCstOutsDependency
 /// ```
 /// This is a workaround for #11273 while a proper fix lands.
 struct SwitchStoreOfIfResultValue
-    : public OpRewritePattern<IREE::TensorExt::DispatchTensorStoreOp> {
+    : OpRewritePattern<IREE::TensorExt::DispatchTensorStoreOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(IREE::TensorExt::DispatchTensorStoreOp storeOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/ConvertUnsupportedFloatArithPass.cpp b/compiler/src/iree/compiler/Codegen/Common/ConvertUnsupportedFloatArithPass.cpp
index 377a12218828..aa34b710662f 100644
--- a/compiler/src/iree/compiler/Codegen/Common/ConvertUnsupportedFloatArithPass.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/ConvertUnsupportedFloatArithPass.cpp
@@ -756,7 +756,7 @@ struct ExtFFromSmallFloat final : OpRewritePattern<arith::ExtFOp> {
 };
 
 struct ConvertUnsupportedFloatArithPass final
-    : public impl::ConvertUnsupportedFloatArithPassBase<
+    : impl::ConvertUnsupportedFloatArithPassBase<
           ConvertUnsupportedFloatArithPass> {
   void runOnOperation() override;
   using Base::Base;
diff --git a/compiler/src/iree/compiler/Codegen/Common/ConvertUnsupportedFloatToIntBuffers.cpp b/compiler/src/iree/compiler/Codegen/Common/ConvertUnsupportedFloatToIntBuffers.cpp
index 6b316a03ab81..ae4eed040456 100644
--- a/compiler/src/iree/compiler/Codegen/Common/ConvertUnsupportedFloatToIntBuffers.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/ConvertUnsupportedFloatToIntBuffers.cpp
@@ -160,7 +160,7 @@ struct ConvertMemRefAlloc final : OpConversionPattern<memref::AllocOp> {
 
 // Tries to completely convert a generic Operation.
 // This will process attributes, result types, and nested regions.
-struct GenericTypeConversionPattern : public ConversionPattern {
+struct GenericTypeConversionPattern : ConversionPattern {
   GenericTypeConversionPattern(TypeConverter &typeConverter,
                                MLIRContext *context)
       : ConversionPattern(typeConverter, MatchAnyOpTypeTag(), 0, context) {}
diff --git a/compiler/src/iree/compiler/Codegen/Common/ConvertWorkgroupForallToPCF.cpp b/compiler/src/iree/compiler/Codegen/Common/ConvertWorkgroupForallToPCF.cpp
index aeceb0367b6b..bfa5e783c519 100644
--- a/compiler/src/iree/compiler/Codegen/Common/ConvertWorkgroupForallToPCF.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/ConvertWorkgroupForallToPCF.cpp
@@ -26,7 +26,7 @@ struct ConvertWorkgroupForall : OpRewritePattern<scf::ForallOp> {
 };
 
 struct ConvertWorkgroupForallToPCFPass final
-    : public impl::ConvertWorkgroupForallToPCFPassBase<
+    : impl::ConvertWorkgroupForallToPCFPassBase<
           ConvertWorkgroupForallToPCFPass> {
   void runOnOperation() override;
   using Base::Base;
diff --git a/compiler/src/iree/compiler/Codegen/Common/DecomposePackUnPackOps.cpp b/compiler/src/iree/compiler/Codegen/Common/DecomposePackUnPackOps.cpp
index f981bc8f5f84..5300635b7726 100644
--- a/compiler/src/iree/compiler/Codegen/Common/DecomposePackUnPackOps.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/DecomposePackUnPackOps.cpp
@@ -45,7 +45,7 @@ namespace {
 
 /// A wrapper pattern that calls linalg::lowerPack on linalg::PackOp. It lowers
 /// a linalg.pack op to tensor.pad + tensor.expand_shape + linalg.transpose ops.
-struct LowerPackPattern : public OpRewritePattern<linalg::PackOp> {
+struct LowerPackPattern : OpRewritePattern<linalg::PackOp> {
   using Base::Base;
 
   explicit LowerPackPattern(MLIRContext *context,
@@ -78,7 +78,7 @@ struct LowerPackPattern : public OpRewritePattern<linalg::PackOp> {
 /// A wrapper pattern that calls linalg::lowerUnPack on linalg::UnPackOp. It
 /// lowers a linalg.unpack op to tensor.empty + linalg.transpose +
 /// tensor.collapse_shape + tensor.extract_slice ops.
-struct LowerUnPackPattern : public OpRewritePattern<linalg::UnPackOp> {
+struct LowerUnPackPattern : OpRewritePattern<linalg::UnPackOp> {
   using Base::Base;
 
   explicit LowerUnPackPattern(MLIRContext *context,
diff --git a/compiler/src/iree/compiler/Codegen/Common/DecomposeSoftmax.cpp b/compiler/src/iree/compiler/Codegen/Common/DecomposeSoftmax.cpp
index 3e3ca38bed75..579c8e59ed9e 100644
--- a/compiler/src/iree/compiler/Codegen/Common/DecomposeSoftmax.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/DecomposeSoftmax.cpp
@@ -27,7 +27,7 @@ static bool isScalarOrTensorOfSizeOne(Type t) {
   return t.isIntOrIndexOrFloat();
 }
 
-struct FuseElementWiseGenericOps : public OpRewritePattern<linalg::GenericOp> {
+struct FuseElementWiseGenericOps : OpRewritePattern<linalg::GenericOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(linalg::GenericOp genericOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/EncodingUtils.h b/compiler/src/iree/compiler/Codegen/Common/EncodingUtils.h
index 377ccab5bd25..7f77fed53ebe 100644
--- a/compiler/src/iree/compiler/Codegen/Common/EncodingUtils.h
+++ b/compiler/src/iree/compiler/Codegen/Common/EncodingUtils.h
@@ -79,7 +79,7 @@ class MaterializeEncodingTypeConverter : public TypeConverter {
 };
 
 /// Conversion target to use for for materializing the encoding.
-struct MaterializeEncodingConversionTarget : public ConversionTarget {
+struct MaterializeEncodingConversionTarget : ConversionTarget {
   MaterializeEncodingConversionTarget(MLIRContext &context);
 };
 
diff --git a/compiler/src/iree/compiler/Codegen/Common/ExtractAddressComputation.h b/compiler/src/iree/compiler/Codegen/Common/ExtractAddressComputation.h
index 69ecb1b09d29..89f114fafd23 100644
--- a/compiler/src/iree/compiler/Codegen/Common/ExtractAddressComputation.h
+++ b/compiler/src/iree/compiler/Codegen/Common/ExtractAddressComputation.h
@@ -31,7 +31,7 @@ template <typename StoreLoadLikeOp, Value (*getSrcMemRef)(StoreLoadLikeOp),
               Value /*srcMemRef*/, ArrayRef<Value> /*indices*/),
           SmallVector<OpFoldResult> (*getViewSizeForEachDim)(
               RewriterBase & /*rewriter*/, StoreLoadLikeOp /*storeLoadOp*/)>
-struct StoreLoadLikeOpRewriter : public OpRewritePattern<StoreLoadLikeOp> {
+struct StoreLoadLikeOpRewriter : OpRewritePattern<StoreLoadLikeOp> {
   using OpRewritePattern<StoreLoadLikeOp>::OpRewritePattern;
 
   LogicalResult matchAndRewrite(StoreLoadLikeOp storeLoadLikeOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/FastMathPatterns.cpp b/compiler/src/iree/compiler/Codegen/Common/FastMathPatterns.cpp
index c8c03a0e7c21..2f9bed474313 100644
--- a/compiler/src/iree/compiler/Codegen/Common/FastMathPatterns.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/FastMathPatterns.cpp
@@ -30,7 +30,7 @@ static Value evalErfPolynomial(Value x, Value t, ArrayRef<Value> coeffs,
 // Pattern to lower math.erf to its device lib implementation
 // (from
 // https://github.com/ROCm/llvm-project/blob/amd-staging/amd/device-libs/ocml/src/erfF.cl#L11)
-struct FastErfPattern : public OpRewritePattern<math::ErfOp> {
+struct FastErfPattern : OpRewritePattern<math::ErfOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(math::ErfOp op,
diff --git a/compiler/src/iree/compiler/Codegen/Common/FlattenMemRefSubspanPass.cpp b/compiler/src/iree/compiler/Codegen/Common/FlattenMemRefSubspanPass.cpp
index 778f98394488..1eca6310be17 100644
--- a/compiler/src/iree/compiler/Codegen/Common/FlattenMemRefSubspanPass.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/FlattenMemRefSubspanPass.cpp
@@ -89,7 +89,7 @@ static bool isRankZeroOrOneMemRef(Type type) {
 }
 
 /// Flattens n-D MemRef to 1-D MemRef and allows other types.
-struct FlattenMemRefTypeConverter final : public TypeConverter {
+struct FlattenMemRefTypeConverter final : TypeConverter {
   FlattenMemRefTypeConverter() {
     // Allow all other types.
     addConversion([](Type type) -> std::optional<Type> { return type; });
@@ -150,7 +150,7 @@ static Value createTotalElementCountValue(ShapedType type,
 
 // Flattens memref allocation ops with more than 1 dimensions to 1 dimension.
 template <typename AllocOpTy>
-struct FlattenAlloc final : public OpConversionPattern<AllocOpTy> {
+struct FlattenAlloc final : OpConversionPattern<AllocOpTy> {
   using OpConversionPattern<AllocOpTy>::OpConversionPattern;
 
   LogicalResult
@@ -173,7 +173,7 @@ struct FlattenAlloc final : public OpConversionPattern<AllocOpTy> {
 };
 
 /// Flattens memref global ops with more than 1 dimensions to 1 dimension.
-struct FlattenGlobal final : public OpConversionPattern<memref::GlobalOp> {
+struct FlattenGlobal final : OpConversionPattern<memref::GlobalOp> {
   using Base::Base;
 
   static Attribute flattenAttribute(Attribute value, ShapedType newType) {
@@ -216,8 +216,7 @@ struct FlattenGlobal final : public OpConversionPattern<memref::GlobalOp> {
 };
 
 /// Flattens memref global load ops with more than 1 dimensions to 1 dimension.
-struct FlattenGetGlobal final
-    : public OpConversionPattern<memref::GetGlobalOp> {
+struct FlattenGetGlobal final : OpConversionPattern<memref::GetGlobalOp> {
   using Base::Base;
 
   LogicalResult
@@ -245,7 +244,7 @@ struct FlattenGetGlobal final
 
 /// Flattens memref subspan ops with more than 1 dimensions to 1 dimension.
 struct FlattenBindingSubspan final
-    : public OpConversionPattern<IREE::HAL::InterfaceBindingSubspanOp> {
+    : OpConversionPattern<IREE::HAL::InterfaceBindingSubspanOp> {
   using Base::Base;
 
   LogicalResult
@@ -322,8 +321,7 @@ struct FlattenBindingSubspan final
 // TODO(ravishankarm): For now just handle the case where the result is 0D
 // memref, and offset is 0. This is how void pointers are modeled. Generalize if
 // necessary.
-struct FlattenReinterpretCast
-    : public OpConversionPattern<memref::ReinterpretCastOp> {
+struct FlattenReinterpretCast : OpConversionPattern<memref::ReinterpretCastOp> {
   using Base::Base;
 
   LogicalResult
@@ -435,7 +433,7 @@ static Value linearizeIndices(Value sourceValue, ValueRange indices,
 }
 
 /// Flattens memref subspan ops with more than 1 dimensions to 1 dimension.
-struct FlattenSubView final : public OpConversionPattern<memref::SubViewOp> {
+struct FlattenSubView final : OpConversionPattern<memref::SubViewOp> {
   using Base::Base;
 
   LogicalResult
@@ -467,7 +465,7 @@ struct FlattenSubView final : public OpConversionPattern<memref::SubViewOp> {
 };
 
 /// Linearizes indices in memref.load ops.
-struct LinearizeLoadIndices final : public OpConversionPattern<memref::LoadOp> {
+struct LinearizeLoadIndices final : OpConversionPattern<memref::LoadOp> {
   using Base::Base;
 
   LogicalResult
@@ -492,7 +490,7 @@ struct LinearizeLoadIndices final : public OpConversionPattern<memref::LoadOp> {
 
 /// Linearizes indices in gpu.subgroup_mma_load_matrix ops.
 struct LinearizeMMALoadIndices final
-    : public OpConversionPattern<gpu::SubgroupMmaLoadMatrixOp> {
+    : OpConversionPattern<gpu::SubgroupMmaLoadMatrixOp> {
   using Base::Base;
 
   LogicalResult
@@ -517,8 +515,7 @@ struct LinearizeMMALoadIndices final
 };
 
 /// Linearizes indices in memref.store ops.
-struct LinearizeStoreIndices final
-    : public OpConversionPattern<memref::StoreOp> {
+struct LinearizeStoreIndices final : OpConversionPattern<memref::StoreOp> {
   using Base::Base;
 
   LogicalResult
@@ -543,7 +540,7 @@ struct LinearizeStoreIndices final
 
 /// Linearizes indices in gpu.subgroup_mma_store_matrix ops.
 struct LinearizeMMAStoreIndices final
-    : public OpConversionPattern<gpu::SubgroupMmaStoreMatrixOp> {
+    : OpConversionPattern<gpu::SubgroupMmaStoreMatrixOp> {
   using Base::Base;
 
   LogicalResult
@@ -570,7 +567,7 @@ struct LinearizeMMAStoreIndices final
 
 /// Linearizes indices in vector.transfer_read ops.
 struct LinearizeTransferReadIndices final
-    : public OpConversionPattern<vector::TransferReadOp> {
+    : OpConversionPattern<vector::TransferReadOp> {
   using Base::Base;
 
   LogicalResult
@@ -603,7 +600,7 @@ struct LinearizeTransferReadIndices final
 
 /// Linearizes indices in vector.transfer_write ops.
 struct LinearizeTransferWriteIndices final
-    : public OpConversionPattern<vector::TransferWriteOp> {
+    : OpConversionPattern<vector::TransferWriteOp> {
   using Base::Base;
 
   LogicalResult
@@ -634,7 +631,7 @@ struct LinearizeTransferWriteIndices final
 };
 
 /// Updates deallocations to the flattened allocation.
-struct FlattenDealloc final : public OpConversionPattern<memref::DeallocOp> {
+struct FlattenDealloc final : OpConversionPattern<memref::DeallocOp> {
   using Base::Base;
 
   LogicalResult
@@ -652,7 +649,7 @@ struct FlattenDealloc final : public OpConversionPattern<memref::DeallocOp> {
 
 /// Adjusts unrealized_conversion_cast ops' inputs to flattened memref values.
 struct AdjustConversionCast final
-    : public OpConversionPattern<UnrealizedConversionCastOp> {
+    : OpConversionPattern<UnrealizedConversionCastOp> {
   using Base::Base;
 
   LogicalResult
@@ -685,7 +682,7 @@ struct AdjustConversionCast final
 /// Removes MemRef reshape ops given that we'll linearize both the source and
 /// target type to the same one.
 template <typename ReshapeOpTy>
-struct FoldMemRefReshape final : public OpConversionPattern<ReshapeOpTy> {
+struct FoldMemRefReshape final : OpConversionPattern<ReshapeOpTy> {
   using OpConversionPattern<ReshapeOpTy>::OpConversionPattern;
 
   LogicalResult
@@ -723,8 +720,7 @@ struct FoldMemRefReshape final : public OpConversionPattern<ReshapeOpTy> {
 };
 
 /// Fold alignment hints.
-struct FoldAssumeAlignOp
-    : public OpConversionPattern<memref::AssumeAlignmentOp> {
+struct FoldAssumeAlignOp : OpConversionPattern<memref::AssumeAlignmentOp> {
   using Base::Base;
   LogicalResult
   matchAndRewrite(memref::AssumeAlignmentOp op, OpAdaptor adaptor,
@@ -735,7 +731,7 @@ struct FoldAssumeAlignOp
 };
 
 /// Removes memref.cast that turns static shapes into dynamic shapes.
-struct RemoveDynamicCastOp final : public OpRewritePattern<memref::CastOp> {
+struct RemoveDynamicCastOp final : OpRewritePattern<memref::CastOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(memref::CastOp castOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/FlattenMemRefs.cpp b/compiler/src/iree/compiler/Codegen/Common/FlattenMemRefs.cpp
index 51d058bd4eba..2319299e1107 100644
--- a/compiler/src/iree/compiler/Codegen/Common/FlattenMemRefs.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/FlattenMemRefs.cpp
@@ -242,7 +242,7 @@ static void replaceOp(T op, PatternRewriter &rewriter, Value flatMemref,
 }
 
 template <typename T>
-struct MemRefRewritePatternBase : public OpRewritePattern<T> {
+struct MemRefRewritePatternBase : OpRewritePattern<T> {
   using OpRewritePattern<T>::OpRewritePattern;
   LogicalResult matchAndRewrite(T op,
                                 PatternRewriter &rewriter) const override {
@@ -258,47 +258,47 @@ struct MemRefRewritePatternBase : public OpRewritePattern<T> {
   }
 };
 
-struct FlattenMemrefLoad : public MemRefRewritePatternBase<memref::LoadOp> {
+struct FlattenMemrefLoad : MemRefRewritePatternBase<memref::LoadOp> {
   using MemRefRewritePatternBase<memref::LoadOp>::MemRefRewritePatternBase;
 };
 
-struct FlattenVectorLoad : public MemRefRewritePatternBase<vector::LoadOp> {
+struct FlattenVectorLoad : MemRefRewritePatternBase<vector::LoadOp> {
   using MemRefRewritePatternBase<vector::LoadOp>::MemRefRewritePatternBase;
 };
 
-struct FlattenMemrefStore : public MemRefRewritePatternBase<memref::StoreOp> {
+struct FlattenMemrefStore : MemRefRewritePatternBase<memref::StoreOp> {
   using MemRefRewritePatternBase<memref::StoreOp>::MemRefRewritePatternBase;
 };
 
-struct FlattenVectorStore : public MemRefRewritePatternBase<vector::StoreOp> {
+struct FlattenVectorStore : MemRefRewritePatternBase<vector::StoreOp> {
   using MemRefRewritePatternBase<vector::StoreOp>::MemRefRewritePatternBase;
 };
 
 struct FlattenVectorMaskedLoad
-    : public MemRefRewritePatternBase<vector::MaskedLoadOp> {
+    : MemRefRewritePatternBase<vector::MaskedLoadOp> {
   using MemRefRewritePatternBase<
       vector::MaskedLoadOp>::MemRefRewritePatternBase;
 };
 
 struct FlattenVectorMaskedStore
-    : public MemRefRewritePatternBase<vector::MaskedStoreOp> {
+    : MemRefRewritePatternBase<vector::MaskedStoreOp> {
   using MemRefRewritePatternBase<
       vector::MaskedStoreOp>::MemRefRewritePatternBase;
 };
 
 struct FlattenVectorTransferRead
-    : public MemRefRewritePatternBase<vector::TransferReadOp> {
+    : MemRefRewritePatternBase<vector::TransferReadOp> {
   using MemRefRewritePatternBase<
       vector::TransferReadOp>::MemRefRewritePatternBase;
 };
 
 struct FlattenVectorTransferWrite
-    : public MemRefRewritePatternBase<vector::TransferWriteOp> {
+    : MemRefRewritePatternBase<vector::TransferWriteOp> {
   using MemRefRewritePatternBase<
       vector::TransferWriteOp>::MemRefRewritePatternBase;
 };
 
-struct FlattenSubview : public OpRewritePattern<memref::SubViewOp> {
+struct FlattenSubview : OpRewritePattern<memref::SubViewOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(memref::SubViewOp op,
@@ -347,7 +347,7 @@ struct FlattenSubview : public OpRewritePattern<memref::SubViewOp> {
 };
 
 struct DecomposeMemrefsPass
-    : public impl::DecomposeMemrefsPassBase<DecomposeMemrefsPass> {
+    : impl::DecomposeMemrefsPassBase<DecomposeMemrefsPass> {
   using Base::Base;
 
   void getDependentDialects(DialectRegistry &registry) const override {
diff --git a/compiler/src/iree/compiler/Codegen/Common/FoldAffineMinInDistributedLoops.cpp b/compiler/src/iree/compiler/Codegen/Common/FoldAffineMinInDistributedLoops.cpp
index 3f3ea86d8aad..29650e8d1c0e 100644
--- a/compiler/src/iree/compiler/Codegen/Common/FoldAffineMinInDistributedLoops.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/FoldAffineMinInDistributedLoops.cpp
@@ -82,7 +82,7 @@ namespace {
 /// can reuse upstream utilities to prove that the `affine.min` ops are tightly
 /// bound so that we can replace them with the tight bound.
 struct FoldAffineMinOverDistributedLoopInductionVariable final
-    : public OpRewritePattern<affine::AffineMinOp> {
+    : OpRewritePattern<affine::AffineMinOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(affine::AffineMinOp minOp,
@@ -124,7 +124,7 @@ struct FoldAffineMinOverDistributedLoopInductionVariable final
 };
 
 struct FoldAffineMinOverWorkgroupIDs final
-    : public OpRewritePattern<affine::AffineMinOp> {
+    : OpRewritePattern<affine::AffineMinOp> {
   FoldAffineMinOverWorkgroupIDs(MLIRContext *context,
                                 ArrayRef<int64_t> numWorkgroup,
                                 PatternBenefit benefit = 1)
diff --git a/compiler/src/iree/compiler/Codegen/Common/FoldSplitReductionAndWorkgroupMappingLoopsPass.cpp b/compiler/src/iree/compiler/Codegen/Common/FoldSplitReductionAndWorkgroupMappingLoopsPass.cpp
index 0b1a17e2b8ff..bb1f49ed3cff 100644
--- a/compiler/src/iree/compiler/Codegen/Common/FoldSplitReductionAndWorkgroupMappingLoopsPass.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/FoldSplitReductionAndWorkgroupMappingLoopsPass.cpp
@@ -18,7 +18,7 @@ namespace mlir::iree_compiler {
 namespace {
 
 struct FoldSplitReductionAndWorkgroupMappingLoopsPass
-    : public impl::FoldSplitReductionAndWorkgroupMappingLoopsPassBase<
+    : impl::FoldSplitReductionAndWorkgroupMappingLoopsPassBase<
           FoldSplitReductionAndWorkgroupMappingLoopsPass> {
   using Base::Base;
 
diff --git a/compiler/src/iree/compiler/Codegen/Common/ForOpCanonicalizationPass.cpp b/compiler/src/iree/compiler/Codegen/Common/ForOpCanonicalizationPass.cpp
index c188248240cc..15be4b86df88 100644
--- a/compiler/src/iree/compiler/Codegen/Common/ForOpCanonicalizationPass.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/ForOpCanonicalizationPass.cpp
@@ -21,8 +21,7 @@ namespace mlir::iree_compiler {
 
 namespace {
 
-struct CanonicalizeForOpInductionVarShape final
-    : public OpRewritePattern<scf::ForOp> {
+struct CanonicalizeForOpInductionVarShape final : OpRewritePattern<scf::ForOp> {
   using Base::Base;
 
   // Return true if it might be possible to yield the operand of `op` instead of
@@ -200,7 +199,7 @@ struct CanonicalizeForOpInductionVarShape final
 /// Those loop-carried values will be lowered into SPIR-V local variables. This
 /// pattern allows packing i4/i8/f16 values into i32 variables tightly so that
 /// we can generate shader conformant SPIR-V.
-struct PackForOpInductionVarVector final : public OpRewritePattern<scf::ForOp> {
+struct PackForOpInductionVarVector final : OpRewritePattern<scf::ForOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(scf::ForOp forOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/AMDGPULowerCoalescedDMAToGatherLDS.cpp b/compiler/src/iree/compiler/Codegen/Common/GPU/AMDGPULowerCoalescedDMAToGatherLDS.cpp
index eb2ee9451851..23bb78fca4c4 100644
--- a/compiler/src/iree/compiler/Codegen/Common/GPU/AMDGPULowerCoalescedDMAToGatherLDS.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/GPU/AMDGPULowerCoalescedDMAToGatherLDS.cpp
@@ -192,7 +192,7 @@ generateGatherIndices(OpBuilder &rewriter, Location loc,
 }
 
 struct LowerCoalescedGatherDMAPattern final
-    : public OpRewritePattern<IREE::GPU::CoalescedGatherDMAOp> {
+    : OpRewritePattern<IREE::GPU::CoalescedGatherDMAOp> {
   using Base::Base;
 
   LowerCoalescedGatherDMAPattern(MLIRContext *context,
@@ -482,7 +482,7 @@ struct LowerCoalescedGatherDMAPattern final
 /// (gather_to_lds) fails due to DMA size alignment issues.
 /// Each lane transfers one element per iteration across the subgroup.
 struct LowerCoalescedGatherDMAFallbackPattern final
-    : public OpRewritePattern<IREE::GPU::CoalescedGatherDMAOp> {
+    : OpRewritePattern<IREE::GPU::CoalescedGatherDMAOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(IREE::GPU::CoalescedGatherDMAOp dmaOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUApplyPaddingLevel.cpp b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUApplyPaddingLevel.cpp
index 1d7ee9f5733e..671b8df4d3d7 100644
--- a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUApplyPaddingLevel.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUApplyPaddingLevel.cpp
@@ -81,7 +81,7 @@ static void makePadDPS(RewriterBase &rewriter, tensor::PadOp padOp) {
                              });
 }
 
-struct MaskListener final : public RewriterBase::Listener {
+struct MaskListener final : RewriterBase::Listener {
   void notifyOperationInserted(Operation *op,
                                RewriterBase::InsertPoint previous) override {
     if (auto padOp = dyn_cast<tensor::PadOp>(op)) {
diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUBubbleResourceCasts.cpp b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUBubbleResourceCasts.cpp
index 2817810d1664..5cd2ec0baa5a 100644
--- a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUBubbleResourceCasts.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUBubbleResourceCasts.cpp
@@ -97,7 +97,7 @@ static Operation *isTriviallyProducedByReadOnlyViewLike(
 
 namespace {
 struct BubbleResourceCastPattern
-    : public OpRewritePattern<IREE::GPU::BufferResourceCastOp> {
+    : OpRewritePattern<IREE::GPU::BufferResourceCastOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(IREE::GPU::BufferResourceCastOp castOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUConvertToCoalescedDMA.cpp b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUConvertToCoalescedDMA.cpp
index 013ff0fea0d1..ddb8b6044c91 100644
--- a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUConvertToCoalescedDMA.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUConvertToCoalescedDMA.cpp
@@ -548,7 +548,7 @@ static LogicalResult createDMAInForall(scf::ForallOp threadForallOp,
 
 /// Base class for converting operations to coalesced DMA operations.
 template <typename OpTy>
-struct ConvertToCoalescedDMABase : public OpRewritePattern<OpTy> {
+struct ConvertToCoalescedDMABase : OpRewritePattern<OpTy> {
   using OpRewritePattern<OpTy>::OpRewritePattern;
 
   LogicalResult matchAndRewrite(OpTy op,
@@ -579,8 +579,7 @@ struct ConvertToCoalescedDMABase : public OpRewritePattern<OpTy> {
                                                             OpTy op) const = 0;
 };
 
-struct ConvertCopyToCoalescedDMA
-    : public ConvertToCoalescedDMABase<linalg::CopyOp> {
+struct ConvertCopyToCoalescedDMA : ConvertToCoalescedDMABase<linalg::CopyOp> {
   using ConvertToCoalescedDMABase::ConvertToCoalescedDMABase;
 
 protected:
@@ -597,8 +596,7 @@ struct ConvertCopyToCoalescedDMA
 
 /// Pattern to convert tensor.pad fusion cases directly without requiring
 /// warp-mapped forall parent.
-struct ConvertPadFusionCopyToCoalescedDMA
-    : public OpRewritePattern<linalg::CopyOp> {
+struct ConvertPadFusionCopyToCoalescedDMA : OpRewritePattern<linalg::CopyOp> {
   using OpRewritePattern::OpRewritePattern;
 
   LogicalResult matchAndRewrite(linalg::CopyOp copyOp,
@@ -653,7 +651,7 @@ struct ConvertPadFusionCopyToCoalescedDMA
 };
 
 struct ConvertGatherToCoalescedDMA
-    : public OpRewritePattern<IREE::LinalgExt::GatherOp> {
+    : OpRewritePattern<IREE::LinalgExt::GatherOp> {
   using OpRewritePattern<IREE::LinalgExt::GatherOp>::OpRewritePattern;
 
   LogicalResult matchAndRewrite(IREE::LinalgExt::GatherOp gatherOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUFuseSubgroupConsumers.cpp b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUFuseSubgroupConsumers.cpp
index 44ad2dece880..e35bc56c067f 100644
--- a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUFuseSubgroupConsumers.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUFuseSubgroupConsumers.cpp
@@ -27,8 +27,7 @@ using namespace IREE::PCF;
 namespace {
 
 /// Pattern that fuses tilable consumers into subgroup-scoped pcf.generic ops.
-struct FuseConsumerIntoSubgroupGenericOp final
-    : public OpRewritePattern<GenericOp> {
+struct FuseConsumerIntoSubgroupGenericOp final : OpRewritePattern<GenericOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(GenericOp genericOp,
@@ -64,7 +63,7 @@ struct FuseConsumerIntoSubgroupGenericOp final
 /// Pattern that fuses tensor.extract_slice consumers into subgroup-scoped
 /// pcf.generic ops.
 struct FuseExtractSliceIntoSubgroupGenericOp final
-    : public OpRewritePattern<tensor::ExtractSliceOp> {
+    : OpRewritePattern<tensor::ExtractSliceOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(tensor::ExtractSliceOp extractSliceOp,
@@ -91,8 +90,7 @@ struct FuseExtractSliceIntoSubgroupGenericOp final
 };
 
 struct GPUFuseSubgroupConsumersPass final
-    : public impl::GPUFuseSubgroupConsumersPassBase<
-          GPUFuseSubgroupConsumersPass> {
+    : impl::GPUFuseSubgroupConsumersPassBase<GPUFuseSubgroupConsumersPass> {
   void runOnOperation() override {
     RewritePatternSet patterns(&getContext());
     patterns.add<FuseConsumerIntoSubgroupGenericOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUHeuristics.h b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUHeuristics.h
index c4fe42ae2c31..2749ed21536e 100644
--- a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUHeuristics.h
+++ b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUHeuristics.h
@@ -60,7 +60,7 @@ struct GPUMatmulShapeType {
 };
 
 /// Struct containing information about a GPU MMA intrinsic type.
-struct GPUIntrinsicType : public GPUMatmulShapeType {
+struct GPUIntrinsicType : GPUMatmulShapeType {
   IREE::Codegen::InnerTileDescAttrInterface mmaKind;
   GPUIntrinsicType(int64_t m, int64_t n, int64_t k, Type a, Type b, Type c,
                    IREE::Codegen::InnerTileDescAttrInterface kind)
diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUPatterns.cpp b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUPatterns.cpp
index 18e8c015d34c..01e839eae20e 100644
--- a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUPatterns.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUPatterns.cpp
@@ -44,7 +44,7 @@ namespace {
 /// %3 = vector.transpose %2, [1, 0, 2]
 ///      : vector<1x16x8xf32> to vector<16x1x8xf32>
 /// ```
-struct FlattenTransferReadOp : public OpRewritePattern<vector::TransferReadOp> {
+struct FlattenTransferReadOp : OpRewritePattern<vector::TransferReadOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(vector::TransferReadOp transferReadOp,
@@ -160,7 +160,7 @@ struct FlattenTransferReadOp : public OpRewritePattern<vector::TransferReadOp> {
 // Merges transpose op into the transfer read op. Transpose are not supported on
 // MMA types but MMA load can transpose the matrix when loading.
 struct CombineTransferReadOpBroadcast final
-    : public OpRewritePattern<vector::BroadcastOp> {
+    : OpRewritePattern<vector::BroadcastOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(vector::BroadcastOp op,
@@ -255,7 +255,7 @@ struct RemoveUnitDimStretchingBroadcast final
 // A `dealloc` is converted into a call to `free` on the underlying data buffer.
 // The memref descriptor being an SSA value, there is no need to clean it up
 // in any way.
-struct DropSharedMemoryDeallocOp : public OpRewritePattern<memref::DeallocOp> {
+struct DropSharedMemoryDeallocOp : OpRewritePattern<memref::DeallocOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(memref::DeallocOp op,
diff --git a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUVectorDistribution.cpp b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUVectorDistribution.cpp
index d4ad4cb9cce7..c58fc211b3e5 100644
--- a/compiler/src/iree/compiler/Codegen/Common/GPU/GPUVectorDistribution.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/GPU/GPUVectorDistribution.cpp
@@ -40,7 +40,7 @@ struct VectorDistributionRewriter : PatternRewriter {
 };
 
 /// Custom listener to store emitted ops that needs to be distributed.
-struct VectorDistributionListener : public RewriterBase::Listener {
+struct VectorDistributionListener : RewriterBase::Listener {
   bool hasOpsToBeDistributed() { return !toBeDistributed.empty(); }
 
   void clearOpsToBeDistributed() { return toBeDistributed.clear(); }
diff --git a/compiler/src/iree/compiler/Codegen/Common/IREEExpandStridedMetadata.cpp b/compiler/src/iree/compiler/Codegen/Common/IREEExpandStridedMetadata.cpp
index a02432b02be6..d790703a37c7 100644
--- a/compiler/src/iree/compiler/Codegen/Common/IREEExpandStridedMetadata.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/IREEExpandStridedMetadata.cpp
@@ -154,7 +154,7 @@ namespace {
 /// interface binding. This preserves SSA links through buffer binding
 /// optimizations that update offsets.
 struct ConvertMemRefExtractMetadataToIREECodegen
-    : public OpRewritePattern<memref::ExtractStridedMetadataOp> {
+    : OpRewritePattern<memref::ExtractStridedMetadataOp> {
   using OpRewritePattern<memref::ExtractStridedMetadataOp>::OpRewritePattern;
   LogicalResult matchAndRewrite(memref::ExtractStridedMetadataOp op,
                                 PatternRewriter &rewriter) const override {
@@ -169,7 +169,7 @@ struct ConvertMemRefExtractMetadataToIREECodegen
 };
 
 struct ResolveExtractMetadataFromHalInterfaceBindingSubspan
-    : public OpRewritePattern<IREE::Codegen::ExtractStridedMetadataOp> {
+    : OpRewritePattern<IREE::Codegen::ExtractStridedMetadataOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(IREE::Codegen::ExtractStridedMetadataOp op,
                                 PatternRewriter &rewriter) const override {
@@ -280,7 +280,7 @@ struct ResolveExtractMetadataFromHalInterfaceBindingSubspan
 /// a HAL binding (those are resolved by
 /// ResolveExtractMetadataFromHalInterfaceBindingSubspan).
 struct ConvertIREECodegenExtractMetadataToMemRef
-    : public OpRewritePattern<IREE::Codegen::ExtractStridedMetadataOp> {
+    : OpRewritePattern<IREE::Codegen::ExtractStridedMetadataOp> {
   using OpRewritePattern<
       IREE::Codegen::ExtractStridedMetadataOp>::OpRewritePattern;
   LogicalResult matchAndRewrite(IREE::Codegen::ExtractStridedMetadataOp op,
diff --git a/compiler/src/iree/compiler/Codegen/Common/IREEInjectAssumeAlignment.cpp b/compiler/src/iree/compiler/Codegen/Common/IREEInjectAssumeAlignment.cpp
index 85ac629bf3ea..24caa5f6f353 100644
--- a/compiler/src/iree/compiler/Codegen/Common/IREEInjectAssumeAlignment.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/IREEInjectAssumeAlignment.cpp
@@ -18,7 +18,7 @@ namespace mlir::iree_compiler {
 
 namespace {
 struct InjectAssumeAlignmentForSubspanOp
-    : public OpRewritePattern<IREE::HAL::InterfaceBindingSubspanOp> {
+    : OpRewritePattern<IREE::HAL::InterfaceBindingSubspanOp> {
   using OpRewritePattern<
       IREE::HAL::InterfaceBindingSubspanOp>::OpRewritePattern;
   LogicalResult matchAndRewrite(IREE::HAL::InterfaceBindingSubspanOp op,
@@ -26,8 +26,7 @@ struct InjectAssumeAlignmentForSubspanOp
 };
 
 struct IREEInjectAssumeAlignmentPass final
-    : public impl::IREEInjectAssumeAlignmentPassBase<
-          IREEInjectAssumeAlignmentPass> {
+    : impl::IREEInjectAssumeAlignmentPassBase<IREEInjectAssumeAlignmentPass> {
   void runOnOperation() override;
   using Base::Base;
 };
diff --git a/compiler/src/iree/compiler/Codegen/Common/IREELoopInvariantCodeMotion.cpp b/compiler/src/iree/compiler/Codegen/Common/IREELoopInvariantCodeMotion.cpp
index 07d442ca4479..22e650751a51 100644
--- a/compiler/src/iree/compiler/Codegen/Common/IREELoopInvariantCodeMotion.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/IREELoopInvariantCodeMotion.cpp
@@ -14,7 +14,7 @@ namespace mlir::iree_compiler {
 namespace {
 /// IREE loop invariant code motion (LICM) pass.
 struct IREELoopInvariantCodeMotionPass
-    : public impl::IREELoopInvariantCodeMotionPassBase<
+    : impl::IREELoopInvariantCodeMotionPassBase<
           IREELoopInvariantCodeMotionPass> {
   void runOnOperation() override;
 };
diff --git a/compiler/src/iree/compiler/Codegen/Common/MaterializeEncodingPatterns.cpp b/compiler/src/iree/compiler/Codegen/Common/MaterializeEncodingPatterns.cpp
index ff147917b803..dc255e9e7198 100644
--- a/compiler/src/iree/compiler/Codegen/Common/MaterializeEncodingPatterns.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/MaterializeEncodingPatterns.cpp
@@ -145,7 +145,7 @@ namespace {
 /// Pattern to materialize the encoding for `hal.interface.binding.subspan`
 /// operations.
 struct MaterializeInterfaceBindingEncoding
-    : public OpConversionPattern<IREE::HAL::InterfaceBindingSubspanOp> {
+    : OpConversionPattern<IREE::HAL::InterfaceBindingSubspanOp> {
   using OpConversionPattern<
       IREE::HAL::InterfaceBindingSubspanOp>::OpConversionPattern;
 
@@ -214,7 +214,7 @@ struct MaterializeInterfaceBindingEncoding
 /// Pattern to convert `iree_tensor_ext.dispatch.tensor.load` operation when
 /// materializing the encoding.
 struct MaterializeTensorExtDispatchTensorLoadOp
-    : public OpConversionPattern<IREE::TensorExt::DispatchTensorLoadOp> {
+    : OpConversionPattern<IREE::TensorExt::DispatchTensorLoadOp> {
   using OpConversionPattern<
       IREE::TensorExt::DispatchTensorLoadOp>::OpConversionPattern;
 
@@ -249,7 +249,7 @@ struct MaterializeTensorExtDispatchTensorLoadOp
 /// Pattern to convert `iree_tensor_ext.dispatch.tensor.store` operation when
 /// materializing the encoding.
 struct MaterializeTensorExtDispatchTensorStoreOp
-    : public OpConversionPattern<IREE::TensorExt::DispatchTensorStoreOp> {
+    : OpConversionPattern<IREE::TensorExt::DispatchTensorStoreOp> {
   using OpConversionPattern<
       IREE::TensorExt::DispatchTensorStoreOp>::OpConversionPattern;
 
@@ -313,7 +313,7 @@ static Value generateEncodingTransferOps(RewriterBase &rewriter, Value src,
 /// Pattern to convert `iree_tensor_ext.dispatch.tensor.load` operation when
 /// materializing the encoding.
 struct DecomposeMismatchEncodingTensorLoadOp
-    : public OpRewritePattern<IREE::TensorExt::DispatchTensorLoadOp> {
+    : OpRewritePattern<IREE::TensorExt::DispatchTensorLoadOp> {
   using OpRewritePattern<
       IREE::TensorExt::DispatchTensorLoadOp>::OpRewritePattern;
 
@@ -380,7 +380,7 @@ struct DecomposeMismatchEncodingTensorLoadOp
 /// Pattern to convert `iree_tensor_ext.dispatch.tensor.store` operation when
 /// materializing the encoding.
 struct DecomposeMismatchEncodingTensorStoreOp
-    : public OpRewritePattern<IREE::TensorExt::DispatchTensorStoreOp> {
+    : OpRewritePattern<IREE::TensorExt::DispatchTensorStoreOp> {
   using OpRewritePattern<
       IREE::TensorExt::DispatchTensorStoreOp>::OpRewritePattern;
 
@@ -452,7 +452,7 @@ struct DecomposeMismatchEncodingTensorStoreOp
 
 /// Generic pattern to convert an operation.
 template <typename OpTy>
-struct MaterializeOperation : public OpConversionPattern<OpTy> {
+struct MaterializeOperation : OpConversionPattern<OpTy> {
   using OpConversionPattern<OpTy>::OpConversionPattern;
 
   LogicalResult
@@ -472,7 +472,7 @@ struct MaterializeOperation : public OpConversionPattern<OpTy> {
 };
 
 struct MaterializeOptimizationBarrierOp
-    : public OpConversionPattern<IREE::Util::OptimizationBarrierOp> {
+    : OpConversionPattern<IREE::Util::OptimizationBarrierOp> {
   using OpConversionPattern<
       IREE::Util::OptimizationBarrierOp>::OpConversionPattern;
 
@@ -512,7 +512,7 @@ getReassociationIndices(int outerDims,
 /// Convert iree_linalg_ext.set_encoding op to pack + tile swizzling ops. We use
 /// expand_shape + linalg.transpose to represent a tile swizzling op.
 struct SetEncodingOpLoweringConversion
-    : public OpConversionPattern<IREE::Encoding::SetEncodingOp> {
+    : OpConversionPattern<IREE::Encoding::SetEncodingOp> {
   using Base::Base;
 
   LogicalResult
@@ -576,7 +576,7 @@ struct SetEncodingOpLoweringConversion
 };
 
 struct UnsetEncodingOpLoweringConversion
-    : public OpConversionPattern<IREE::Encoding::UnsetEncodingOp> {
+    : OpConversionPattern<IREE::Encoding::UnsetEncodingOp> {
   using OpConversionPattern<
       IREE::Encoding::UnsetEncodingOp>::OpConversionPattern;
 
@@ -677,8 +677,7 @@ static bool isRankedTensorTypeWithEncoding(Type type) {
   return rankedTensorType.getEncoding() ? true : false;
 }
 
-struct MaterializeFuncReturnOp final
-    : public OpConversionPattern<func::ReturnOp> {
+struct MaterializeFuncReturnOp final : OpConversionPattern<func::ReturnOp> {
   using Base::Base;
   LogicalResult
   matchAndRewrite(func::ReturnOp op, OpAdaptor adaptor,
diff --git a/compiler/src/iree/compiler/Codegen/Common/MemrefCopyToLinalg.cpp b/compiler/src/iree/compiler/Codegen/Common/MemrefCopyToLinalg.cpp
index f1c85625e0a5..a97bf986d28e 100644
--- a/compiler/src/iree/compiler/Codegen/Common/MemrefCopyToLinalg.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/MemrefCopyToLinalg.cpp
@@ -17,7 +17,7 @@ namespace mlir::iree_compiler {
 #include "iree/compiler/Codegen/Common/Passes.h.inc"
 
 namespace {
-struct MemrefCopyOpToLinalg : public OpRewritePattern<memref::CopyOp> {
+struct MemrefCopyOpToLinalg : OpRewritePattern<memref::CopyOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(memref::CopyOp copyOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/PatchFuncOps.cpp b/compiler/src/iree/compiler/Codegen/Common/PatchFuncOps.cpp
index 42fa1aef977f..3a75f87a10e9 100644
--- a/compiler/src/iree/compiler/Codegen/Common/PatchFuncOps.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/PatchFuncOps.cpp
@@ -46,7 +46,7 @@ static LogicalResult getMatchedFuncOp(StringRef fileName,
 }
 
 namespace {
-struct PatchFuncOpsPass : public impl::PatchFuncOpsPassBase<PatchFuncOpsPass> {
+struct PatchFuncOpsPass : impl::PatchFuncOpsPassBase<PatchFuncOpsPass> {
   void getDependentDialects(DialectRegistry &registry) const override {
     registry.insert<IREE::Codegen::IREECodegenDialect>();
   }
diff --git a/compiler/src/iree/compiler/Codegen/Common/PropagateConstantOffsets.cpp b/compiler/src/iree/compiler/Codegen/Common/PropagateConstantOffsets.cpp
index dd4ad8651fae..bf7386c1d759 100644
--- a/compiler/src/iree/compiler/Codegen/Common/PropagateConstantOffsets.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/PropagateConstantOffsets.cpp
@@ -20,8 +20,7 @@ namespace mlir::iree_compiler {
 
 namespace {
 struct PropagateConstantOffsetsPass final
-    : public impl::PropagateConstantOffsetsPassBase<
-          PropagateConstantOffsetsPass> {
+    : impl::PropagateConstantOffsetsPassBase<PropagateConstantOffsetsPass> {
   using Base::Base;
   void runOnOperation() override;
 };
diff --git a/compiler/src/iree/compiler/Codegen/Common/RematerializeParallelOps.cpp b/compiler/src/iree/compiler/Codegen/Common/RematerializeParallelOps.cpp
index 1a62e2a5cd30..20ecc95343e1 100644
--- a/compiler/src/iree/compiler/Codegen/Common/RematerializeParallelOps.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/RematerializeParallelOps.cpp
@@ -34,8 +34,7 @@ static bool hasDirectWriteResult(Operation *op) {
 
 /// Rematerialize all parallel elementwise operations into its users within a
 /// `flow.dispatch.region`.
-struct RematerializeParallelOpsPattern
-    : public OpRewritePattern<linalg::GenericOp> {
+struct RematerializeParallelOpsPattern : OpRewritePattern<linalg::GenericOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(linalg::GenericOp genericOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/ReplaceSlowMinMaxOps.cpp b/compiler/src/iree/compiler/Codegen/Common/ReplaceSlowMinMaxOps.cpp
index e867b7937642..ef73ae753e15 100644
--- a/compiler/src/iree/compiler/Codegen/Common/ReplaceSlowMinMaxOps.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/ReplaceSlowMinMaxOps.cpp
@@ -18,7 +18,7 @@ namespace {
 
 template <class SlowMinMaxOp, class FastMinMaxOp>
 struct ReplaceSlowWithFastMinMaxOpPattern final
-    : public OpRewritePattern<SlowMinMaxOp> {
+    : OpRewritePattern<SlowMinMaxOp> {
   using OpRewritePattern<SlowMinMaxOp>::OpRewritePattern;
 
   LogicalResult matchAndRewrite(SlowMinMaxOp slowOp,
@@ -34,7 +34,7 @@ struct ReplaceSlowWithFastMinMaxOpPattern final
 
 template <class SlowReductionOp>
 struct ReplaceSlowWithFastReductionMinMaxOpPattern final
-    : public OpRewritePattern<SlowReductionOp> {
+    : OpRewritePattern<SlowReductionOp> {
   using OpRewritePattern<SlowReductionOp>::OpRewritePattern;
 
   LogicalResult matchAndRewrite(SlowReductionOp slowReductionOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/ResolveSwizzleHints.cpp b/compiler/src/iree/compiler/Codegen/Common/ResolveSwizzleHints.cpp
index b6f5994755e5..8df1a1bd8a20 100644
--- a/compiler/src/iree/compiler/Codegen/Common/ResolveSwizzleHints.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/ResolveSwizzleHints.cpp
@@ -22,7 +22,7 @@ namespace mlir::iree_compiler {
 
 namespace {
 struct ResolveSwizzleHintsPass final
-    : public impl::ResolveSwizzleHintsPassBase<ResolveSwizzleHintsPass> {
+    : impl::ResolveSwizzleHintsPassBase<ResolveSwizzleHintsPass> {
   using Base::Base;
   void runOnOperation() override;
 };
diff --git a/compiler/src/iree/compiler/Codegen/Common/TensorToVectorVectorizePad.cpp b/compiler/src/iree/compiler/Codegen/Common/TensorToVectorVectorizePad.cpp
index 1f41ff706aa5..568d57c2a2e8 100644
--- a/compiler/src/iree/compiler/Codegen/Common/TensorToVectorVectorizePad.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/TensorToVectorVectorizePad.cpp
@@ -77,8 +77,7 @@ namespace {
 /// %init = tensor.empty() : tensor<1x2x2x3xf32>
 /// %pad = vector.transfer_write %insert11, %init
 /// ```
-struct VectorizePadWithConditions final
-    : public OpRewritePattern<tensor::PadOp> {
+struct VectorizePadWithConditions final : OpRewritePattern<tensor::PadOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(tensor::PadOp padOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/TestPartitionableLoopsInterface.cpp b/compiler/src/iree/compiler/Codegen/Common/TestPartitionableLoopsInterface.cpp
index cfee5863b8f8..fa899c9bcd13 100644
--- a/compiler/src/iree/compiler/Codegen/Common/TestPartitionableLoopsInterface.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/TestPartitionableLoopsInterface.cpp
@@ -25,7 +25,7 @@ namespace {
 /// the value has zeros for non-partitionable loops and 1 for partitionable
 /// loops.
 struct TestPartitionableLoopsInterfacePattern
-    : public OpInterfaceRewritePattern<PartitionableLoopsInterface> {
+    : OpInterfaceRewritePattern<PartitionableLoopsInterface> {
   using OpInterfaceRewritePattern<
       PartitionableLoopsInterface>::OpInterfaceRewritePattern;
 
diff --git a/compiler/src/iree/compiler/Codegen/Common/TileDispatchUsingForall.cpp b/compiler/src/iree/compiler/Codegen/Common/TileDispatchUsingForall.cpp
index 6e7005a67a12..d6b4d6e2bc85 100644
--- a/compiler/src/iree/compiler/Codegen/Common/TileDispatchUsingForall.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/TileDispatchUsingForall.cpp
@@ -35,7 +35,7 @@ namespace mlir::iree_compiler {
 namespace {
 
 struct TileAndDistributeToWorkgroupsUsingForallOpPass final
-    : public impl::TileAndDistributeToWorkgroupsUsingForallOpPassBase<
+    : impl::TileAndDistributeToWorkgroupsUsingForallOpPassBase<
           TileAndDistributeToWorkgroupsUsingForallOpPass> {
   explicit TileAndDistributeToWorkgroupsUsingForallOpPass(
       bool transposeWorkgroup) {
diff --git a/compiler/src/iree/compiler/Codegen/Common/TileLargeTensors.cpp b/compiler/src/iree/compiler/Codegen/Common/TileLargeTensors.cpp
index 7320283ead89..59e1bf7b7f12 100644
--- a/compiler/src/iree/compiler/Codegen/Common/TileLargeTensors.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/TileLargeTensors.cpp
@@ -21,7 +21,7 @@ namespace mlir::iree_compiler {
 namespace {
 
 struct TileLargeTensorsPass final
-    : public impl::TileLargeTensorsPassBase<TileLargeTensorsPass> {
+    : impl::TileLargeTensorsPassBase<TileLargeTensorsPass> {
   using Base::Base;
   void runOnOperation() override;
 };
diff --git a/compiler/src/iree/compiler/Codegen/Common/TransformExtensions/CommonExtensions.cpp b/compiler/src/iree/compiler/Codegen/Common/TransformExtensions/CommonExtensions.cpp
index f4b1a4648082..07ce4828add7 100644
--- a/compiler/src/iree/compiler/Codegen/Common/TransformExtensions/CommonExtensions.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/TransformExtensions/CommonExtensions.cpp
@@ -870,7 +870,7 @@ static IREEOneShotBufferizationOptions getBufferizationOptions() {
 
 namespace {
 /// Pattern to rewrite tensor.empty to tensor.alloc.
-struct EmptyTensorLoweringPattern : public OpRewritePattern<tensor::EmptyOp> {
+struct EmptyTensorLoweringPattern : OpRewritePattern<tensor::EmptyOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(tensor::EmptyOp op,
diff --git a/compiler/src/iree/compiler/Codegen/Common/Transforms.cpp b/compiler/src/iree/compiler/Codegen/Common/Transforms.cpp
index ddb3eee3b87c..bab6bfc63623 100644
--- a/compiler/src/iree/compiler/Codegen/Common/Transforms.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/Transforms.cpp
@@ -118,7 +118,7 @@ void populateFuseTilableForallConsumersPattern(RewritePatternSet &patterns) {
 namespace {
 
 struct FoldRelayoutOpIntoMapStorePattern
-    : public OpRewritePattern<IREE::LinalgExt::MapStoreOp> {
+    : OpRewritePattern<IREE::LinalgExt::MapStoreOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(IREE::LinalgExt::MapStoreOp mapStoreOp,
@@ -140,7 +140,7 @@ struct FoldRelayoutOpIntoMapStorePattern
 };
 
 struct FoldPadOpIntoMapStorePattern
-    : public OpRewritePattern<IREE::LinalgExt::MapStoreOp> {
+    : OpRewritePattern<IREE::LinalgExt::MapStoreOp> {
   using Base::Base;
   FoldPadOpIntoMapStorePattern(MLIRContext *context,
                                PadDistributionConfigFn configFn,
@@ -335,7 +335,7 @@ swapExpandShapeWithSlice(RewriterBase &rewriter,
 namespace {
 
 struct SwapExpandShapeWithSlicePattern
-    : public OpRewritePattern<tensor::ExtractSliceOp> {
+    : OpRewritePattern<tensor::ExtractSliceOp> {
   SwapExpandShapeWithSlicePattern(MLIRContext *context,
                                   linalg::ControlFusionFn controlFn,
                                   PatternBenefit benefit = 1)
@@ -811,7 +811,7 @@ swapCollapseShapeWithSlice(RewriterBase &rewriter,
 namespace {
 
 struct SwapCollapseShapeWithSlicePattern
-    : public OpRewritePattern<tensor::ExtractSliceOp> {
+    : OpRewritePattern<tensor::ExtractSliceOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(tensor::ExtractSliceOp sliceOp,
@@ -842,7 +842,7 @@ void populateSwapExtractWithCollapsePattern(RewritePatternSet &patterns) {
 namespace {
 
 struct RemoveOptimizationBarrier final
-    : public OpRewritePattern<IREE::Util::OptimizationBarrierOp> {
+    : OpRewritePattern<IREE::Util::OptimizationBarrierOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(IREE::Util::OptimizationBarrierOp barrierOp,
diff --git a/compiler/src/iree/compiler/Codegen/Common/TypePropagationPass.cpp b/compiler/src/iree/compiler/Codegen/Common/TypePropagationPass.cpp
index 2f0a34250b24..3b7b0549b336 100644
--- a/compiler/src/iree/compiler/Codegen/Common/TypePropagationPass.cpp
+++ b/compiler/src/iree/compiler/Codegen/Common/TypePropagationPass.cpp
@@ -115,7 +115,7 @@ Value materializeAsConvertElementType(OpBuilder &builder, Type type,
 }
 
 /// Type converter to use for type propagation.
-struct TypePropagationTypeConverter : public TypeConverter {
+struct TypePropagationTypeConverter : TypeConverter {
   TypePropagationTypeConverter() {
     addConversion([](Type t) {
       auto convertedType = getLegalizedType(t);
@@ -128,7 +128,7 @@ struct TypePropagationTypeConverter : public TypeConverter {
 };
 
 /// Type converter used to drop encodings that need no materialization.
-struct DropEncodingTypeConverter : public TypeConverter {
+struct DropEncodingTypeConverter : TypeConverter {
   DropEncodingTypeConverter() {
     addConversion([](Type t) -> Type {
       if (auto dispatchTensor =
@@ -148,14 +148,13 @@ struct DropEncodingTypeConverter : public TypeConverter {
 
 /// Base class for patterns that handle individual operations.
 template <typename T>
-struct TypePropagationPattern : public OpConversionPattern<T> {
+struct TypePropagationPattern : OpConversionPattern<T> {
   TypePropagationPattern(TypeConverter &typeConverter, MLIRContext *context)
       : OpConversionPattern<T>(typeConverter, context, 100) {}
 };
 
 /// Type conversion for arith.constant operands.
-struct ConstantOpTypeConversion
-    : public TypePropagationPattern<arith::ConstantOp> {
+struct ConstantOpTypeConversion : TypePropagationPattern<arith::ConstantOp> {
   using TypePropagationPattern<arith::ConstantOp>::TypePropagationPattern;
 
   LogicalResult
@@ -197,7 +196,7 @@ struct ConstantOpTypeConversion
 /// here cause the region of the operation cannot be cloned. Instead create
 /// a new operation with the operands of the correct type.
 template <typename OpTy>
-struct NamedOpTypePropagation : public TypePropagationPattern<OpTy> {
+struct NamedOpTypePropagation : TypePropagationPattern<OpTy> {
   using TypePropagationPattern<OpTy>::TypePropagationPattern;
 
   LogicalResult
@@ -221,8 +220,7 @@ struct NamedOpTypePropagation : public TypePropagationPattern<OpTy> {
 /// - Convert corresponding basic block argument type and introduce element
 /// conversion ops to get back the original type.
 /// - Convert the result type if the `outs` operand has changed.
-struct GenericOpTypePropagation
-    : public TypePropagationPattern<linalg::GenericOp> {
+struct GenericOpTypePropagation : TypePropagationPattern<linalg::GenericOp> {
   using TypePropagationPattern<linalg::GenericOp>::TypePropagationPattern;
 
   LogicalResult
@@ -324,8 +322,7 @@ struct GenericOpTypePropagation
 };
 
 /// Legalizes `linalg.fill` operation.
-struct LinalgFillTypePropagation
-    : public TypePropagationPattern<linalg::FillOp> {
+struct LinalgFillTypePropagation : TypePropagationPattern<linalg::FillOp> {
   using TypePropagationPattern<linalg::FillOp>::TypePropagationPattern;
 
   LogicalResult
@@ -351,7 +348,7 @@ struct LinalgFillTypePropagation
 
 /// Pattern to legalize `tensor.extract` operations.
 struct TensorExtractTypePropagation
-    : public TypePropagationPattern<tensor::ExtractOp> {
+    : TypePropagationPattern<tensor::ExtractOp> {
   using TypePropagationPattern<tensor::ExtractOp>::TypePropagationPattern;
 
   LogicalResult
@@ -486,7 +483,7 @@ struct IREELinalgExtSortTypePropagation
 /// Simple rewrite pattern that just forwards the source as the result if the
 /// result type is not legal (but source type is)
 template <typename OpTy>
-struct ForwardSourceType : public TypePropagationPattern<OpTy> {
+struct ForwardSourceType : TypePropagationPattern<OpTy> {
   using TypePropagationPattern<OpTy>::TypePropagationPattern;
 
   LogicalResult
@@ -504,7 +501,7 @@ struct ForwardSourceType : public TypePropagationPattern<OpTy> {
 
 /// Rewrite pattern to replace the element type (if it is not legal) with the
 /// legal element type.
-struct LegalizeResultElementType : public ConversionPattern {
+struct LegalizeResultElementType : ConversionPattern {
   LegalizeResultElementType(TypeConverter &typeConverter, MLIRContext *context)
       : ConversionPattern(typeConverter, MatchAnyOpTypeTag(), /*benefit=*/1,
                           context) {}
@@ -557,7 +554,7 @@ struct LegalizeResultElementType : public ConversionPattern {
 // Rewrite pattern for converting the signature of all basic blocks in the
 // top-level operation.
 template <typename OpTy>
-struct LegalizeBasicBlocks : public TypePropagationPattern<OpTy> {
+struct LegalizeBasicBlocks : TypePropagationPattern<OpTy> {
   using TypePropagationPattern<OpTy>::TypePropagationPattern;
 
   LogicalResult
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/CPU/IR/IREECPUDialect.cpp b/compiler/src/iree/compiler/Codegen/Dialect/CPU/IR/IREECPUDialect.cpp
index 3fe7745d62aa..941aff5b64e9 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/CPU/IR/IREECPUDialect.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/CPU/IR/IREECPUDialect.cpp
@@ -12,7 +12,7 @@
 
 namespace mlir::iree_compiler::IREE::CPU {
 
-struct IREECPUDialectOpAsmInterface : public OpAsmDialectInterface {
+struct IREECPUDialectOpAsmInterface : OpAsmDialectInterface {
   using OpAsmDialectInterface::OpAsmDialectInterface;
   AliasResult getAlias(Attribute attr, raw_ostream &os) const override {
     if (isa<IREE::CPU::LoweringConfigAttr>(attr)) {
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenDialect.cpp b/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenDialect.cpp
index 431fe3c8c6de..88e705ba9bfb 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenDialect.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenDialect.cpp
@@ -21,7 +21,7 @@
 
 namespace mlir::iree_compiler::IREE::Codegen {
 
-struct IREECodegenDialectOpAsmInterface : public OpAsmDialectInterface {
+struct IREECodegenDialectOpAsmInterface : OpAsmDialectInterface {
   using OpAsmDialectInterface::OpAsmDialectInterface;
   AliasResult getAlias(Attribute attr, raw_ostream &os) const override {
     if (isa<TranslationInfoAttr>(attr)) {
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/UKernelOps.cpp b/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/UKernelOps.cpp
index b16fcf2738fe..aec49271f600 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/UKernelOps.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/Codegen/IR/UKernelOps.cpp
@@ -295,7 +295,7 @@ namespace {
 
 template <typename OpTy>
 struct UKernelOpsBufferizationInterface
-    : public bufferization::DstBufferizableOpInterfaceExternalModel<
+    : bufferization::DstBufferizableOpInterfaceExternalModel<
           UKernelOpsBufferizationInterface<OpTy>, OpTy> {
   LogicalResult bufferize(Operation *op, RewriterBase &rewriter,
                           const bufferization::BufferizationOptions &options,
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/Codegen/Transforms/ReshapeFusion.cpp b/compiler/src/iree/compiler/Codegen/Dialect/Codegen/Transforms/ReshapeFusion.cpp
index f216e054b92a..899038fb436f 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/Codegen/Transforms/ReshapeFusion.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/Codegen/Transforms/ReshapeFusion.cpp
@@ -191,7 +191,7 @@ static InnerTiledOp expandInnerTiledOp(
 ///   %result = inner_tiled ins(%src, ...) outs(%expanded_out)
 ///   %collapsed_result = tensor.collapse_shape %result [[0, 1], ...]
 struct FoldProducerCollapseShapeWithInnerTiled
-    : public OpRewritePattern<tensor::CollapseShapeOp> {
+    : OpRewritePattern<tensor::CollapseShapeOp> {
   FoldProducerCollapseShapeWithInnerTiled(MLIRContext *context,
                                           linalg::ControlFusionFn controlFn,
                                           PatternBenefit benefit = 1)
@@ -248,7 +248,7 @@ struct FoldProducerCollapseShapeWithInnerTiled
 ///   %expanded_out = tensor.expand_shape %out [[0, 1], ...]
 ///   %result = inner_tiled ins(%expanded_lhs, ...) outs(%expanded_out)
 struct FoldConsumerExpandShapeWithInnerTiled
-    : public OpRewritePattern<tensor::ExpandShapeOp> {
+    : OpRewritePattern<tensor::ExpandShapeOp> {
   FoldConsumerExpandShapeWithInnerTiled(MLIRContext *context,
                                         linalg::ControlFusionFn controlFn,
                                         PatternBenefit benefit = 1)
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/GPU/ExternalInterfaces/GPUScopeExternalModels.cpp b/compiler/src/iree/compiler/Codegen/Dialect/GPU/ExternalInterfaces/GPUScopeExternalModels.cpp
index 9e9e1dc95fe9..5620d5951688 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/GPU/ExternalInterfaces/GPUScopeExternalModels.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/GPU/ExternalInterfaces/GPUScopeExternalModels.cpp
@@ -40,8 +40,8 @@ class IREEGPUConversionDialectInterface final
 /// Uses gpu.num_subgroups for worker count and gpu.subgroup_id for worker ID.
 /// Allocations at this scope use GPU shared memory space.
 struct SubgroupScopeModel
-    : public PCF::ScopeAttrInterface::ExternalModel<SubgroupScopeModel,
-                                                    GPU::SubgroupScopeAttr> {
+    : PCF::ScopeAttrInterface::ExternalModel<SubgroupScopeModel,
+                                             GPU::SubgroupScopeAttr> {
   SmallVector<Value> getWorkerCounts(Attribute attr, OpBuilder &builder,
                                      Location loc, int64_t numIds) const {
     assert(numIds >= 1 && "expected at least one requested worker count");
@@ -90,8 +90,8 @@ struct SubgroupScopeModel
 /// Uses gpu.subgroup_size for worker count and gpu.lane_id for worker ID.
 /// Allocations at this scope are not yet supported.
 struct LaneScopeModel
-    : public PCF::ScopeAttrInterface::ExternalModel<LaneScopeModel,
-                                                    GPU::LaneScopeAttr> {
+    : PCF::ScopeAttrInterface::ExternalModel<LaneScopeModel,
+                                             GPU::LaneScopeAttr> {
   SmallVector<Value> getWorkerCounts(Attribute attr, OpBuilder &builder,
                                      Location loc, int64_t numIds) const {
     assert(numIds >= 1 && "expected at least one requested worker count");
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/GPU/Transforms/BufferizationInterfaces.cpp b/compiler/src/iree/compiler/Codegen/Dialect/GPU/Transforms/BufferizationInterfaces.cpp
index cccf381066d0..0e042e465a08 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/GPU/Transforms/BufferizationInterfaces.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/GPU/Transforms/BufferizationInterfaces.cpp
@@ -100,7 +100,7 @@ static ArrayAttr fencedGpuAddressSpaces(RewriterBase &rewriter, Iter buffers) {
 /// Bufferization of iree_gpu.barrier_region. Always just bufferizes in place
 /// and gets inlined with barriers.
 struct BarrierRegionOpBufferizationInterface
-    : public BufferizableOpInterface::ExternalModel<
+    : BufferizableOpInterface::ExternalModel<
           BarrierRegionOpBufferizationInterface, IREE::GPU::BarrierRegionOp> {
   bool bufferizesToMemoryRead(Operation *op, OpOperand &opOperand,
                               const AnalysisState &state) const {
@@ -226,7 +226,7 @@ struct BarrierRegionOpBufferizationInterface
 /// Bufferization of iree_gpu.value_barrier. Always just bufferizes in place
 /// and replaces with a barrier.
 struct ValueBarrierOpBufferizationInterface
-    : public BufferizableOpInterface::ExternalModel<
+    : BufferizableOpInterface::ExternalModel<
           ValueBarrierOpBufferizationInterface, IREE::GPU::ValueBarrierOp> {
   bool bufferizesToMemoryRead(Operation *op, OpOperand &opOperand,
                               const AnalysisState &state) const {
@@ -296,8 +296,8 @@ struct ValueBarrierOpBufferizationInterface
 /// Bufferization of iree_gpu.yield. Bufferized as part of their enclosing ops,
 /// so this is for analysis only.
 struct YieldOpBufferizationInterface
-    : public BufferizableOpInterface::ExternalModel<
-          YieldOpBufferizationInterface, IREE::GPU::YieldOp> {
+    : BufferizableOpInterface::ExternalModel<YieldOpBufferizationInterface,
+                                             IREE::GPU::YieldOp> {
   bool bufferizesToMemoryRead(Operation *op, OpOperand &opOperand,
                               const AnalysisState &state) const {
     return false;
@@ -353,7 +353,7 @@ struct YieldOpBufferizationInterface
 /// Bufferization of iree_gpu.coalesced_gather_dma. This op bufferizes to itself
 /// with memref operands instead of tensor operands.
 struct CoalescedGatherDMAOpBufferizationInterface
-    : public BufferizableOpInterface::ExternalModel<
+    : BufferizableOpInterface::ExternalModel<
           CoalescedGatherDMAOpBufferizationInterface,
           IREE::GPU::CoalescedGatherDMAOp> {
   bool bufferizesToMemoryRead(Operation *op, OpOperand &opOperand,
@@ -476,7 +476,7 @@ static bool hasStorageBufferMemSpace(BaseMemRefType m) {
 /// `storage_buffer`, else just forwards the input. This op never
 /// reads or writes.
 struct BufferResourceCastOpBufferizationInterface
-    : public BufferizableOpInterface::ExternalModel<
+    : BufferizableOpInterface::ExternalModel<
           BufferResourceCastOpBufferizationInterface,
           IREE::GPU::BufferResourceCastOp> {
   bool bufferizesToMemoryRead(Operation *op, OpOperand &opOperand,
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/GPU/Transforms/Transforms.cpp b/compiler/src/iree/compiler/Codegen/Dialect/GPU/Transforms/Transforms.cpp
index 0c40c401c2e8..ce293325abf8 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/GPU/Transforms/Transforms.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/GPU/Transforms/Transforms.cpp
@@ -1107,8 +1107,7 @@ fuseExtractSliceIntoProducerForall(RewriterBase &rewriter,
 //===----------------------------------------------------------------------===//
 
 namespace {
-struct LowerInnerTiledPattern
-    : public OpRewritePattern<IREE::Codegen::InnerTiledOp> {
+struct LowerInnerTiledPattern : OpRewritePattern<IREE::Codegen::InnerTiledOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(IREE::Codegen::InnerTiledOp tiledOp,
                                 PatternRewriter &rewriter) const override {
@@ -1592,7 +1591,7 @@ distributeInnerTiledOp(RewriterBase &rewriter,
 
 namespace {
 struct DropInnerTiledUnitDimsPattern
-    : public OpRewritePattern<IREE::Codegen::InnerTiledOp> {
+    : OpRewritePattern<IREE::Codegen::InnerTiledOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(IREE::Codegen::InnerTiledOp tiledOp,
                                 PatternRewriter &rewriter) const override {
@@ -1690,8 +1689,7 @@ struct OffsetMapInfo {
   }
 };
 
-struct UnrollInnerTiledPattern
-    : public OpRewritePattern<Codegen::InnerTiledOp> {
+struct UnrollInnerTiledPattern : OpRewritePattern<Codegen::InnerTiledOp> {
   UnrollInnerTiledPattern(MLIRContext *context,
                           const vector::UnrollVectorOptions &options,
                           PatternBenefit benefit = 1)
@@ -1954,8 +1952,7 @@ void mapLaneForalls(RewriterBase &rewriter, Operation *funcOp,
 //===---------------------------------------------------------------------===//
 
 namespace {
-struct LowerBarrierRegion
-    : public OpRewritePattern<IREE::GPU::BarrierRegionOp> {
+struct LowerBarrierRegion : OpRewritePattern<IREE::GPU::BarrierRegionOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(IREE::GPU::BarrierRegionOp barrierRegionOp,
                                 PatternRewriter &rewriter) const final {
@@ -2065,8 +2062,7 @@ void populateIREEGPUVectorizationPatterns(RewritePatternSet &patterns) {
 //===----------------------------------------------------------------------===//
 
 namespace {
-struct LowerValueBarrierPattern
-    : public OpRewritePattern<IREE::GPU::ValueBarrierOp> {
+struct LowerValueBarrierPattern : OpRewritePattern<IREE::GPU::ValueBarrierOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(IREE::GPU::ValueBarrierOp barrier,
                                 PatternRewriter &rewriter) const override {
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/PCF/IR/PCFDialect.cpp b/compiler/src/iree/compiler/Codegen/Dialect/PCF/IR/PCFDialect.cpp
index c0b9b8b074a7..a97818aed927 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/PCF/IR/PCFDialect.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/PCF/IR/PCFDialect.cpp
@@ -20,7 +20,7 @@ namespace mlir::iree_compiler::IREE::PCF {
 namespace {
 
 // Used to control inlining behavior.
-struct PCFInlinerInterface : public DialectInlinerInterface {
+struct PCFInlinerInterface : DialectInlinerInterface {
   using DialectInlinerInterface::DialectInlinerInterface;
 
   bool isLegalToInline(Operation *call, Operation *callable,
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/FuseProducers.cpp b/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/FuseProducers.cpp
index 0d079810eede..a6146d61ed02 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/FuseProducers.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/FuseProducers.cpp
@@ -29,8 +29,7 @@ struct FuseProducersPass final
   void runOnOperation() override;
 };
 
-struct FuseProducerIntoGenericOp
-    : public OpRewritePattern<IREE::PCF::GenericOp> {
+struct FuseProducerIntoGenericOp : OpRewritePattern<IREE::PCF::GenericOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(IREE::PCF::GenericOp genericOp,
                                 PatternRewriter &rewriter) const override {
@@ -43,7 +42,7 @@ struct FuseProducerIntoGenericOp
   }
 };
 
-struct FuseProducerIntoLoopOp : public OpRewritePattern<IREE::PCF::LoopOp> {
+struct FuseProducerIntoLoopOp : OpRewritePattern<IREE::PCF::LoopOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(IREE::PCF::LoopOp loopOp,
                                 PatternRewriter &rewriter) const override {
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/LowerStructuralPCF.cpp b/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/LowerStructuralPCF.cpp
index dc89441c2d23..8bcad94bb00c 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/LowerStructuralPCF.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/LowerStructuralPCF.cpp
@@ -60,7 +60,7 @@ struct LowerStructuralPCFPass final
   void runOnOperation() override;
 };
 
-struct LowerGenericOp : public OpRewritePattern<IREE::PCF::GenericOp> {
+struct LowerGenericOp : OpRewritePattern<IREE::PCF::GenericOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(IREE::PCF::GenericOp genericOp,
                                 PatternRewriter &rewriter) const override {
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/Transforms.cpp b/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/Transforms.cpp
index 350a31b5401d..0e2f2098f609 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/Transforms.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/PCF/Transforms/Transforms.cpp
@@ -248,7 +248,7 @@ static LogicalResult dropUnusedResults(RewriterBase &rewriter, OpTy op) {
 }
 
 template <typename OpTy>
-struct DropUnusedResult final : public OpRewritePattern<OpTy> {
+struct DropUnusedResult final : OpRewritePattern<OpTy> {
   using OpRewritePattern<OpTy>::OpRewritePattern;
 
   LogicalResult matchAndRewrite(OpTy op,
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/IR/VectorExtDialect.cpp b/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/IR/VectorExtDialect.cpp
index bf4e94e14f8a..78b9ef4fcd57 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/IR/VectorExtDialect.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/IR/VectorExtDialect.cpp
@@ -22,7 +22,7 @@ using namespace mlir::iree_compiler::IREE::VectorExt;
 
 namespace mlir::iree_compiler::IREE::VectorExt {
 
-struct IREEVectorExtDialectOpAsmInterface : public OpAsmDialectInterface {
+struct IREEVectorExtDialectOpAsmInterface : OpAsmDialectInterface {
   using OpAsmDialectInterface::OpAsmDialectInterface;
   AliasResult getAlias(Attribute attr, raw_ostream &os) const override {
     if (isa<NestedLayoutAttr>(attr)) {
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/Transforms/BufferizationInterfaces.cpp b/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/Transforms/BufferizationInterfaces.cpp
index 7f89076453cb..1762f63798d6 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/Transforms/BufferizationInterfaces.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/Transforms/BufferizationInterfaces.cpp
@@ -25,7 +25,7 @@ using mlir::bufferization::replaceOpWithNewBufferizedOp;
 namespace {
 
 struct TransferGatherOpInterface
-    : public BufferizableOpInterface::ExternalModel<
+    : BufferizableOpInterface::ExternalModel<
           TransferGatherOpInterface, IREE::VectorExt::TransferGatherOp> {
   bool bufferizesToMemoryRead(Operation *op, OpOperand &opOperand,
                               const AnalysisState &state) const {
@@ -68,7 +68,7 @@ struct TransferGatherOpInterface
 };
 
 struct TransferScatterOpInterface
-    : public BufferizableOpInterface::ExternalModel<
+    : BufferizableOpInterface::ExternalModel<
           TransferScatterOpInterface, IREE::VectorExt::TransferScatterOp> {
   bool bufferizesToMemoryRead(Operation *op, OpOperand &opOperand,
                               const AnalysisState &state) const {
diff --git a/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/Transforms/LowerTransferGatherOps.cpp b/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/Transforms/LowerTransferGatherOps.cpp
index 3694327f4ee5..90142c0a0726 100644
--- a/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/Transforms/LowerTransferGatherOps.cpp
+++ b/compiler/src/iree/compiler/Codegen/Dialect/VectorExt/Transforms/LowerTransferGatherOps.cpp
@@ -100,7 +100,7 @@ static Value extractVecSlice(OpBuilder &b, Location loc, Value vec,
 
 /// Unrolls dim 0 of a transfer_gather, reducing vector rank by 1 each
 /// application. Stops at rank 1.
-struct UnrollTransferGatherDim : public OpRewritePattern<TransferGatherOp> {
+struct UnrollTransferGatherDim : OpRewritePattern<TransferGatherOp> {
   using OpRewritePattern::OpRewritePattern;
 
   LogicalResult matchAndRewrite(TransferGatherOp op,
diff --git a/compiler/src/iree/compiler/Codegen/ExternalInterfaces/CPUEncodingExternalModels.cpp b/compiler/src/iree/compiler/Codegen/ExternalInterfaces/CPUEncodingExternalModels.cpp
index d89f69c4c450..6a07328b6abb 100644
--- a/compiler/src/iree/compiler/Codegen/ExternalInterfaces/CPUEncodingExternalModels.cpp
+++ b/compiler/src/iree/compiler/Codegen/ExternalInterfaces/CPUEncodingExternalModels.cpp
@@ -688,7 +688,7 @@ enumerateCPUMatmulTiles(IREE::Encoding::EncodingAttr encoding,
 }
 
 struct CPUEncodingPackedLayoutMaterializerAttr
-    : public PackedLayoutMaterializerAttrExternalModelBase<
+    : PackedLayoutMaterializerAttrExternalModelBase<
           CPUEncodingPackedLayoutMaterializerAttr, CPUEncodingResolverAttr> {
 
   DictionaryAttr getConfiguration(Attribute attr) const {
@@ -745,7 +745,7 @@ struct CPUEncodingPackedLayoutMaterializerAttr
 };
 
 struct CPUEncodingResolverMaterializerAttr final
-    : public EncodingLayoutMaterializerAttrExternalModelBase<
+    : EncodingLayoutMaterializerAttrExternalModelBase<
           CPUEncodingResolverMaterializerAttr, CPUEncodingResolverAttr> {
 
   Operation *lowerOp(Attribute attr, OpBuilder &b, Operation *op,
diff --git a/compiler/src/iree/compiler/Codegen/ExternalInterfaces/GPUEncodingExternalModels.cpp b/compiler/src/iree/compiler/Codegen/ExternalInterfaces/GPUEncodingExternalModels.cpp
index 41245bbb6f1b..8af60f862803 100644
--- a/compiler/src/iree/compiler/Codegen/ExternalInterfaces/GPUEncodingExternalModels.cpp
+++ b/compiler/src/iree/compiler/Codegen/ExternalInterfaces/GPUEncodingExternalModels.cpp
@@ -551,7 +551,7 @@ static Operation *lowerContractionOrScaledContractionOpToInnerTiledOp(
 }
 
 struct GPUEncodingPackedLayoutMaterializerAttr
-    : public PackedLayoutMaterializerAttrExternalModelBase<
+    : PackedLayoutMaterializerAttrExternalModelBase<
           GPUEncodingPackedLayoutMaterializerAttr, GPUEncodingResolverAttr> {
   DictionaryAttr getConfiguration(Attribute attr) const {
     return cast<GPUEncodingResolverAttr>(attr).getConfiguration();
@@ -601,7 +601,7 @@ struct GPUEncodingPackedLayoutMaterializerAttr
 };
 
 struct GPUEncodingResolverMaterializerAttr
-    : public EncodingLayoutMaterializerAttrExternalModelBase<
+    : EncodingLayoutMaterializerAttrExternalModelBase<
           GPUEncodingResolverMaterializerAttr, GPUEncodingResolverAttr> {
   Operation *lowerOp(Attribute attr, OpBuilder &b, Operation *op,
                      TypeRange convertedResTypes,
diff --git a/compiler/src/iree/compiler/Codegen/ExternalInterfaces/UtilExternalModels.cpp b/compiler/src/iree/compiler/Codegen/ExternalInterfaces/UtilExternalModels.cpp
index 9e75042796e9..aa0a6fcff3e3 100644
--- a/compiler/src/iree/compiler/Codegen/ExternalInterfaces/UtilExternalModels.cpp
+++ b/compiler/src/iree/compiler/Codegen/ExternalInterfaces/UtilExternalModels.cpp
@@ -19,8 +19,8 @@ namespace {
 //===----------------------------------------------------------------------===//
 
 struct LoadFromBufferOpInterface
-    : public ValueBoundsOpInterface::ExternalModel<
-          LoadFromBufferOpInterface, IREE::Codegen::LoadFromBufferOp> {
+    : ValueBoundsOpInterface::ExternalModel<LoadFromBufferOpInterface,
+                                            IREE::Codegen::LoadFromBufferOp> {
   void populateBoundsForShapedValueDim(Operation *op, Value value, int64_t dim,
                                        ValueBoundsConstraintSet &cstr) const {
     auto loadOp = cast<IREE::Codegen::LoadFromBufferOp>(op);
diff --git a/compiler/src/iree/compiler/Codegen/ExternalInterfaces/Utils.h b/compiler/src/iree/compiler/Codegen/ExternalInterfaces/Utils.h
index 1a98b6b5a076..83c4cdf04497 100644
--- a/compiler/src/iree/compiler/Codegen/ExternalInterfaces/Utils.h
+++ b/compiler/src/iree/compiler/Codegen/ExternalInterfaces/Utils.h
@@ -38,7 +38,7 @@ void adjustTileSizesForBitcast(RankedTensorType type,
 template <typename EncodingPackedLayoutMaterializerAttr,
           typename EncodingLayoutAttr>
 struct PackedLayoutMaterializerAttrExternalModelBase
-    : public IREE::Codegen::PackedLayoutMaterializerAttr::ExternalModel<
+    : IREE::Codegen::PackedLayoutMaterializerAttr::ExternalModel<
           EncodingPackedLayoutMaterializerAttr, EncodingLayoutAttr> {
 public:
   IREE::Codegen::MaterializeEncodingInfo
@@ -161,7 +161,7 @@ struct PackedLayoutMaterializerAttrExternalModelBase
 
 template <typename EncodingLayoutMaterializerAttr, typename EncodingLayoutAttr>
 struct EncodingLayoutMaterializerAttrExternalModelBase
-    : public IREE::Encoding::LayoutMaterializerAttr::ExternalModel<
+    : IREE::Encoding::LayoutMaterializerAttr::ExternalModel<
           EncodingLayoutMaterializerAttr, EncodingLayoutAttr> {
 public:
   IREE::Codegen::MaterializeEncodingInfo
diff --git a/compiler/src/iree/compiler/Codegen/Interfaces/BufferizationInterfaces.cpp b/compiler/src/iree/compiler/Codegen/Interfaces/BufferizationInterfaces.cpp
index 3f0abb3cbe64..013a1f747204 100644
--- a/compiler/src/iree/compiler/Codegen/Interfaces/BufferizationInterfaces.cpp
+++ b/compiler/src/iree/compiler/Codegen/Interfaces/BufferizationInterfaces.cpp
@@ -54,7 +54,7 @@ namespace {
 //===----------------------------------------------------------------------===//
 
 struct DispatchTensorLoadOpInterface
-    : public BufferizableOpInterface::ExternalModel<
+    : BufferizableOpInterface::ExternalModel<
           DispatchTensorLoadOpInterface,
           IREE::TensorExt::DispatchTensorLoadOp> {
   bool isWritable(Operation *op, Value value,
@@ -100,7 +100,7 @@ struct DispatchTensorLoadOpInterface
 };
 
 struct DispatchTensorStoreOpInterface
-    : public BufferizableOpInterface::ExternalModel<
+    : BufferizableOpInterface::ExternalModel<
           DispatchTensorStoreOpInterface,
           IREE::TensorExt::DispatchTensorStoreOp> {
   bool bufferizesToMemoryRead(Operation *op, OpOperand &opOperand,
@@ -167,8 +167,8 @@ struct DispatchTensorStoreOpInterface
 };
 
 struct LoadFromBufferOpInterface
-    : public BufferizableOpInterface::ExternalModel<
-          LoadFromBufferOpInterface, IREE::Codegen::LoadFromBufferOp> {
+    : BufferizableOpInterface::ExternalModel<LoadFromBufferOpInterface,
+                                             IREE::Codegen::LoadFromBufferOp> {
   bool isWritable(Operation *op, Value value,
                   const AnalysisState &state) const {
     // Search for a hal.interface.binding.subspan op that is the source of the
@@ -198,8 +198,8 @@ struct LoadFromBufferOpInterface
 };
 
 struct StoreToBufferOpInterface
-    : public BufferizableOpInterface::ExternalModel<
-          StoreToBufferOpInterface, IREE::Codegen::StoreToBufferOp> {
+    : BufferizableOpInterface::ExternalModel<StoreToBufferOpInterface,
+                                             IREE::Codegen::StoreToBufferOp> {
   bool bufferizesToMemoryRead(Operation *op, OpOperand &opOperand,
                               const AnalysisState &state) const {
     return true;
@@ -356,7 +356,7 @@ static LogicalResult bufferizeLinalgExtOp(RewriterBase &rewriter,
 /// a new op that operates entirely on memrefs.
 template <typename OpTy>
 struct LinalgExtOpInterface
-    : public bufferization::DstBufferizableOpInterfaceExternalModel<
+    : bufferization::DstBufferizableOpInterfaceExternalModel<
           LinalgExtOpInterface<OpTy>, OpTy> {
 
   bool bufferizesToMemoryRead(Operation *op, OpOperand &opOperand,
@@ -384,9 +384,8 @@ struct LinalgExtOpInterfaceHelper {
 };
 
 struct DispatchTensorLoadOpSubsetInterface
-    : public SubsetOpInterface::ExternalModel<
-          DispatchTensorLoadOpSubsetInterface,
-          IREE::TensorExt::DispatchTensorLoadOp> {
+    : SubsetOpInterface::ExternalModel<DispatchTensorLoadOpSubsetInterface,
+                                       IREE::TensorExt::DispatchTensorLoadOp> {
   bool operatesOnEquivalentSubset(
       Operation *op, SubsetOpInterface candidate,
       function_ref<bool(Value, Value)> equivalenceFn) const {
@@ -409,9 +408,8 @@ struct DispatchTensorLoadOpSubsetInterface
 };
 
 struct DispatchTensorStoreOpSubsetInterface
-    : public SubsetOpInterface::ExternalModel<
-          DispatchTensorStoreOpSubsetInterface,
-          IREE::TensorExt::DispatchTensorStoreOp> {
+    : SubsetOpInterface::ExternalModel<DispatchTensorStoreOpSubsetInterface,
+                                       IREE::TensorExt::DispatchTensorStoreOp> {
 
   bool operatesOnEquivalentSubset(
       Operation *op, SubsetOpInterface candidate,
@@ -435,7 +433,7 @@ struct DispatchTensorStoreOpSubsetInterface
 };
 
 struct DispatchTensorStoreOpSubsetInsertionInterface
-    : public SubsetInsertionOpInterface::ExternalModel<
+    : SubsetInsertionOpInterface::ExternalModel<
           DispatchTensorStoreOpSubsetInsertionInterface,
           IREE::TensorExt::DispatchTensorStoreOp> {
 
@@ -475,8 +473,8 @@ struct DispatchTensorStoreOpSubsetInsertionInterface
 };
 
 struct LoadFromBufferOpSubsetInterface
-    : public SubsetOpInterface::ExternalModel<LoadFromBufferOpSubsetInterface,
-                                              IREE::Codegen::LoadFromBufferOp> {
+    : SubsetOpInterface::ExternalModel<LoadFromBufferOpSubsetInterface,
+                                       IREE::Codegen::LoadFromBufferOp> {
   bool operatesOnEquivalentSubset(
       Operation *op, SubsetOpInterface candidate,
       function_ref<bool(Value, Value)> equivalenceFn) const {
@@ -500,8 +498,8 @@ struct LoadFromBufferOpSubsetInterface
 };
 
 struct StoreToBufferOpSubsetInterface
-    : public SubsetOpInterface::ExternalModel<StoreToBufferOpSubsetInterface,
-                                              IREE::Codegen::StoreToBufferOp> {
+    : SubsetOpInterface::ExternalModel<StoreToBufferOpSubsetInterface,
+                                       IREE::Codegen::StoreToBufferOp> {
 
   bool operatesOnEquivalentSubset(
       Operation *op, SubsetOpInterface candidate,
@@ -528,7 +526,7 @@ struct StoreToBufferOpSubsetInterface
 };
 
 struct StoreToBufferOpSubsetInsertionInterface
-    : public SubsetInsertionOpInterface::ExternalModel<
+    : SubsetInsertionOpInterface::ExternalModel<
           StoreToBufferOpSubsetInsertionInterface,
           IREE::Codegen::StoreToBufferOp> {
 
diff --git a/compiler/src/iree/compiler/Codegen/Interfaces/BufferizationInterfaces.h b/compiler/src/iree/compiler/Codegen/Interfaces/BufferizationInterfaces.h
index a10c07f9dd43..1c08aeb14a16 100644
--- a/compiler/src/iree/compiler/Codegen/Interfaces/BufferizationInterfaces.h
+++ b/compiler/src/iree/compiler/Codegen/Interfaces/BufferizationInterfaces.h
@@ -14,7 +14,7 @@
 namespace mlir::iree_compiler {
 
 struct IREEOneShotBufferizationOptions
-    : public mlir::bufferization::OneShotBufferizationOptions {
+    : mlir::bufferization::OneShotBufferizationOptions {
   // For now this has no extra fields. Keeping this anyway in case this is
   // needed in future.
 };
diff --git a/compiler/src/iree/compiler/Codegen/Interfaces/PartitionableLoopsInterface.cpp b/compiler/src/iree/compiler/Codegen/Interfaces/PartitionableLoopsInterface.cpp
index 01faf18bf6f8..f3d81e4acb31 100644
--- a/compiler/src/iree/compiler/Codegen/Interfaces/PartitionableLoopsInterface.cpp
+++ b/compiler/src/iree/compiler/Codegen/Interfaces/PartitionableLoopsInterface.cpp
@@ -55,7 +55,7 @@ getPartitionableLoopsImpl(linalg::LinalgOp linalgOp,
 /// External model implementation for all LinalgOps.
 template <typename OpTy>
 struct LinalgOpPartitionableLoops
-    : public PartitionableLoopsInterface::ExternalModel<
+    : PartitionableLoopsInterface::ExternalModel<
           LinalgOpPartitionableLoops<OpTy>, OpTy> {
   llvm::SmallVector<unsigned>
   getPartitionableLoops(Operation *op,
@@ -67,8 +67,8 @@ struct LinalgOpPartitionableLoops
 
 /// External model implementation for linalg::Mmt4DOp.
 struct Mmt4DOpPartitionableLoops
-    : public PartitionableLoopsInterface::ExternalModel<
-          Mmt4DOpPartitionableLoops, linalg::Mmt4DOp> {
+    : PartitionableLoopsInterface::ExternalModel<Mmt4DOpPartitionableLoops,
+                                                 linalg::Mmt4DOp> {
   llvm::SmallVector<unsigned>
   getPartitionableLoops(Operation *op,
                         std::optional<unsigned> maxNumPartitionedLoops) const {
@@ -78,8 +78,8 @@ struct Mmt4DOpPartitionableLoops
 
 /// External model implementation for linalg::BatchMmt4DOp.
 struct BatchMmt4DOpPartitionableLoops
-    : public PartitionableLoopsInterface::ExternalModel<
-          BatchMmt4DOpPartitionableLoops, linalg::BatchMmt4DOp> {
+    : PartitionableLoopsInterface::ExternalModel<BatchMmt4DOpPartitionableLoops,
+                                                 linalg::BatchMmt4DOp> {
   llvm::SmallVector<unsigned>
   getPartitionableLoops(Operation *op,
                         std::optional<unsigned> maxNumPartitionedLoops) const {
@@ -97,7 +97,7 @@ struct BatchMmt4DOpPartitionableLoops
 /// the outer parallel loops as partitionable.
 template <typename OpTy>
 struct OuterParallelAsPartitionableLoops
-    : public PartitionableLoopsInterface::ExternalModel<
+    : PartitionableLoopsInterface::ExternalModel<
           OuterParallelAsPartitionableLoops<OpTy>, OpTy> {
   llvm::SmallVector<unsigned>
   getPartitionableLoops(Operation *op,
@@ -130,8 +130,9 @@ struct OuterParallelAsPartitionableLoops
 /// External model implementation for operations that are to be executed
 /// sequentially.
 template <typename OpTy>
-struct NoPartitionableLoops : public PartitionableLoopsInterface::ExternalModel<
-                                  NoPartitionableLoops<OpTy>, OpTy> {
+struct NoPartitionableLoops
+    : PartitionableLoopsInterface::ExternalModel<NoPartitionableLoops<OpTy>,
+                                                 OpTy> {
   llvm::SmallVector<unsigned>
   getPartitionableLoops(Operation *op,
                         std::optional<unsigned> maxNumPartitionedLoops) const {
@@ -140,8 +141,8 @@ struct NoPartitionableLoops : public PartitionableLoopsInterface::ExternalModel<
 };
 
 struct ConcatOpPartitionableLoops
-    : public PartitionableLoopsInterface::ExternalModel<
-          ConcatOpPartitionableLoops, tensor::ConcatOp> {
+    : PartitionableLoopsInterface::ExternalModel<ConcatOpPartitionableLoops,
+                                                 tensor::ConcatOp> {
   llvm::SmallVector<unsigned>
   getPartitionableLoops(Operation *op,
                         std::optional<unsigned> maxNumPartitionedLoops) const {
@@ -170,8 +171,8 @@ struct ConcatOpPartitionableLoops
 
 /// External model implementation for specifying partitionable loops of FftOp.
 struct FftOpPartitionableLoops
-    : public PartitionableLoopsInterface::ExternalModel<
-          FftOpPartitionableLoops, IREE::LinalgExt::FftOp> {
+    : PartitionableLoopsInterface::ExternalModel<FftOpPartitionableLoops,
+                                                 IREE::LinalgExt::FftOp> {
   llvm::SmallVector<unsigned>
   getPartitionableLoops(Operation *op,
                         std::optional<unsigned> maxNumPartitionedLoops) const {
@@ -198,7 +199,7 @@ struct FftOpPartitionableLoops
 /// partitionable.
 template <typename OpTy>
 struct AllParallelAsPartitionableLoops
-    : public PartitionableLoopsInterface::ExternalModel<
+    : PartitionableLoopsInterface::ExternalModel<
           AllParallelAsPartitionableLoops<OpTy>, OpTy> {
   llvm::SmallVector<unsigned>
   getPartitionableLoops(Operation *op,
diff --git a/compiler/src/iree/compiler/Codegen/Interfaces/ProcessorOpInterfaces.cpp b/compiler/src/iree/compiler/Codegen/Interfaces/ProcessorOpInterfaces.cpp
index b893acd2ccfd..61cc1131aef6 100644
--- a/compiler/src/iree/compiler/Codegen/Interfaces/ProcessorOpInterfaces.cpp
+++ b/compiler/src/iree/compiler/Codegen/Interfaces/ProcessorOpInterfaces.cpp
@@ -29,24 +29,24 @@ static unsigned dimToIndex(gpu::Dimension dim) {
 }
 
 struct ThreadIdOpInterface
-    : public ProcessorIDInterface::ExternalModel<ThreadIdOpInterface,
-                                                 gpu::ThreadIdOp> {
+    : ProcessorIDInterface::ExternalModel<ThreadIdOpInterface,
+                                          gpu::ThreadIdOp> {
   unsigned getDimIndex(Operation *op) const {
     return dimToIndex(cast<gpu::ThreadIdOp>(op).getDimension());
   }
 };
 
 struct BlockDimOpInterface
-    : public ProcessorCountInterface::ExternalModel<BlockDimOpInterface,
-                                                    gpu::BlockDimOp> {
+    : ProcessorCountInterface::ExternalModel<BlockDimOpInterface,
+                                             gpu::BlockDimOp> {
   unsigned getDimIndex(Operation *op) const {
     return dimToIndex(cast<gpu::BlockDimOp>(op).getDimension());
   }
 };
 
 struct WorkgroupIdOpInterface
-    : public ProcessorIDInterface::ExternalModel<
-          WorkgroupIdOpInterface, IREE::HAL::InterfaceWorkgroupIDOp> {
+    : ProcessorIDInterface::ExternalModel<WorkgroupIdOpInterface,
+                                          IREE::HAL::InterfaceWorkgroupIDOp> {
   unsigned getDimIndex(Operation *op) const {
     return cast<IREE::HAL::InterfaceWorkgroupIDOp>(op)
         .getDimension()
@@ -55,7 +55,7 @@ struct WorkgroupIdOpInterface
 };
 
 struct WorkgroupCountOpInterface
-    : public ProcessorCountInterface::ExternalModel<
+    : ProcessorCountInterface::ExternalModel<
           WorkgroupCountOpInterface, IREE::HAL::InterfaceWorkgroupCountOp> {
   unsigned getDimIndex(Operation *op) const {
     return cast<IREE::HAL::InterfaceWorkgroupCountOp>(op)
@@ -65,7 +65,7 @@ struct WorkgroupCountOpInterface
 };
 
 struct WorkgroupTileSizeOpInterface
-    : public ProcessorTileSizeInterface::ExternalModel<
+    : ProcessorTileSizeInterface::ExternalModel<
           WorkgroupTileSizeOpInterface, IREE::HAL::InterfaceWorkgroupSizeOp> {
   unsigned getDimIndex(Operation *op) const {
     return cast<IREE::HAL::InterfaceWorkgroupSizeOp>(op)
diff --git a/compiler/src/iree/compiler/Codegen/Interfaces/VectorizableOpInterface.cpp b/compiler/src/iree/compiler/Codegen/Interfaces/VectorizableOpInterface.cpp
index 3f8b2dc63ae8..4d85305ed3ad 100644
--- a/compiler/src/iree/compiler/Codegen/Interfaces/VectorizableOpInterface.cpp
+++ b/compiler/src/iree/compiler/Codegen/Interfaces/VectorizableOpInterface.cpp
@@ -41,8 +41,8 @@ static bool getBoolOption(DictionaryAttr options, StringRef name,
 }
 
 struct GatherOpVectorizationModel
-    : public VectorizableOpInterface::ExternalModel<GatherOpVectorizationModel,
-                                                    IREE::LinalgExt::GatherOp> {
+    : VectorizableOpInterface::ExternalModel<GatherOpVectorizationModel,
+                                             IREE::LinalgExt::GatherOp> {
 
   bool isVectorizable(Operation *op, ArrayRef<int64_t> vectorSizes,
                       ArrayRef<bool> scalableDims,
@@ -161,8 +161,8 @@ struct GatherOpVectorizationModel
 };
 
 struct ArgCompareOpVectorizationModel
-    : public VectorizableOpInterface::ExternalModel<
-          ArgCompareOpVectorizationModel, IREE::LinalgExt::ArgCompareOp> {
+    : VectorizableOpInterface::ExternalModel<ArgCompareOpVectorizationModel,
+                                             IREE::LinalgExt::ArgCompareOp> {
 
   bool isVectorizable(Operation *op, ArrayRef<int64_t> vectorSizes,
                       ArrayRef<bool> scalableDims,
@@ -315,8 +315,8 @@ struct ArgCompareOpVectorizationModel
 };
 
 struct ToLayoutOpVectorizationModel
-    : public VectorizableOpInterface::ExternalModel<
-          ToLayoutOpVectorizationModel, IREE::VectorExt::ToLayoutOp> {
+    : VectorizableOpInterface::ExternalModel<ToLayoutOpVectorizationModel,
+                                             IREE::VectorExt::ToLayoutOp> {
 
   bool isVectorizable(Operation *op, ArrayRef<int64_t> vectorSizes,
                       ArrayRef<bool> scalableDims,
@@ -389,8 +389,8 @@ struct ToLayoutOpVectorizationModel
 };
 
 struct MapStoreOpVectorizationModel
-    : public VectorizableOpInterface::ExternalModel<
-          MapStoreOpVectorizationModel, IREE::LinalgExt::MapStoreOp> {
+    : VectorizableOpInterface::ExternalModel<MapStoreOpVectorizationModel,
+                                             IREE::LinalgExt::MapStoreOp> {
 
   bool isVectorizable(Operation *op, ArrayRef<int64_t> vectorSizes,
                       ArrayRef<bool> scalableDims,
@@ -792,7 +792,7 @@ struct LinalgStructuredOpVectorizationModel
 /// These go through linalg::vectorize but are not LinalgOp subclasses.
 template <typename OpTy>
 struct NonLinalgStructuredOpVectorizationModel
-    : public VectorizableOpInterface::ExternalModel<
+    : VectorizableOpInterface::ExternalModel<
           NonLinalgStructuredOpVectorizationModel<OpTy>, OpTy> {
 
   bool isVectorizable(Operation *op, ArrayRef<int64_t> vectorSizes,
@@ -819,8 +819,8 @@ struct NonLinalgStructuredOpVectorizationModel
 /// External model for tensor::PadOp. Different dialect, goes through
 /// linalg::vectorize.
 struct PadOpVectorizationModel
-    : public VectorizableOpInterface::ExternalModel<PadOpVectorizationModel,
-                                                    tensor::PadOp> {
+    : VectorizableOpInterface::ExternalModel<PadOpVectorizationModel,
+                                             tensor::PadOp> {
 
   bool isVectorizable(Operation *op, ArrayRef<int64_t> vectorSizes,
                       ArrayRef<bool> scalableDims,
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp
index ae8fb1f24d26..7bfe30da7dc0 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/ConvertToLLVM.cpp
@@ -74,7 +74,7 @@ namespace mlir::iree_compiler {
 namespace {
 
 template <typename OpT>
-struct ConvertOpToLLVMWithABIPattern : public ConvertOpToLLVMPattern<OpT> {
+struct ConvertOpToLLVMWithABIPattern : ConvertOpToLLVMPattern<OpT> {
   ConvertOpToLLVMWithABIPattern(HALDispatchABI &abi,
                                 LLVMTypeConverter &typeConverter,
                                 PatternBenefit benefit = 1)
@@ -108,7 +108,7 @@ struct ConvertOpToLLVMWithABIPattern : public ConvertOpToLLVMPattern<OpT> {
 /// NOTE: we bump the benefit of the pattern to 100 to pick this pattern instead
 /// of a competing pattern inserted by `populateFuncToLLVMConversionPatterns`.
 struct ConvertHALEntryPointFuncOp
-    : public ConvertOpToLLVMWithABIPattern<func::FuncOp> {
+    : ConvertOpToLLVMWithABIPattern<func::FuncOp> {
   ConvertHALEntryPointFuncOp(HALDispatchABI &abi,
                              LLVMTypeConverter &typeConverter)
       : ConvertOpToLLVMWithABIPattern(abi, typeConverter,
@@ -203,8 +203,7 @@ struct ConvertHALEntryPointFuncOp
 ///
 /// The parent LLVMFuncOp must be compatible with HALDispatchABI.
 struct ConvertHALExecutableConstantLoadOp
-    : public ConvertOpToLLVMWithABIPattern<
-          IREE::HAL::ExecutableConstantLoadOp> {
+    : ConvertOpToLLVMWithABIPattern<IREE::HAL::ExecutableConstantLoadOp> {
   using ConvertOpToLLVMWithABIPattern::ConvertOpToLLVMWithABIPattern;
   LogicalResult
   matchAndRewrite(IREE::HAL::ExecutableConstantLoadOp loadOp,
@@ -223,7 +222,7 @@ struct ConvertHALExecutableConstantLoadOp
 ///
 /// The parent LLVMFuncOp must be compatible with HALDispatchABI.
 struct ConvertHALInterfaceWorkgroupIDOp
-    : public ConvertOpToLLVMWithABIPattern<IREE::HAL::InterfaceWorkgroupIDOp> {
+    : ConvertOpToLLVMWithABIPattern<IREE::HAL::InterfaceWorkgroupIDOp> {
   using ConvertOpToLLVMWithABIPattern::ConvertOpToLLVMWithABIPattern;
   LogicalResult
   matchAndRewrite(IREE::HAL::InterfaceWorkgroupIDOp idOp,
@@ -241,8 +240,7 @@ struct ConvertHALInterfaceWorkgroupIDOp
 ///
 /// The parent LLVMFuncOp must be compatible with HALDispatchABI.
 struct ConvertHALInterfaceWorkgroupSizeOp
-    : public ConvertOpToLLVMWithABIPattern<
-          IREE::HAL::InterfaceWorkgroupSizeOp> {
+    : ConvertOpToLLVMWithABIPattern<IREE::HAL::InterfaceWorkgroupSizeOp> {
   using ConvertOpToLLVMWithABIPattern::ConvertOpToLLVMWithABIPattern;
   LogicalResult
   matchAndRewrite(IREE::HAL::InterfaceWorkgroupSizeOp sizeOp,
@@ -261,8 +259,7 @@ struct ConvertHALInterfaceWorkgroupSizeOp
 ///
 /// The parent LLVMFuncOp must be compatible with HALDispatchABI.
 struct ConvertHALInterfaceWorkgroupCountOp
-    : public ConvertOpToLLVMWithABIPattern<
-          IREE::HAL::InterfaceWorkgroupCountOp> {
+    : ConvertOpToLLVMWithABIPattern<IREE::HAL::InterfaceWorkgroupCountOp> {
   using ConvertOpToLLVMWithABIPattern::ConvertOpToLLVMWithABIPattern;
   LogicalResult
   matchAndRewrite(IREE::HAL::InterfaceWorkgroupCountOp countOp,
@@ -281,7 +278,7 @@ struct ConvertHALInterfaceWorkgroupCountOp
 ///
 /// The parent LLVMFuncOp must be compatible with HALDispatchABI.
 struct ConvertHALInterfaceConstantLoadOp
-    : public ConvertOpToLLVMWithABIPattern<IREE::HAL::InterfaceConstantLoadOp> {
+    : ConvertOpToLLVMWithABIPattern<IREE::HAL::InterfaceConstantLoadOp> {
   using ConvertOpToLLVMWithABIPattern::ConvertOpToLLVMWithABIPattern;
   LogicalResult
   matchAndRewrite(IREE::HAL::InterfaceConstantLoadOp loadOp,
@@ -300,8 +297,7 @@ struct ConvertHALInterfaceConstantLoadOp
 ///
 /// The parent LLVMFuncOp must be compatible with HALDispatchABI.
 struct ConvertHALInterfaceBindingSubspanOp
-    : public ConvertOpToLLVMWithABIPattern<
-          IREE::HAL::InterfaceBindingSubspanOp> {
+    : ConvertOpToLLVMWithABIPattern<IREE::HAL::InterfaceBindingSubspanOp> {
   using ConvertOpToLLVMWithABIPattern::ConvertOpToLLVMWithABIPattern;
   LogicalResult
   matchAndRewrite(IREE::HAL::InterfaceBindingSubspanOp subspanOp,
@@ -403,7 +399,7 @@ static int64_t getMemoryAccessByteSize(Type type) {
 }
 
 struct ConvertHALInstrumentWorkgroupOp
-    : public ConvertOpToLLVMWithABIPattern<IREE::HAL::InstrumentWorkgroupOp> {
+    : ConvertOpToLLVMWithABIPattern<IREE::HAL::InstrumentWorkgroupOp> {
   using ConvertOpToLLVMWithABIPattern::ConvertOpToLLVMWithABIPattern;
   LogicalResult
   matchAndRewrite(IREE::HAL::InstrumentWorkgroupOp instrumentOp,
@@ -516,7 +512,7 @@ static std::optional<uint64_t> mapValueType(Type type) {
 }
 
 struct ConvertHALInstrumentValueOp
-    : public ConvertOpToLLVMWithABIPattern<IREE::HAL::InstrumentValueOp> {
+    : ConvertOpToLLVMWithABIPattern<IREE::HAL::InstrumentValueOp> {
   using ConvertOpToLLVMWithABIPattern::ConvertOpToLLVMWithABIPattern;
   LogicalResult
   matchAndRewrite(IREE::HAL::InstrumentValueOp instrumentOp,
@@ -584,7 +580,7 @@ struct ConvertHALInstrumentValueOp
 };
 
 struct ConvertHALInstrumentMemoryLoadOp
-    : public ConvertOpToLLVMWithABIPattern<IREE::HAL::InstrumentMemoryLoadOp> {
+    : ConvertOpToLLVMWithABIPattern<IREE::HAL::InstrumentMemoryLoadOp> {
   using ConvertOpToLLVMWithABIPattern::ConvertOpToLLVMWithABIPattern;
   LogicalResult
   matchAndRewrite(IREE::HAL::InstrumentMemoryLoadOp instrumentOp,
@@ -632,7 +628,7 @@ struct ConvertHALInstrumentMemoryLoadOp
 };
 
 struct ConvertHALInstrumentMemoryStoreOp
-    : public ConvertOpToLLVMWithABIPattern<IREE::HAL::InstrumentMemoryStoreOp> {
+    : ConvertOpToLLVMWithABIPattern<IREE::HAL::InstrumentMemoryStoreOp> {
   using ConvertOpToLLVMWithABIPattern::ConvertOpToLLVMWithABIPattern;
   LogicalResult
   matchAndRewrite(IREE::HAL::InstrumentMemoryStoreOp instrumentOp,
@@ -709,7 +705,7 @@ static IREE::HAL::CallingConvention getCallingConvention(Operation *forOp) {
 /// Note: this is an LLVM::CallOp -> LLVM::CallOp rewrite that is introduced
 /// after all conversions are done. Importantly, this is not a conversion
 /// pattern.
-struct RewriteFuncOpABI : public OpRewritePattern<LLVM::LLVMFuncOp> {
+struct RewriteFuncOpABI : OpRewritePattern<LLVM::LLVMFuncOp> {
   RewriteFuncOpABI(HALDispatchABI &abi, LLVMTypeConverter &typeConverter)
       : OpRewritePattern(&typeConverter.getContext()), abi(abi) {}
 
@@ -766,7 +762,7 @@ struct RewriteFuncOpABI : public OpRewritePattern<LLVM::LLVMFuncOp> {
 /// Note: this is an LLVM::CallOp -> LLVM::CallOp rewrite that is introduced
 /// after all conversions are done. Importantly, this is not a conversion
 /// pattern.
-struct RewriteCallOpABI : public OpRewritePattern<LLVM::CallOp> {
+struct RewriteCallOpABI : OpRewritePattern<LLVM::CallOp> {
   RewriteCallOpABI(HALDispatchABI &abi, LLVMTypeConverter &typeConverter)
       : OpRewritePattern(&typeConverter.getContext()), abi(abi) {}
 
@@ -813,7 +809,7 @@ struct RewriteCallOpABI : public OpRewritePattern<LLVM::CallOp> {
 /// after all conversions are done. Importantly, this is not a conversion
 /// pattern.
 struct RewriteExternCallOpToDynamicImportCallOp
-    : public OpRewritePattern<LLVM::CallOp> {
+    : OpRewritePattern<LLVM::CallOp> {
   RewriteExternCallOpToDynamicImportCallOp(HALDispatchABI &abi,
                                            LLVMTypeConverter &typeConverter)
       : OpRewritePattern(&typeConverter.getContext()), abi(abi),
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/ExpandF16OpToF32Pass.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/ExpandF16OpToF32Pass.cpp
index 3fa5512ec7f6..65321dc17310 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/ExpandF16OpToF32Pass.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/ExpandF16OpToF32Pass.cpp
@@ -23,7 +23,7 @@ namespace {
 /// f16 operands to f32, performing the arithmetic operation on the extended
 /// operands, and then truncating the result back to f16.
 template <typename Op>
-struct ExpandF16OpToF32Pattern : public OpRewritePattern<Op> {
+struct ExpandF16OpToF32Pattern : OpRewritePattern<Op> {
 public:
   using OpRewritePattern<Op>::OpRewritePattern;
 
@@ -54,7 +54,7 @@ struct ExpandF16OpToF32Pattern : public OpRewritePattern<Op> {
 };
 
 struct ExpandF16OpToF32Pass
-    : public impl::ExpandF16OpToF32PassBase<ExpandF16OpToF32Pass> {
+    : impl::ExpandF16OpToF32PassBase<ExpandF16OpToF32Pass> {
   void getDependentDialects(DialectRegistry &registry) const override {
     registry.insert<linalg::LinalgDialect>();
   }
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUAssignConstantOrdinals.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUAssignConstantOrdinals.cpp
index 815fd344b0e8..fba858e36b92 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUAssignConstantOrdinals.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUAssignConstantOrdinals.cpp
@@ -16,7 +16,7 @@ namespace mlir::iree_compiler {
 namespace {
 
 struct LLVMCPUAssignConstantOrdinalsPass
-    : public impl::LLVMCPUAssignConstantOrdinalsPassBase<
+    : impl::LLVMCPUAssignConstantOrdinalsPassBase<
           LLVMCPUAssignConstantOrdinalsPass> {
   void runOnOperation() override {
     IREE::HAL::ExecutableVariantOp variantOp = getOperation();
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUAssignImportOrdinals.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUAssignImportOrdinals.cpp
index b7e6726d1560..05c77ac1cab1 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUAssignImportOrdinals.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUAssignImportOrdinals.cpp
@@ -17,7 +17,7 @@ namespace mlir::iree_compiler {
 namespace {
 
 struct LLVMCPUAssignImportOrdinalsPass
-    : public impl::LLVMCPUAssignImportOrdinalsPassBase<
+    : impl::LLVMCPUAssignImportOrdinalsPassBase<
           LLVMCPUAssignImportOrdinalsPass> {
   void runOnOperation() override {
     IREE::HAL::ExecutableVariantOp variantOp = getOperation();
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPULinkExecutables.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPULinkExecutables.cpp
index 0676a09973f6..5f84289dad09 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPULinkExecutables.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPULinkExecutables.cpp
@@ -78,7 +78,7 @@ static LogicalResult linkAllTargetExecutables(StringRef target, bool lazy,
 }
 
 struct LLVMCPULinkExecutablesPass
-    : public impl::LLVMCPULinkExecutablesPassBase<LLVMCPULinkExecutablesPass> {
+    : impl::LLVMCPULinkExecutablesPassBase<LLVMCPULinkExecutablesPass> {
   using Base::Base;
   void runOnOperation() override {
     mlir::ModuleOp moduleOp = getOperation();
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUMmt4dVectorLowering.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUMmt4dVectorLowering.cpp
index e54afa2d5454..a115ce4d5521 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUMmt4dVectorLowering.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUMmt4dVectorLowering.cpp
@@ -31,8 +31,7 @@ namespace mlir::iree_compiler {
 
 namespace {
 struct LLVMCPUMmt4dVectorLoweringPass
-    : public impl::LLVMCPUMmt4dVectorLoweringPassBase<
-          LLVMCPUMmt4dVectorLoweringPass> {
+    : impl::LLVMCPUMmt4dVectorLoweringPassBase<LLVMCPUMmt4dVectorLoweringPass> {
   using Base::Base;
 
   void getDependentDialects(DialectRegistry &registry) const override {
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUSynchronizeSymbolVisibility.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUSynchronizeSymbolVisibility.cpp
index 595161119b5c..9d7fc65381a2 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUSynchronizeSymbolVisibility.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/LLVMCPUSynchronizeSymbolVisibility.cpp
@@ -31,7 +31,7 @@ static void setVisibilityFromLinkage(SymbolOpInterface op,
 }
 
 struct LLVMCPUSynchronizeSymbolVisibilityPass
-    : public impl::LLVMCPUSynchronizeSymbolVisibilityPassBase<
+    : impl::LLVMCPUSynchronizeSymbolVisibilityPassBase<
           LLVMCPUSynchronizeSymbolVisibilityPass> {
   void runOnOperation() override {
     mlir::ModuleOp moduleOp = getOperation();
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.cpp
index 652d0add5629..5a0249343331 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/Passes.cpp
@@ -745,7 +745,7 @@ void registerCodegenLLVMCPUPasses() {
       });
 
   struct LinalgToLLVMPipelineOptions
-      : public PassPipelineOptions<LinalgToLLVMPipelineOptions> {
+      : PassPipelineOptions<LinalgToLLVMPipelineOptions> {
     Option<bool> enableArmSME{
         *this, "enable-arm-sme",
         llvm::cl::desc("Enable the ArmSME lowering pipeline.")};
diff --git a/compiler/src/iree/compiler/Codegen/LLVMCPU/VectorContractCustomKernels.cpp b/compiler/src/iree/compiler/Codegen/LLVMCPU/VectorContractCustomKernels.cpp
index 974527d74fed..86beaddd0a9a 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMCPU/VectorContractCustomKernels.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMCPU/VectorContractCustomKernels.cpp
@@ -1017,7 +1017,7 @@ class MMTCustomKernelPattern : public OpRewritePattern<vector::ContractionOp> {
 /// dot-product instructions (sdot).
 /// It matches the same patterns as MMT_8x4x8_i8i8i32_Aarch64Dotprod_InlineAsm
 struct MMT_8x4x8_i8i8i32_Aarch64Dotprod_Intrinsics
-    : public OpRewritePattern<vector::ContractionOp> {
+    : OpRewritePattern<vector::ContractionOp> {
 public:
   using Base::Base;
 
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToLLVM.cpp b/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToLLVM.cpp
index 7b14f54c0915..dd4663336267 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToLLVM.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToLLVM.cpp
@@ -114,7 +114,7 @@ namespace {
 /// Scalarize math ops. It is needed to lower vector operation that don't have
 /// vector support in CUDA and ROCM device library.
 template <typename MathOpTy>
-struct ScalarizeMathOp : public OpRewritePattern<MathOpTy> {
+struct ScalarizeMathOp : OpRewritePattern<MathOpTy> {
   using OpRewritePattern<MathOpTy>::OpRewritePattern;
 
   LogicalResult matchAndRewrite(MathOpTy mathOp,
@@ -149,7 +149,7 @@ struct ScalarizeMathOp : public OpRewritePattern<MathOpTy> {
   }
 };
 
-struct ConvertSharedMemAllocOp : public OpRewritePattern<memref::AllocOp> {
+struct ConvertSharedMemAllocOp : OpRewritePattern<memref::AllocOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(memref::AllocOp allocOp,
@@ -384,7 +384,7 @@ class ConvertFunc : public ConvertOpToLLVMPattern<func::FuncOp> {
 };
 
 struct ConvertIREEBindingSubspanOp final
-    : public ConvertOpToLLVMPattern<IREE::HAL::InterfaceBindingSubspanOp> {
+    : ConvertOpToLLVMPattern<IREE::HAL::InterfaceBindingSubspanOp> {
   using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern;
 
   LogicalResult
@@ -490,7 +490,7 @@ struct ConvertIREEBindingSubspanOp final
 };
 
 struct ConvertIREEConstantOp final
-    : public ConvertOpToLLVMPattern<IREE::HAL::InterfaceConstantLoadOp> {
+    : ConvertOpToLLVMPattern<IREE::HAL::InterfaceConstantLoadOp> {
   using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern;
 
   LogicalResult
@@ -571,7 +571,7 @@ struct ConvertIREEConstantOp final
 /// corresponding GPU ops.
 template <typename InterfaceOpTy, typename NewOpTy>
 struct HALInterfaceWorkgroupOpsConverter final
-    : public OpConversionPattern<InterfaceOpTy> {
+    : OpConversionPattern<InterfaceOpTy> {
   using OpConversionPattern<InterfaceOpTy>::OpConversionPattern;
 
   LogicalResult
@@ -605,7 +605,7 @@ class ConvertNullPointerOp
 };
 
 struct ConvertIREEUtilAssumeIntOp final
-    : public ConvertOpToLLVMPattern<IREE::Util::AssumeIntOp> {
+    : ConvertOpToLLVMPattern<IREE::Util::AssumeIntOp> {
   using ConvertOpToLLVMPattern::ConvertOpToLLVMPattern;
 
   LogicalResult
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToROCDL.cpp b/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToROCDL.cpp
index db9fad45f5ab..725a489b64df 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToROCDL.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/ConvertToROCDL.cpp
@@ -71,7 +71,7 @@ namespace {
 //   gfx90a-gfx11: rocdl.s.barrier
 //   gfx12+: rocdl.s.barrier.signal + rocdl.s.barrier.wait
 struct LowerGlobalSubgroupBarrier
-    : public OpRewritePattern<IREE::GPU::GlobalSubgroupBarrierOp> {
+    : OpRewritePattern<IREE::GPU::GlobalSubgroupBarrierOp> {
   LowerGlobalSubgroupBarrier(MLIRContext *context, amdgpu::Chipset chipset)
       : OpRewritePattern(context), chipset(chipset) {}
 
@@ -136,7 +136,7 @@ populateLowerGlobalSubgroupBarrierPatterns(RewritePatternSet &patterns,
 /// This only looks at successor mfmas within the same block and is best
 /// effort.
 constexpr StringLiteral kSwapName = "iree_gpu.swap_mfma";
-struct SwapSetPrioWithMFMA : public OpRewritePattern<ROCDL::SetPrioOp> {
+struct SwapSetPrioWithMFMA : OpRewritePattern<ROCDL::SetPrioOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(ROCDL::SetPrioOp setPrio,
                                 PatternRewriter &rewriter) const override {
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/KernelConfig.cpp b/compiler/src/iree/compiler/Codegen/LLVMGPU/KernelConfig.cpp
index 664ed3dcf323..29993acbdbeb 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/KernelConfig.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/KernelConfig.cpp
@@ -124,7 +124,7 @@ static llvm::cl::opt<bool> clDirectConvolution(
 // Custom parser for llvm::cl::opt<std::optional<uint64_t>>. Allows a flag to
 // be truly optional: unset on the command line means std::nullopt, while a
 // user-provided non-negative integer is stored in the optional.
-struct OptionalUInt64Parser : public llvm::cl::parser<std::optional<uint64_t>> {
+struct OptionalUInt64Parser : llvm::cl::parser<std::optional<uint64_t>> {
   OptionalUInt64Parser(llvm::cl::Option &O)
       : llvm::cl::parser<std::optional<uint64_t>>(O) {}
   bool parse(llvm::cl::Option &O, llvm::StringRef, llvm::StringRef arg,
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPUAssignConstantOrdinals.cpp b/compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPUAssignConstantOrdinals.cpp
index a7841657b4f2..6005d7428906 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPUAssignConstantOrdinals.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPUAssignConstantOrdinals.cpp
@@ -16,7 +16,7 @@ namespace mlir::iree_compiler {
 namespace {
 
 struct LLVMGPUAssignConstantOrdinalsPass
-    : public impl::LLVMGPUAssignConstantOrdinalsPassBase<
+    : impl::LLVMGPUAssignConstantOrdinalsPassBase<
           LLVMGPUAssignConstantOrdinalsPass> {
   void runOnOperation() override {
     IREE::HAL::ExecutableVariantOp variantOp = getOperation();
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPULinkExecutables.cpp b/compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPULinkExecutables.cpp
index d631a06a21a9..f836e4090841 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPULinkExecutables.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPULinkExecutables.cpp
@@ -119,7 +119,7 @@ static LogicalResult linkAllTargetExecutables(StringRef target, bool lazy,
 }
 
 struct LLVMGPULinkExecutablesPass
-    : public impl::LLVMGPULinkExecutablesPassBase<LLVMGPULinkExecutablesPass> {
+    : impl::LLVMGPULinkExecutablesPassBase<LLVMGPULinkExecutablesPass> {
   using Base::Base;
   void runOnOperation() override {
     mlir::ModuleOp moduleOp = getOperation();
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPUVectorLowering.cpp b/compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPUVectorLowering.cpp
index 2e6f2f5c33a8..ebdb9b4b663b 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPUVectorLowering.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPUVectorLowering.cpp
@@ -34,7 +34,7 @@ namespace mlir::iree_compiler {
 namespace {
 
 struct PromoteContractOperands final
-    : public vector::MaskableOpRewritePattern<vector::ContractionOp> {
+    : vector::MaskableOpRewritePattern<vector::ContractionOp> {
   using MaskableOpRewritePattern::MaskableOpRewritePattern;
 
   FailureOr<Value>
@@ -507,7 +507,7 @@ struct ContractToChainFMA final : OpRewritePattern<vector::ContractionOp> {
   }
 };
 
-struct UnrollElementwiseOps final : public RewritePattern {
+struct UnrollElementwiseOps final : RewritePattern {
   UnrollElementwiseOps(MLIRContext *context, PatternBenefit benefit = 1)
       : RewritePattern(MatchAnyOpTypeTag(), benefit, context) {}
 
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/TransformExtensions/LLVMGPUExtensions.cpp b/compiler/src/iree/compiler/Codegen/LLVMGPU/TransformExtensions/LLVMGPUExtensions.cpp
index a15a7e788cdb..a357f619562b 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/TransformExtensions/LLVMGPUExtensions.cpp
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/TransformExtensions/LLVMGPUExtensions.cpp
@@ -423,7 +423,7 @@ namespace {
 /// }
 /// gpu.synchronize
 /// %0 = memref.load %src[%c0] : memref<1024xf32>
-struct WarpOpLoad : public OpRewritePattern<gpu::WarpExecuteOnLane0Op> {
+struct WarpOpLoad : OpRewritePattern<gpu::WarpExecuteOnLane0Op> {
   using Base::Base;
   LogicalResult matchAndRewrite(gpu::WarpExecuteOnLane0Op warpOp,
                                 PatternRewriter &rewriter) const override {
@@ -470,7 +470,7 @@ struct WarpOpLoad : public OpRewritePattern<gpu::WarpExecuteOnLane0Op> {
 /// Shared memory allocations are represented as AllocOp in IREE but they
 /// really have the semantic of global variables. Therefore hoisting them is
 /// always correct for static allocations.
-struct HoistSharedMemoryAlloc : public OpRewritePattern<memref::AllocOp> {
+struct HoistSharedMemoryAlloc : OpRewritePattern<memref::AllocOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(memref::AllocOp alloc,
                                 PatternRewriter &rewriter) const override {
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/SPIRVVectorToGPUSubgroupMMAOps.cpp b/compiler/src/iree/compiler/Codegen/SPIRV/SPIRVVectorToGPUSubgroupMMAOps.cpp
index a6cd13bf264c..a6ccaadfba71 100644
--- a/compiler/src/iree/compiler/Codegen/SPIRV/SPIRVVectorToGPUSubgroupMMAOps.cpp
+++ b/compiler/src/iree/compiler/Codegen/SPIRV/SPIRVVectorToGPUSubgroupMMAOps.cpp
@@ -20,7 +20,7 @@ namespace mlir::iree_compiler {
 
 namespace {
 struct SPIRVVectorToGPUSubgroupMMAPass final
-    : public impl::SPIRVVectorToGPUSubgroupMMAPassBase<
+    : impl::SPIRVVectorToGPUSubgroupMMAPassBase<
           SPIRVVectorToGPUSubgroupMMAPass> {
   void getDependentDialects(DialectRegistry &registry) const override {
     registry.insert<affine::AffineDialect, gpu::GPUDialect,
diff --git a/compiler/src/iree/compiler/Codegen/SPIRV/SPIRVVectorizeLoadStore.cpp b/compiler/src/iree/compiler/Codegen/SPIRV/SPIRVVectorizeLoadStore.cpp
index 1428d1409cd7..a9cff496b2a9 100644
--- a/compiler/src/iree/compiler/Codegen/SPIRV/SPIRVVectorizeLoadStore.cpp
+++ b/compiler/src/iree/compiler/Codegen/SPIRV/SPIRVVectorizeLoadStore.cpp
@@ -696,7 +696,7 @@ class ProcessAssumeAlignment final
 };
 
 struct ProcessSubgroupMMALoad final
-    : public MemRefConversionPattern<gpu::SubgroupMmaLoadMatrixOp> {
+    : MemRefConversionPattern<gpu::SubgroupMmaLoadMatrixOp> {
   using MemRefConversionPattern::MemRefConversionPattern;
 
   LogicalResult
@@ -731,7 +731,7 @@ struct ProcessSubgroupMMALoad final
 };
 
 struct ProcessSubgroupMMAStore final
-    : public MemRefConversionPattern<gpu::SubgroupMmaStoreMatrixOp> {
+    : MemRefConversionPattern<gpu::SubgroupMmaStoreMatrixOp> {
   using MemRefConversionPattern::MemRefConversionPattern;
 
   LogicalResult
@@ -813,7 +813,7 @@ static Value predicateMaybeMaskedScalarTransfer(
 /// This is very specific to SPIR-V as pointer cannot be casted to vector type
 /// if any of the memory access is not vector.
 struct ScalarizeVectorTransferRead final
-    : public OpRewritePattern<vector::TransferReadOp> {
+    : OpRewritePattern<vector::TransferReadOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(vector::TransferReadOp readOp,
@@ -894,7 +894,7 @@ struct ScalarizeVectorTransferRead final
   }
 };
 
-struct ScalarizeVectorLoad final : public OpRewritePattern<vector::LoadOp> {
+struct ScalarizeVectorLoad final : OpRewritePattern<vector::LoadOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(vector::LoadOp loadOp,
@@ -940,7 +940,7 @@ struct ScalarizeVectorLoad final : public OpRewritePattern<vector::LoadOp> {
 };
 
 struct ScalarizeVectorTransferWrite final
-    : public OpRewritePattern<vector::TransferWriteOp> {
+    : OpRewritePattern<vector::TransferWriteOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(vector::TransferWriteOp writeOp,
@@ -1024,8 +1024,7 @@ struct ScalarizeVectorTransferWrite final
 /// We run this at the same time as scalarizing masked transfers to try to fold
 /// away any remaining mask creation ops as SPIR-V lacks support for masked
 /// operations.
-struct ReifyExtractOfCreateMask final
-    : public OpRewritePattern<vector::ExtractOp> {
+struct ReifyExtractOfCreateMask final : OpRewritePattern<vector::ExtractOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(vector::ExtractOp extractOp,
diff --git a/compiler/src/iree/compiler/Codegen/Transforms/AffineMinDistributedSCFCanonicalization.cpp b/compiler/src/iree/compiler/Codegen/Transforms/AffineMinDistributedSCFCanonicalization.cpp
index 8e2227590d04..0c448c1c9c77 100644
--- a/compiler/src/iree/compiler/Codegen/Transforms/AffineMinDistributedSCFCanonicalization.cpp
+++ b/compiler/src/iree/compiler/Codegen/Transforms/AffineMinDistributedSCFCanonicalization.cpp
@@ -170,7 +170,7 @@ static std::optional<int64_t> foldAffineMin(affine::AffineMinOp minOp) {
 
 namespace {
 struct AffineMinDistributedSCFCanonicalizationPattern
-    : public mlir::OpRewritePattern<mlir::affine::AffineMinOp> {
+    : mlir::OpRewritePattern<mlir::affine::AffineMinOp> {
   using Base::Base;
 
   mlir::LogicalResult
@@ -189,8 +189,8 @@ struct AffineMinDistributedSCFCanonicalizationPattern
 /// Pass to be able to test AffineMinDistributedSCFCanonicalizationPattern
 /// individually.
 struct AffineMinDistributedSCFCanonicalizationPass
-    : public PassWrapper<AffineMinDistributedSCFCanonicalizationPass,
-                         InterfacePass<mlir::FunctionOpInterface>> {
+    : PassWrapper<AffineMinDistributedSCFCanonicalizationPass,
+                  InterfacePass<mlir::FunctionOpInterface>> {
   MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(
       AffineMinDistributedSCFCanonicalizationPass)
 
diff --git a/compiler/src/iree/compiler/Codegen/Transforms/RemoveSingleIterationLoop.cpp b/compiler/src/iree/compiler/Codegen/Transforms/RemoveSingleIterationLoop.cpp
index 27d3f60e9859..ba3b518752e7 100644
--- a/compiler/src/iree/compiler/Codegen/Transforms/RemoveSingleIterationLoop.cpp
+++ b/compiler/src/iree/compiler/Codegen/Transforms/RemoveSingleIterationLoop.cpp
@@ -59,7 +59,7 @@ static void replaceForWithIf(PatternRewriter &rewriter, scf::ForOp op,
 
 namespace {
 /// Rewriting pattern that replaces single-iteration loops with their bodies.
-struct SimplifyTrivialLoops : public OpRewritePattern<scf::ForOp> {
+struct SimplifyTrivialLoops : OpRewritePattern<scf::ForOp> {
 
   SimplifyTrivialLoops(MLIRContext *context, ForControlFnRef controlFn)
       : OpRewritePattern(context), controlFn(controlFn) {}
diff --git a/compiler/src/iree/compiler/Codegen/Transforms/Transforms.cpp b/compiler/src/iree/compiler/Codegen/Transforms/Transforms.cpp
index eae38d50c49e..cb0a595239d1 100644
--- a/compiler/src/iree/compiler/Codegen/Transforms/Transforms.cpp
+++ b/compiler/src/iree/compiler/Codegen/Transforms/Transforms.cpp
@@ -649,7 +649,7 @@ static SmallVector<Attribute> appendSplitReductionMappingToWorkgroupMapping(
 // and lower corresponding to the workgoup mapping. The newly created
 // loop also has workgroup mapping.
 struct FoldSplitReductionForallWithWorkgroupForall
-    : public OpRewritePattern<scf::ForallOp> {
+    : OpRewritePattern<scf::ForallOp> {
   using Base::Base;
 
   LogicalResult matchAndRewrite(scf::ForallOp forallOp,
@@ -1018,7 +1018,7 @@ distributeLinalgOpsWithFilter(mlir::FunctionOpInterface funcOp,
 //===--------------------------------------------------------------------====//
 
 namespace {
-struct HoistForallFromFor : public OpRewritePattern<scf::ForOp> {
+struct HoistForallFromFor : OpRewritePattern<scf::ForOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(scf::ForOp loop,
                                 PatternRewriter &rewriter) const final {
@@ -1335,7 +1335,7 @@ namespace {
 /// may be too intrusive, so we only apply it selectively for now.
 // TODO: atm hardcoded on linalg.fill but we could take any result of any
 // generic that yields a constant in that result.
-struct FoldFillIntoPad : public OpRewritePattern<tensor::PadOp> {
+struct FoldFillIntoPad : OpRewritePattern<tensor::PadOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(tensor::PadOp padOp,
                                 PatternRewriter &rewriter) const final {
diff --git a/compiler/src/iree/compiler/Codegen/Transforms/Transforms.h b/compiler/src/iree/compiler/Codegen/Transforms/Transforms.h
index c97fa5dd5161..9595647370a6 100644
--- a/compiler/src/iree/compiler/Codegen/Transforms/Transforms.h
+++ b/compiler/src/iree/compiler/Codegen/Transforms/Transforms.h
@@ -205,7 +205,7 @@ void populateFoldSplitReductionAndWorkgroupMappingLoops(
 /// Apply the `promoteSubViews` transformation as a pattern.
 /// `filter` controls LinalgTransformMarker matching and update when specified.
 /// See `promoteSubViews` for more details.
-struct LinalgBasePromotionPattern : public RewritePattern {
+struct LinalgBasePromotionPattern : RewritePattern {
   /// Entry point to match any LinalgOp
   /// OpInterface. MatchAnyOpTag-based constructor
   /// with a mandatory `filter`.
@@ -261,7 +261,7 @@ struct LinalgBasePromotionPattern : public RewritePattern {
 };
 
 template <typename OpTy>
-struct LinalgPromotionPattern : public LinalgBasePromotionPattern {
+struct LinalgPromotionPattern : LinalgBasePromotionPattern {
   /// SFINAE: This constructor can only trigger for
   /// concrete ops that have a static
   /// `getOperationName` method.
diff --git a/compiler/src/iree/compiler/Codegen/VMVX/VMVXAssignConstantOrdinals.cpp b/compiler/src/iree/compiler/Codegen/VMVX/VMVXAssignConstantOrdinals.cpp
index f36bb9ea059f..b34ac90c1b86 100644
--- a/compiler/src/iree/compiler/Codegen/VMVX/VMVXAssignConstantOrdinals.cpp
+++ b/compiler/src/iree/compiler/Codegen/VMVX/VMVXAssignConstantOrdinals.cpp
@@ -16,8 +16,7 @@ namespace mlir::iree_compiler {
 namespace {
 
 struct VMVXAssignConstantOrdinalsPass
-    : public impl::VMVXAssignConstantOrdinalsPassBase<
-          VMVXAssignConstantOrdinalsPass> {
+    : impl::VMVXAssignConstantOrdinalsPassBase<VMVXAssignConstantOrdinalsPass> {
   void runOnOperation() override {
     IREE::HAL::ExecutableVariantOp variantOp = getOperation();
 
diff --git a/compiler/src/iree/compiler/Codegen/VMVX/VMVXLinkExecutables.cpp b/compiler/src/iree/compiler/Codegen/VMVX/VMVXLinkExecutables.cpp
index 86d23ff7c6d5..50edd73076cc 100644
--- a/compiler/src/iree/compiler/Codegen/VMVX/VMVXLinkExecutables.cpp
+++ b/compiler/src/iree/compiler/Codegen/VMVX/VMVXLinkExecutables.cpp
@@ -80,7 +80,7 @@ static LogicalResult linkAllTargetExecutables(StringRef target, bool lazy,
 }
 
 struct VMVXLinkExecutablesPass
-    : public impl::VMVXLinkExecutablesPassBase<VMVXLinkExecutablesPass> {
+    : impl::VMVXLinkExecutablesPassBase<VMVXLinkExecutablesPass> {
   void runOnOperation() override {
     mlir::ModuleOp moduleOp = getOperation();
     auto moduleBuilder = OpBuilder::atBlockBegin(moduleOp.getBody());
diff --git a/compiler/src/iree/compiler/Codegen/VMVX/VMVXLowerLinalgMicrokernels.cpp b/compiler/src/iree/compiler/Codegen/VMVX/VMVXLowerLinalgMicrokernels.cpp
index 5cbf771dae03..e10332582e62 100644
--- a/compiler/src/iree/compiler/Codegen/VMVX/VMVXLowerLinalgMicrokernels.cpp
+++ b/compiler/src/iree/compiler/Codegen/VMVX/VMVXLowerLinalgMicrokernels.cpp
@@ -529,8 +529,7 @@ struct CopyEmitter {
 
 /// Matches a generic which contains an expressible binary operation, emitting
 /// as a vmvx op.
-struct LinalgBinaryGenericConversion
-    : public OpRewritePattern<linalg::GenericOp> {
+struct LinalgBinaryGenericConversion : OpRewritePattern<linalg::GenericOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(linalg::GenericOp op,
                                 PatternRewriter &rewriter) const override {
@@ -714,8 +713,7 @@ struct LinalgBinaryGenericConversion
 
 /// Matches a generic which contains an expressible unary operation, emitting
 /// as a vmvx op.
-struct LinalgUnaryGenericConversion
-    : public OpRewritePattern<linalg::GenericOp> {
+struct LinalgUnaryGenericConversion : OpRewritePattern<linalg::GenericOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(linalg::GenericOp op,
                                 PatternRewriter &rewriter) const override {
@@ -842,8 +840,7 @@ struct LinalgUnaryGenericConversion
 
 /// Matches a "trivial" generic which only yields, emitting as copy
 /// operation(s).
-struct LinalgTrivialGenericConversion
-    : public OpRewritePattern<linalg::GenericOp> {
+struct LinalgTrivialGenericConversion : OpRewritePattern<linalg::GenericOp> {
   using Base::Base;
   LogicalResult matchAndRewrite(linalg::GenericOp op,
                                 PatternRewriter &rewriter) const override {
@@ -885,7 +882,7 @@ struct LinalgTrivialGenericConversion
   }
 };
 
-struct LinalgFillConversion : public OpRewritePattern<linalg::FillOp> {
+struct LinalgFillConversion : OpRewritePattern<linalg::FillOp> {
   using Base::Base;
   struct OpInfo {
     linalg::FillOp op;