diff --git a/libclc/generic/include/clc/integer/integer-gentype.inc b/libclc/generic/include/clc/integer/integer-gentype.inc index 80e133f52fcaf..6b482ab25cefd 100644 --- a/libclc/generic/include/clc/integer/integer-gentype.inc +++ b/libclc/generic/include/clc/integer/integer-gentype.inc @@ -1,57 +1,51 @@ -#ifndef __CLC_BODY_U -#define __CLC_BODY_U __CLC_BODY -#endif -#ifndef __CLC_BODY_S -#define __CLC_BODY_S __CLC_BODY -#endif +#define __CLC_GEN_S #define __CLC_GENTYPE int -#include __CLC_BODY_S +#include __CLC_BODY #undef __CLC_GENTYPE #define __CLC_GENTYPE int2 -#include __CLC_BODY_S +#include __CLC_BODY #undef __CLC_GENTYPE #define __CLC_GENTYPE int3 -#include __CLC_BODY_S +#include __CLC_BODY #undef __CLC_GENTYPE #define __CLC_GENTYPE int4 -#include __CLC_BODY_S +#include __CLC_BODY #undef __CLC_GENTYPE #define __CLC_GENTYPE int8 -#include __CLC_BODY_S +#include __CLC_BODY #undef __CLC_GENTYPE #define __CLC_GENTYPE int16 -#include __CLC_BODY_S +#include __CLC_BODY #undef __CLC_GENTYPE +#undef __CLC_GEN_S + #define __CLC_GENTYPE uint -#include __CLC_BODY_U +#include __CLC_BODY #undef __CLC_GENTYPE #define __CLC_GENTYPE uint2 -#include __CLC_BODY_U +#include __CLC_BODY #undef __CLC_GENTYPE #define __CLC_GENTYPE uint3 -#include __CLC_BODY_U +#include __CLC_BODY #undef __CLC_GENTYPE #define __CLC_GENTYPE uint4 -#include __CLC_BODY_U +#include __CLC_BODY #undef __CLC_GENTYPE #define __CLC_GENTYPE uint8 -#include __CLC_BODY_U +#include __CLC_BODY #undef __CLC_GENTYPE #define __CLC_GENTYPE uint16 -#include __CLC_BODY_U +#include __CLC_BODY #undef __CLC_GENTYPE - -#undef __CLC_BODY_U -#undef __CLC_BODY_S diff --git a/libclc/generic/include/spirv/integer/definitions.h b/libclc/generic/include/spirv/integer/definitions.h deleted file mode 100644 index eb81e5184b624..0000000000000 --- a/libclc/generic/include/spirv/integer/definitions.h +++ /dev/null @@ -1,23 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define CHAR_BIT 8 -#define INT_MAX 2147483647 -#define INT_MIN (-2147483647 - 1) -#define LONG_MAX 0x7fffffffffffffffL -#define LONG_MIN (-0x7fffffffffffffffL - 1) -#define CHAR_MAX SCHAR_MAX -#define CHAR_MIN SCHAR_MIN -#define SCHAR_MAX 127 -#define SCHAR_MIN (-127 - 1) -#define SHRT_MAX 32767 -#define SHRT_MIN (-32767 - 1) -#define UCHAR_MAX 255 -#define USHRT_MAX 65535 -#define UINT_MAX 0xffffffff -#define ULONG_MAX 0xffffffffffffffffUL diff --git a/libclc/generic/include/spirv/integer/rotate.inc b/libclc/generic/include/spirv/integer/rotate.inc deleted file mode 100644 index 2cd78f39ce3c1..0000000000000 --- a/libclc/generic/include/spirv/integer/rotate.inc +++ /dev/null @@ -1,9 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_rotate(__SPIRV_GENTYPE x, __SPIRV_GENTYPE y); diff --git a/libclc/generic/include/spirv/shared/vload.h b/libclc/generic/include/spirv/shared/vload.h deleted file mode 100644 index 99c2571456c0b..0000000000000 --- a/libclc/generic/include/spirv/shared/vload.h +++ /dev/null @@ -1,67 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define _SPIRV_VLOAD_DECL(SUFFIX, MEM_TYPE, VEC_TYPE, WIDTH, ADDR_SPACE) \ - _CLC_OVERLOAD _CLC_DECL VEC_TYPE __spirv_ocl_vload##SUFFIXn__R##VEC_TYPE##WIDTH( \ - size_t offset, const ADDR_SPACE MEM_TYPE *x); - -#define _SPIRV_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, ADDR_SPACE) \ - _SPIRV_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##2, 2, ADDR_SPACE) \ - _SPIRV_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##3, 3, ADDR_SPACE) \ - _SPIRV_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##4, 4, ADDR_SPACE) \ - _SPIRV_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##8, 8, ADDR_SPACE) \ - _SPIRV_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##16, 16, ADDR_SPACE) - -#define _SPIRV_VECTOR_VLOAD_PRIM3(SUFFIX, MEM_TYPE, PRIM_TYPE) \ - _SPIRV_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __private) \ - _SPIRV_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __local) \ - _SPIRV_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __constant) \ - _SPIRV_VECTOR_VLOAD_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __global) - -#define _SPIRV_VECTOR_VLOAD_PRIM1(PRIM_TYPE) \ - _SPIRV_VECTOR_VLOAD_PRIM3(, PRIM_TYPE, PRIM_TYPE) - -// Declare vector load prototypes -_SPIRV_VECTOR_VLOAD_PRIM1(char) -_SPIRV_VECTOR_VLOAD_PRIM1(uchar) -_SPIRV_VECTOR_VLOAD_PRIM1(short) -_SPIRV_VECTOR_VLOAD_PRIM1(ushort) -_SPIRV_VECTOR_VLOAD_PRIM1(int) -_SPIRV_VECTOR_VLOAD_PRIM1(uint) -_SPIRV_VECTOR_VLOAD_PRIM1(long) -_SPIRV_VECTOR_VLOAD_PRIM1(ulong) -_SPIRV_VECTOR_VLOAD_PRIM1(float) -_SPIRV_VECTOR_VLOAD_PRIM3(_half, half, float) -// Use suffix to declare aligned vloada_halfN -_SPIRV_VECTOR_VLOAD_PRIM3(a_half, half, float) - -#ifdef cl_khr_fp64 -#pragma OPENCL EXTENSION cl_khr_fp64: enable - _SPIRV_VECTOR_VLOAD_PRIM1(double) -#endif -#ifdef cl_khr_fp16 -#pragma OPENCL EXTENSION cl_khr_fp16: enable - _SPIRV_VECTOR_VLOAD_PRIM1(half) -#endif - -// Scalar __spirv_ocl_vload_half__Rfloat also needs to be declared -_SPIRV_VLOAD_DECL(_half, half, float, , __constant) -_SPIRV_VLOAD_DECL(_half, half, float, , __global) -_SPIRV_VLOAD_DECL(_half, half, float, , __local) -_SPIRV_VLOAD_DECL(_half, half, float, , __private) - -// Scalar __spirv_ocl_vloada_half__Rfloat is not part of the specs but CTS expects it -_SPIRV_VLOAD_DECL(a_half, half, float, , __constant) -_SPIRV_VLOAD_DECL(a_half, half, float, , __global) -_SPIRV_VLOAD_DECL(a_half, half, float, , __local) -_SPIRV_VLOAD_DECL(a_half, half, float, , __private) - -#undef _SPIRV_VLOAD_DECL -#undef _SPIRV_VECTOR_VLOAD_DECL -#undef _SPIRV_VECTOR_VLOAD_PRIM3 -#undef _SPIRV_VECTOR_VLOAD_PRIM1 diff --git a/libclc/generic/include/spirv/shared/vstore.h b/libclc/generic/include/spirv/shared/vstore.h deleted file mode 100644 index dd8c9a6c12a4f..0000000000000 --- a/libclc/generic/include/spirv/shared/vstore.h +++ /dev/null @@ -1,70 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define _SPIRV_VSTORE_DECL(SUFFIX, PRIM_TYPE, VEC_TYPE, WIDTH, ADDR_SPACE, RND) \ - _CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren##SUFFIX##WIDTH##RND(VEC_TYPE vec, size_t offset, ADDR_SPACE PRIM_TYPE *out); - -#define _SPIRV_VECTOR_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, ADDR_SPACE, RND) \ - _SPIRV_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##2, 2, ADDR_SPACE, RND) \ - _SPIRV_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##3, 3, ADDR_SPACE, RND) \ - _SPIRV_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##4, 4, ADDR_SPACE, RND) \ - _SPIRV_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##8, 8, ADDR_SPACE, RND) \ - _SPIRV_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE##16, 16, ADDR_SPACE, RND) - -#define _SPIRV_VECTOR_VSTORE_PRIM3(SUFFIX, MEM_TYPE, PRIM_TYPE, RND) \ - _SPIRV_VECTOR_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __private, RND) \ - _SPIRV_VECTOR_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __local, RND) \ - _SPIRV_VECTOR_VSTORE_DECL(SUFFIX, MEM_TYPE, PRIM_TYPE, __global, RND) - -#define _SPIRV_VECTOR_VSTORE_PRIM1(PRIM_TYPE) \ - _SPIRV_VECTOR_VSTORE_PRIM3(,PRIM_TYPE, PRIM_TYPE, ) - -#define _SPIRV_VECTOR_VSTORE_HALF_PRIM1(PRIM_TYPE, RND) \ - _SPIRV_VSTORE_DECL(_half, half, PRIM_TYPE, , __private, RND) \ - _SPIRV_VSTORE_DECL(_half, half, PRIM_TYPE, , __local, RND) \ - _SPIRV_VSTORE_DECL(_half, half, PRIM_TYPE, , __global, RND) \ - _SPIRV_VECTOR_VSTORE_PRIM3(_half, half, PRIM_TYPE, RND) \ - _SPIRV_VSTORE_DECL(a_half, half, PRIM_TYPE, , __private, RND) \ - _SPIRV_VSTORE_DECL(a_half, half, PRIM_TYPE, , __local, RND) \ - _SPIRV_VSTORE_DECL(a_half, half, PRIM_TYPE, , __global, RND) \ - _SPIRV_VECTOR_VSTORE_PRIM3(a_half, half, PRIM_TYPE, RND) - -_SPIRV_VECTOR_VSTORE_PRIM1(char) -_SPIRV_VECTOR_VSTORE_PRIM1(uchar) -_SPIRV_VECTOR_VSTORE_PRIM1(short) -_SPIRV_VECTOR_VSTORE_PRIM1(ushort) -_SPIRV_VECTOR_VSTORE_PRIM1(int) -_SPIRV_VECTOR_VSTORE_PRIM1(uint) -_SPIRV_VECTOR_VSTORE_PRIM1(long) -_SPIRV_VECTOR_VSTORE_PRIM1(ulong) -_SPIRV_VECTOR_VSTORE_PRIM1(float) - -_SPIRV_VECTOR_VSTORE_HALF_PRIM1(float,) -_SPIRV_VECTOR_VSTORE_HALF_PRIM1(float, _rtz) -_SPIRV_VECTOR_VSTORE_HALF_PRIM1(float, _rtn) -_SPIRV_VECTOR_VSTORE_HALF_PRIM1(float, _rtp) -_SPIRV_VECTOR_VSTORE_HALF_PRIM1(float, _rte) - -#ifdef cl_khr_fp64 - _SPIRV_VECTOR_VSTORE_PRIM1(double) - _SPIRV_VECTOR_VSTORE_HALF_PRIM1(double,) - _SPIRV_VECTOR_VSTORE_HALF_PRIM1(double, _rtz) - _SPIRV_VECTOR_VSTORE_HALF_PRIM1(double, _rtn) - _SPIRV_VECTOR_VSTORE_HALF_PRIM1(double, _rtp) - _SPIRV_VECTOR_VSTORE_HALF_PRIM1(double, _rte) -#endif - -#ifdef cl_khr_fp16 - _SPIRV_VECTOR_VSTORE_PRIM1(half) -#endif - - -#undef _SPIRV_VSTORE_DECL -#undef _SPIRV_VECTOR_VSTORE_DECL -#undef _SPIRV_VECTOR_VSTORE_PRIM3 -#undef _SPIRV_VECTOR_VSTORE_PRIM1 diff --git a/libclc/generic/include/spirv/spirv.h b/libclc/generic/include/spirv/spirv.h index ad30de4b187c1..3c6e03d205058 100644 --- a/libclc/generic/include/spirv/spirv.h +++ b/libclc/generic/include/spirv/spirv.h @@ -146,22 +146,13 @@ /* 6.11.2.1 Floating-point macros */ #include -/* 6.11.3 Integer Functions */ -#include -#include -#include - /* 6.11.3 Integer Definitions */ #include -/* 6.11.2 and 6.11.3 Shared Integer/Math Functions */ -#include -#include - /* 6.11.4 Common Functions */ #include -#include #include +#include #include #include #include diff --git a/libclc/generic/include/spirv/spirv_builtins.h b/libclc/generic/include/spirv/spirv_builtins.h index 946bbbf7bc72b..5e63e7c7cce0b 100644 --- a/libclc/generic/include/spirv/spirv_builtins.h +++ b/libclc/generic/include/spirv/spirv_builtins.h @@ -12,6 +12,115 @@ #ifndef CLC_SPIRV_BINDING #define CLC_SPIRV_BINDING +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_char_t __spirv_BitCount(__clc_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t + __spirv_BitCount(__clc_vec2_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_char_t + __spirv_BitCount(__clc_vec3_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t + __spirv_BitCount(__clc_vec4_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t + __spirv_BitCount(__clc_vec8_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t + __spirv_BitCount(__clc_vec16_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int8_t __spirv_BitCount(__clc_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_BitCount(__clc_vec2_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_BitCount(__clc_vec3_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_BitCount(__clc_vec4_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_BitCount(__clc_vec8_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_BitCount(__clc_vec16_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int16_t __spirv_BitCount(__clc_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t + __spirv_BitCount(__clc_vec2_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int16_t + __spirv_BitCount(__clc_vec3_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t + __spirv_BitCount(__clc_vec4_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t + __spirv_BitCount(__clc_vec8_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t + __spirv_BitCount(__clc_vec16_int16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int32_t __spirv_BitCount(__clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_BitCount(__clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t + __spirv_BitCount(__clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_BitCount(__clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_BitCount(__clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_BitCount(__clc_vec16_int32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int64_t __spirv_BitCount(__clc_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t + __spirv_BitCount(__clc_vec2_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int64_t + __spirv_BitCount(__clc_vec3_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t + __spirv_BitCount(__clc_vec4_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t + __spirv_BitCount(__clc_vec8_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t + __spirv_BitCount(__clc_vec16_int64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_BitCount(__clc_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t + __spirv_BitCount(__clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t + __spirv_BitCount(__clc_vec3_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t + __spirv_BitCount(__clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t + __spirv_BitCount(__clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t + __spirv_BitCount(__clc_vec16_uint8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint16_t __spirv_BitCount(__clc_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t + __spirv_BitCount(__clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint16_t + __spirv_BitCount(__clc_vec3_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t + __spirv_BitCount(__clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t + __spirv_BitCount(__clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t + __spirv_BitCount(__clc_vec16_uint16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint32_t __spirv_BitCount(__clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t + __spirv_BitCount(__clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint32_t + __spirv_BitCount(__clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t + __spirv_BitCount(__clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t + __spirv_BitCount(__clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t + __spirv_BitCount(__clc_vec16_uint32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint64_t __spirv_BitCount(__clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t + __spirv_BitCount(__clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint64_t + __spirv_BitCount(__clc_vec3_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t + __spirv_BitCount(__clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t + __spirv_BitCount(__clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t + __spirv_BitCount(__clc_vec16_uint64_t); + _CLC_OVERLOAD _CLC_DECL _CLC_CONVERGENT void __spirv_ControlBarrier(__clc_uint32_t, __clc_uint32_t, __clc_uint32_t); @@ -11380,6 +11489,220 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint16_t _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint16_t __spirv_UConvert_Rushort_sat(__clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t __spirv_ocl_clz(__clc_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_clz(__clc_vec2_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_char_t __spirv_ocl_clz(__clc_vec3_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_char_t __spirv_ocl_clz(__clc_vec4_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_char_t __spirv_ocl_clz(__clc_vec8_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t + __spirv_ocl_clz(__clc_vec16_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int8_t __spirv_ocl_clz(__clc_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_ocl_clz(__clc_vec2_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_ocl_clz(__clc_vec3_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_ocl_clz(__clc_vec4_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_ocl_clz(__clc_vec8_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_ocl_clz(__clc_vec16_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int16_t __spirv_ocl_clz(__clc_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t + __spirv_ocl_clz(__clc_vec2_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int16_t + __spirv_ocl_clz(__clc_vec3_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t + __spirv_ocl_clz(__clc_vec4_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t + __spirv_ocl_clz(__clc_vec8_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t + __spirv_ocl_clz(__clc_vec16_int16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int32_t __spirv_ocl_clz(__clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_clz(__clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t + __spirv_ocl_clz(__clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_clz(__clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_clz(__clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_clz(__clc_vec16_int32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int64_t __spirv_ocl_clz(__clc_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t + __spirv_ocl_clz(__clc_vec2_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int64_t + __spirv_ocl_clz(__clc_vec3_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t + __spirv_ocl_clz(__clc_vec4_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t + __spirv_ocl_clz(__clc_vec8_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t + __spirv_ocl_clz(__clc_vec16_int64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_clz(__clc_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t + __spirv_ocl_clz(__clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t + __spirv_ocl_clz(__clc_vec3_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t + __spirv_ocl_clz(__clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t + __spirv_ocl_clz(__clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t + __spirv_ocl_clz(__clc_vec16_uint8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint16_t __spirv_ocl_clz(__clc_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t + __spirv_ocl_clz(__clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint16_t + __spirv_ocl_clz(__clc_vec3_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t + __spirv_ocl_clz(__clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t + __spirv_ocl_clz(__clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t + __spirv_ocl_clz(__clc_vec16_uint16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint32_t __spirv_ocl_clz(__clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t + __spirv_ocl_clz(__clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint32_t + __spirv_ocl_clz(__clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t + __spirv_ocl_clz(__clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t + __spirv_ocl_clz(__clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t + __spirv_ocl_clz(__clc_vec16_uint32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint64_t __spirv_ocl_clz(__clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t + __spirv_ocl_clz(__clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint64_t + __spirv_ocl_clz(__clc_vec3_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t + __spirv_ocl_clz(__clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t + __spirv_ocl_clz(__clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t + __spirv_ocl_clz(__clc_vec16_uint64_t); + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t __spirv_ocl_ctz(__clc_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_ctz(__clc_vec2_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_char_t __spirv_ocl_ctz(__clc_vec3_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_char_t __spirv_ocl_ctz(__clc_vec4_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_char_t __spirv_ocl_ctz(__clc_vec8_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t + __spirv_ocl_ctz(__clc_vec16_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int8_t __spirv_ocl_ctz(__clc_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_ocl_ctz(__clc_vec2_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_ocl_ctz(__clc_vec3_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_ocl_ctz(__clc_vec4_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_ocl_ctz(__clc_vec8_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_ocl_ctz(__clc_vec16_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int16_t __spirv_ocl_ctz(__clc_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t + __spirv_ocl_ctz(__clc_vec2_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int16_t + __spirv_ocl_ctz(__clc_vec3_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t + __spirv_ocl_ctz(__clc_vec4_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t + __spirv_ocl_ctz(__clc_vec8_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t + __spirv_ocl_ctz(__clc_vec16_int16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int32_t __spirv_ocl_ctz(__clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_ctz(__clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t + __spirv_ocl_ctz(__clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_ctz(__clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_ctz(__clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_ctz(__clc_vec16_int32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int64_t __spirv_ocl_ctz(__clc_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t + __spirv_ocl_ctz(__clc_vec2_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int64_t + __spirv_ocl_ctz(__clc_vec3_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t + __spirv_ocl_ctz(__clc_vec4_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t + __spirv_ocl_ctz(__clc_vec8_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t + __spirv_ocl_ctz(__clc_vec16_int64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_ctz(__clc_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t + __spirv_ocl_ctz(__clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t + __spirv_ocl_ctz(__clc_vec3_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t + __spirv_ocl_ctz(__clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t + __spirv_ocl_ctz(__clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t + __spirv_ocl_ctz(__clc_vec16_uint8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint16_t __spirv_ocl_ctz(__clc_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t + __spirv_ocl_ctz(__clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint16_t + __spirv_ocl_ctz(__clc_vec3_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t + __spirv_ocl_ctz(__clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t + __spirv_ocl_ctz(__clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t + __spirv_ocl_ctz(__clc_vec16_uint16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint32_t __spirv_ocl_ctz(__clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t + __spirv_ocl_ctz(__clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint32_t + __spirv_ocl_ctz(__clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t + __spirv_ocl_ctz(__clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t + __spirv_ocl_ctz(__clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t + __spirv_ocl_ctz(__clc_vec16_uint32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint64_t __spirv_ocl_ctz(__clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t + __spirv_ocl_ctz(__clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint64_t + __spirv_ocl_ctz(__clc_vec3_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t + __spirv_ocl_ctz(__clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t + __spirv_ocl_ctz(__clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t + __spirv_ocl_ctz(__clc_vec16_uint64_t); + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_fclamp(__clc_fp32_t, __clc_fp32_t, __clc_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t @@ -11423,6 +11746,115 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_fclamp( __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_fp16_t); #endif +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_char_t __spirv_ocl_popcount(__clc_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t + __spirv_ocl_popcount(__clc_vec2_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_char_t + __spirv_ocl_popcount(__clc_vec3_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t + __spirv_ocl_popcount(__clc_vec4_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t + __spirv_ocl_popcount(__clc_vec8_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t + __spirv_ocl_popcount(__clc_vec16_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int8_t __spirv_ocl_popcount(__clc_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_ocl_popcount(__clc_vec2_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_ocl_popcount(__clc_vec3_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_ocl_popcount(__clc_vec4_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_ocl_popcount(__clc_vec8_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_ocl_popcount(__clc_vec16_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int16_t __spirv_ocl_popcount(__clc_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t + __spirv_ocl_popcount(__clc_vec2_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int16_t + __spirv_ocl_popcount(__clc_vec3_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t + __spirv_ocl_popcount(__clc_vec4_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t + __spirv_ocl_popcount(__clc_vec8_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t + __spirv_ocl_popcount(__clc_vec16_int16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int32_t __spirv_ocl_popcount(__clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_popcount(__clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t + __spirv_ocl_popcount(__clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_popcount(__clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_popcount(__clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_popcount(__clc_vec16_int32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int64_t __spirv_ocl_popcount(__clc_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t + __spirv_ocl_popcount(__clc_vec2_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int64_t + __spirv_ocl_popcount(__clc_vec3_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t + __spirv_ocl_popcount(__clc_vec4_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t + __spirv_ocl_popcount(__clc_vec8_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t + __spirv_ocl_popcount(__clc_vec16_int64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_popcount(__clc_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t + __spirv_ocl_popcount(__clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t + __spirv_ocl_popcount(__clc_vec3_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t + __spirv_ocl_popcount(__clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t + __spirv_ocl_popcount(__clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t + __spirv_ocl_popcount(__clc_vec16_uint8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint16_t __spirv_ocl_popcount(__clc_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t + __spirv_ocl_popcount(__clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint16_t + __spirv_ocl_popcount(__clc_vec3_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t + __spirv_ocl_popcount(__clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t + __spirv_ocl_popcount(__clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t + __spirv_ocl_popcount(__clc_vec16_uint16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint32_t __spirv_ocl_popcount(__clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t + __spirv_ocl_popcount(__clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint32_t + __spirv_ocl_popcount(__clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t + __spirv_ocl_popcount(__clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t + __spirv_ocl_popcount(__clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t + __spirv_ocl_popcount(__clc_vec16_uint32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint64_t __spirv_ocl_popcount(__clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t + __spirv_ocl_popcount(__clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint64_t + __spirv_ocl_popcount(__clc_vec3_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t + __spirv_ocl_popcount(__clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t + __spirv_ocl_popcount(__clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t + __spirv_ocl_popcount(__clc_vec16_uint64_t); + _CLC_OVERLOAD _CLC_DECL void __spirv_ocl_prefetch(__clc_char_t const __global *, __clc_size_t); _CLC_OVERLOAD _CLC_DECL void @@ -11574,8 +12006,115 @@ _CLC_OVERLOAD _CLC_DECL void __spirv_ocl_prefetch(__clc_vec16_fp16_t const __global *, __clc_size_t); #endif -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_s_abs(__clc_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t + __spirv_ocl_rotate(__clc_char_t, __clc_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t + __spirv_ocl_rotate(__clc_vec2_char_t, __clc_vec2_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_char_t + __spirv_ocl_rotate(__clc_vec3_char_t, __clc_vec3_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_char_t + __spirv_ocl_rotate(__clc_vec4_char_t, __clc_vec4_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_char_t + __spirv_ocl_rotate(__clc_vec8_char_t, __clc_vec8_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t + __spirv_ocl_rotate(__clc_vec16_char_t, __clc_vec16_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int8_t + __spirv_ocl_rotate(__clc_int8_t, __clc_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t + __spirv_ocl_rotate(__clc_vec2_int8_t, __clc_vec2_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t + __spirv_ocl_rotate(__clc_vec3_int8_t, __clc_vec3_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t + __spirv_ocl_rotate(__clc_vec4_int8_t, __clc_vec4_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t + __spirv_ocl_rotate(__clc_vec8_int8_t, __clc_vec8_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_ocl_rotate(__clc_vec16_int8_t, __clc_vec16_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int16_t + __spirv_ocl_rotate(__clc_int16_t, __clc_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t + __spirv_ocl_rotate(__clc_vec2_int16_t, __clc_vec2_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int16_t + __spirv_ocl_rotate(__clc_vec3_int16_t, __clc_vec3_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t + __spirv_ocl_rotate(__clc_vec4_int16_t, __clc_vec4_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t + __spirv_ocl_rotate(__clc_vec8_int16_t, __clc_vec8_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t + __spirv_ocl_rotate(__clc_vec16_int16_t, __clc_vec16_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int32_t + __spirv_ocl_rotate(__clc_int32_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_rotate(__clc_vec2_int32_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t + __spirv_ocl_rotate(__clc_vec3_int32_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_rotate(__clc_vec4_int32_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_rotate(__clc_vec8_int32_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_rotate(__clc_vec16_int32_t, __clc_vec16_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int64_t + __spirv_ocl_rotate(__clc_int64_t, __clc_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t + __spirv_ocl_rotate(__clc_vec2_int64_t, __clc_vec2_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int64_t + __spirv_ocl_rotate(__clc_vec3_int64_t, __clc_vec3_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t + __spirv_ocl_rotate(__clc_vec4_int64_t, __clc_vec4_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t + __spirv_ocl_rotate(__clc_vec8_int64_t, __clc_vec8_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t + __spirv_ocl_rotate(__clc_vec16_int64_t, __clc_vec16_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint8_t + __spirv_ocl_rotate(__clc_uint8_t, __clc_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t + __spirv_ocl_rotate(__clc_vec2_uint8_t, __clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t + __spirv_ocl_rotate(__clc_vec3_uint8_t, __clc_vec3_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t + __spirv_ocl_rotate(__clc_vec4_uint8_t, __clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t + __spirv_ocl_rotate(__clc_vec8_uint8_t, __clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t + __spirv_ocl_rotate(__clc_vec16_uint8_t, __clc_vec16_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint16_t + __spirv_ocl_rotate(__clc_uint16_t, __clc_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t + __spirv_ocl_rotate(__clc_vec2_uint16_t, __clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint16_t + __spirv_ocl_rotate(__clc_vec3_uint16_t, __clc_vec3_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t + __spirv_ocl_rotate(__clc_vec4_uint16_t, __clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t + __spirv_ocl_rotate(__clc_vec8_uint16_t, __clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t + __spirv_ocl_rotate(__clc_vec16_uint16_t, __clc_vec16_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint32_t + __spirv_ocl_rotate(__clc_uint32_t, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t + __spirv_ocl_rotate(__clc_vec2_uint32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint32_t + __spirv_ocl_rotate(__clc_vec3_uint32_t, __clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t + __spirv_ocl_rotate(__clc_vec4_uint32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t + __spirv_ocl_rotate(__clc_vec8_uint32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t + __spirv_ocl_rotate(__clc_vec16_uint32_t, __clc_vec16_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint64_t + __spirv_ocl_rotate(__clc_uint64_t, __clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t + __spirv_ocl_rotate(__clc_vec2_uint64_t, __clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint64_t + __spirv_ocl_rotate(__clc_vec3_uint64_t, __clc_vec3_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t + __spirv_ocl_rotate(__clc_vec4_uint64_t, __clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t + __spirv_ocl_rotate(__clc_vec8_uint64_t, __clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t + __spirv_ocl_rotate(__clc_vec16_uint64_t, __clc_vec16_uint64_t); + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_s_abs(__clc_int8_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t @@ -12878,4 +13417,1555 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t __spirv_ocl_u_upsample(__clc_vec16_uint32_t, __clc_vec16_uint32_t); +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t +__spirv_ocl_vload_half(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t +__spirv_ocl_vload_half(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t +__spirv_ocl_vload_half(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t +__spirv_ocl_vload_half(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_vload_halfn_Rfloat16(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_vload_halfn_Rfloat16(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_vload_halfn_Rfloat16(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_vload_halfn_Rfloat16(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_vload_halfn_Rfloat2(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_vload_halfn_Rfloat2(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_vload_halfn_Rfloat2(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_vload_halfn_Rfloat2(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_vload_halfn_Rfloat3(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_vload_halfn_Rfloat3(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_vload_halfn_Rfloat3(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_vload_halfn_Rfloat3(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_vload_halfn_Rfloat4(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_vload_halfn_Rfloat4(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_vload_halfn_Rfloat4(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_vload_halfn_Rfloat4(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_vload_halfn_Rfloat8(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_vload_halfn_Rfloat8(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_vload_halfn_Rfloat8(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_vload_halfn_Rfloat8(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_vloada_halfn_Rfloat16(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_vloada_halfn_Rfloat16(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_vloada_halfn_Rfloat16(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t __spirv_ocl_vloada_halfn_Rfloat16( + __clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_vloada_halfn_Rfloat2(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_vloada_halfn_Rfloat2(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_vloada_halfn_Rfloat2(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_vloada_halfn_Rfloat2(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_vloada_halfn_Rfloat3(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_vloada_halfn_Rfloat3(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_vloada_halfn_Rfloat3(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_vloada_halfn_Rfloat3(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_vloada_halfn_Rfloat4(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_vloada_halfn_Rfloat4(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_vloada_halfn_Rfloat4(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_vloada_halfn_Rfloat4(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_vloada_halfn_Rfloat8(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_vloada_halfn_Rfloat8(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_vloada_halfn_Rfloat8(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_vloada_halfn_Rfloat8(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +_CLC_OVERLOAD _CLC_DECL __clc_vec16_char_t +__spirv_ocl_vloadn_Rchar16(__clc_size_t, __clc_char_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_char_t +__spirv_ocl_vloadn_Rchar16(__clc_size_t, __clc_char_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_char_t +__spirv_ocl_vloadn_Rchar16(__clc_size_t, __clc_char_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_char_t +__spirv_ocl_vloadn_Rchar16(__clc_size_t, __clc_char_t const __constant *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int8_t +__spirv_ocl_vloadn_Rchar16(__clc_size_t, __clc_int8_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int8_t +__spirv_ocl_vloadn_Rchar16(__clc_size_t, __clc_int8_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int8_t +__spirv_ocl_vloadn_Rchar16(__clc_size_t, __clc_int8_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int8_t +__spirv_ocl_vloadn_Rchar16(__clc_size_t, __clc_int8_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec2_char_t +__spirv_ocl_vloadn_Rchar2(__clc_size_t, __clc_char_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_char_t +__spirv_ocl_vloadn_Rchar2(__clc_size_t, __clc_char_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_char_t +__spirv_ocl_vloadn_Rchar2(__clc_size_t, __clc_char_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_char_t +__spirv_ocl_vloadn_Rchar2(__clc_size_t, __clc_char_t const __constant *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int8_t +__spirv_ocl_vloadn_Rchar2(__clc_size_t, __clc_int8_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int8_t +__spirv_ocl_vloadn_Rchar2(__clc_size_t, __clc_int8_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int8_t +__spirv_ocl_vloadn_Rchar2(__clc_size_t, __clc_int8_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int8_t +__spirv_ocl_vloadn_Rchar2(__clc_size_t, __clc_int8_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec3_char_t +__spirv_ocl_vloadn_Rchar3(__clc_size_t, __clc_char_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_char_t +__spirv_ocl_vloadn_Rchar3(__clc_size_t, __clc_char_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_char_t +__spirv_ocl_vloadn_Rchar3(__clc_size_t, __clc_char_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_char_t +__spirv_ocl_vloadn_Rchar3(__clc_size_t, __clc_char_t const __constant *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int8_t +__spirv_ocl_vloadn_Rchar3(__clc_size_t, __clc_int8_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int8_t +__spirv_ocl_vloadn_Rchar3(__clc_size_t, __clc_int8_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int8_t +__spirv_ocl_vloadn_Rchar3(__clc_size_t, __clc_int8_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int8_t +__spirv_ocl_vloadn_Rchar3(__clc_size_t, __clc_int8_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec4_char_t +__spirv_ocl_vloadn_Rchar4(__clc_size_t, __clc_char_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_char_t +__spirv_ocl_vloadn_Rchar4(__clc_size_t, __clc_char_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_char_t +__spirv_ocl_vloadn_Rchar4(__clc_size_t, __clc_char_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_char_t +__spirv_ocl_vloadn_Rchar4(__clc_size_t, __clc_char_t const __constant *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int8_t +__spirv_ocl_vloadn_Rchar4(__clc_size_t, __clc_int8_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int8_t +__spirv_ocl_vloadn_Rchar4(__clc_size_t, __clc_int8_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int8_t +__spirv_ocl_vloadn_Rchar4(__clc_size_t, __clc_int8_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int8_t +__spirv_ocl_vloadn_Rchar4(__clc_size_t, __clc_int8_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec8_char_t +__spirv_ocl_vloadn_Rchar8(__clc_size_t, __clc_char_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_char_t +__spirv_ocl_vloadn_Rchar8(__clc_size_t, __clc_char_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_char_t +__spirv_ocl_vloadn_Rchar8(__clc_size_t, __clc_char_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_char_t +__spirv_ocl_vloadn_Rchar8(__clc_size_t, __clc_char_t const __constant *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int8_t +__spirv_ocl_vloadn_Rchar8(__clc_size_t, __clc_int8_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int8_t +__spirv_ocl_vloadn_Rchar8(__clc_size_t, __clc_int8_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int8_t +__spirv_ocl_vloadn_Rchar8(__clc_size_t, __clc_int8_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int8_t +__spirv_ocl_vloadn_Rchar8(__clc_size_t, __clc_int8_t const __constant *); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_vloadn_Rdouble16(__clc_size_t, __clc_fp64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_vloadn_Rdouble16(__clc_size_t, __clc_fp64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_vloadn_Rdouble16(__clc_size_t, __clc_fp64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_vloadn_Rdouble16(__clc_size_t, __clc_fp64_t const __constant *); +#endif + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_vloadn_Rdouble2(__clc_size_t, __clc_fp64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_vloadn_Rdouble2(__clc_size_t, __clc_fp64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_vloadn_Rdouble2(__clc_size_t, __clc_fp64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_vloadn_Rdouble2(__clc_size_t, __clc_fp64_t const __constant *); +#endif + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_vloadn_Rdouble3(__clc_size_t, __clc_fp64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_vloadn_Rdouble3(__clc_size_t, __clc_fp64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_vloadn_Rdouble3(__clc_size_t, __clc_fp64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_vloadn_Rdouble3(__clc_size_t, __clc_fp64_t const __constant *); +#endif + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_vloadn_Rdouble4(__clc_size_t, __clc_fp64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_vloadn_Rdouble4(__clc_size_t, __clc_fp64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_vloadn_Rdouble4(__clc_size_t, __clc_fp64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_vloadn_Rdouble4(__clc_size_t, __clc_fp64_t const __constant *); +#endif + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_vloadn_Rdouble8(__clc_size_t, __clc_fp64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_vloadn_Rdouble8(__clc_size_t, __clc_fp64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_vloadn_Rdouble8(__clc_size_t, __clc_fp64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_vloadn_Rdouble8(__clc_size_t, __clc_fp64_t const __constant *); +#endif + +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_vloadn_Rfloat16(__clc_size_t, __clc_fp32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_vloadn_Rfloat16(__clc_size_t, __clc_fp32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_vloadn_Rfloat16(__clc_size_t, __clc_fp32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_vloadn_Rfloat16(__clc_size_t, __clc_fp32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_vloadn_Rfloat2(__clc_size_t, __clc_fp32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_vloadn_Rfloat2(__clc_size_t, __clc_fp32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_vloadn_Rfloat2(__clc_size_t, __clc_fp32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_vloadn_Rfloat2(__clc_size_t, __clc_fp32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_vloadn_Rfloat3(__clc_size_t, __clc_fp32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_vloadn_Rfloat3(__clc_size_t, __clc_fp32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_vloadn_Rfloat3(__clc_size_t, __clc_fp32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_vloadn_Rfloat3(__clc_size_t, __clc_fp32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_vloadn_Rfloat4(__clc_size_t, __clc_fp32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_vloadn_Rfloat4(__clc_size_t, __clc_fp32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_vloadn_Rfloat4(__clc_size_t, __clc_fp32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_vloadn_Rfloat4(__clc_size_t, __clc_fp32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_vloadn_Rfloat8(__clc_size_t, __clc_fp32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_vloadn_Rfloat8(__clc_size_t, __clc_fp32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_vloadn_Rfloat8(__clc_size_t, __clc_fp32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_vloadn_Rfloat8(__clc_size_t, __clc_fp32_t const __constant *); + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_vloadn_Rhalf16(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_vloadn_Rhalf16(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_vloadn_Rhalf16(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_vloadn_Rhalf16(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_vloadn_Rhalf2(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_vloadn_Rhalf2(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_vloadn_Rhalf2(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_vloadn_Rhalf2(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_vloadn_Rhalf3(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_vloadn_Rhalf3(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_vloadn_Rhalf3(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_vloadn_Rhalf3(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_vloadn_Rhalf4(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_vloadn_Rhalf4(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_vloadn_Rhalf4(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_vloadn_Rhalf4(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_vloadn_Rhalf8(__clc_size_t, __clc_fp16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_vloadn_Rhalf8(__clc_size_t, __clc_fp16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_vloadn_Rhalf8(__clc_size_t, __clc_fp16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_vloadn_Rhalf8(__clc_size_t, __clc_fp16_t const __constant *); +#endif + +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int32_t +__spirv_ocl_vloadn_Rint16(__clc_size_t, __clc_int32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int32_t +__spirv_ocl_vloadn_Rint16(__clc_size_t, __clc_int32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int32_t +__spirv_ocl_vloadn_Rint16(__clc_size_t, __clc_int32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int32_t +__spirv_ocl_vloadn_Rint16(__clc_size_t, __clc_int32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int32_t +__spirv_ocl_vloadn_Rint2(__clc_size_t, __clc_int32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int32_t +__spirv_ocl_vloadn_Rint2(__clc_size_t, __clc_int32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int32_t +__spirv_ocl_vloadn_Rint2(__clc_size_t, __clc_int32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int32_t +__spirv_ocl_vloadn_Rint2(__clc_size_t, __clc_int32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int32_t +__spirv_ocl_vloadn_Rint3(__clc_size_t, __clc_int32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int32_t +__spirv_ocl_vloadn_Rint3(__clc_size_t, __clc_int32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int32_t +__spirv_ocl_vloadn_Rint3(__clc_size_t, __clc_int32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int32_t +__spirv_ocl_vloadn_Rint3(__clc_size_t, __clc_int32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int32_t +__spirv_ocl_vloadn_Rint4(__clc_size_t, __clc_int32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int32_t +__spirv_ocl_vloadn_Rint4(__clc_size_t, __clc_int32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int32_t +__spirv_ocl_vloadn_Rint4(__clc_size_t, __clc_int32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int32_t +__spirv_ocl_vloadn_Rint4(__clc_size_t, __clc_int32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int32_t +__spirv_ocl_vloadn_Rint8(__clc_size_t, __clc_int32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int32_t +__spirv_ocl_vloadn_Rint8(__clc_size_t, __clc_int32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int32_t +__spirv_ocl_vloadn_Rint8(__clc_size_t, __clc_int32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int32_t +__spirv_ocl_vloadn_Rint8(__clc_size_t, __clc_int32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int64_t +__spirv_ocl_vloadn_Rlong16(__clc_size_t, __clc_int64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int64_t +__spirv_ocl_vloadn_Rlong16(__clc_size_t, __clc_int64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int64_t +__spirv_ocl_vloadn_Rlong16(__clc_size_t, __clc_int64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int64_t +__spirv_ocl_vloadn_Rlong16(__clc_size_t, __clc_int64_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int64_t +__spirv_ocl_vloadn_Rlong2(__clc_size_t, __clc_int64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int64_t +__spirv_ocl_vloadn_Rlong2(__clc_size_t, __clc_int64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int64_t +__spirv_ocl_vloadn_Rlong2(__clc_size_t, __clc_int64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int64_t +__spirv_ocl_vloadn_Rlong2(__clc_size_t, __clc_int64_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int64_t +__spirv_ocl_vloadn_Rlong3(__clc_size_t, __clc_int64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int64_t +__spirv_ocl_vloadn_Rlong3(__clc_size_t, __clc_int64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int64_t +__spirv_ocl_vloadn_Rlong3(__clc_size_t, __clc_int64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int64_t +__spirv_ocl_vloadn_Rlong3(__clc_size_t, __clc_int64_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int64_t +__spirv_ocl_vloadn_Rlong4(__clc_size_t, __clc_int64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int64_t +__spirv_ocl_vloadn_Rlong4(__clc_size_t, __clc_int64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int64_t +__spirv_ocl_vloadn_Rlong4(__clc_size_t, __clc_int64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int64_t +__spirv_ocl_vloadn_Rlong4(__clc_size_t, __clc_int64_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int64_t +__spirv_ocl_vloadn_Rlong8(__clc_size_t, __clc_int64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int64_t +__spirv_ocl_vloadn_Rlong8(__clc_size_t, __clc_int64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int64_t +__spirv_ocl_vloadn_Rlong8(__clc_size_t, __clc_int64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int64_t +__spirv_ocl_vloadn_Rlong8(__clc_size_t, __clc_int64_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int16_t +__spirv_ocl_vloadn_Rshort16(__clc_size_t, __clc_int16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int16_t +__spirv_ocl_vloadn_Rshort16(__clc_size_t, __clc_int16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int16_t +__spirv_ocl_vloadn_Rshort16(__clc_size_t, __clc_int16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_int16_t +__spirv_ocl_vloadn_Rshort16(__clc_size_t, __clc_int16_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int16_t +__spirv_ocl_vloadn_Rshort2(__clc_size_t, __clc_int16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int16_t +__spirv_ocl_vloadn_Rshort2(__clc_size_t, __clc_int16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int16_t +__spirv_ocl_vloadn_Rshort2(__clc_size_t, __clc_int16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_int16_t +__spirv_ocl_vloadn_Rshort2(__clc_size_t, __clc_int16_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int16_t +__spirv_ocl_vloadn_Rshort3(__clc_size_t, __clc_int16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int16_t +__spirv_ocl_vloadn_Rshort3(__clc_size_t, __clc_int16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int16_t +__spirv_ocl_vloadn_Rshort3(__clc_size_t, __clc_int16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_int16_t +__spirv_ocl_vloadn_Rshort3(__clc_size_t, __clc_int16_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int16_t +__spirv_ocl_vloadn_Rshort4(__clc_size_t, __clc_int16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int16_t +__spirv_ocl_vloadn_Rshort4(__clc_size_t, __clc_int16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int16_t +__spirv_ocl_vloadn_Rshort4(__clc_size_t, __clc_int16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_int16_t +__spirv_ocl_vloadn_Rshort4(__clc_size_t, __clc_int16_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int16_t +__spirv_ocl_vloadn_Rshort8(__clc_size_t, __clc_int16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int16_t +__spirv_ocl_vloadn_Rshort8(__clc_size_t, __clc_int16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int16_t +__spirv_ocl_vloadn_Rshort8(__clc_size_t, __clc_int16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_int16_t +__spirv_ocl_vloadn_Rshort8(__clc_size_t, __clc_int16_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint8_t +__spirv_ocl_vloadn_Ruchar16(__clc_size_t, __clc_uint8_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint8_t +__spirv_ocl_vloadn_Ruchar16(__clc_size_t, __clc_uint8_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint8_t +__spirv_ocl_vloadn_Ruchar16(__clc_size_t, __clc_uint8_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint8_t +__spirv_ocl_vloadn_Ruchar16(__clc_size_t, __clc_uint8_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint8_t +__spirv_ocl_vloadn_Ruchar2(__clc_size_t, __clc_uint8_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint8_t +__spirv_ocl_vloadn_Ruchar2(__clc_size_t, __clc_uint8_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint8_t +__spirv_ocl_vloadn_Ruchar2(__clc_size_t, __clc_uint8_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint8_t +__spirv_ocl_vloadn_Ruchar2(__clc_size_t, __clc_uint8_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint8_t +__spirv_ocl_vloadn_Ruchar3(__clc_size_t, __clc_uint8_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint8_t +__spirv_ocl_vloadn_Ruchar3(__clc_size_t, __clc_uint8_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint8_t +__spirv_ocl_vloadn_Ruchar3(__clc_size_t, __clc_uint8_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint8_t +__spirv_ocl_vloadn_Ruchar3(__clc_size_t, __clc_uint8_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint8_t +__spirv_ocl_vloadn_Ruchar4(__clc_size_t, __clc_uint8_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint8_t +__spirv_ocl_vloadn_Ruchar4(__clc_size_t, __clc_uint8_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint8_t +__spirv_ocl_vloadn_Ruchar4(__clc_size_t, __clc_uint8_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint8_t +__spirv_ocl_vloadn_Ruchar4(__clc_size_t, __clc_uint8_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint8_t +__spirv_ocl_vloadn_Ruchar8(__clc_size_t, __clc_uint8_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint8_t +__spirv_ocl_vloadn_Ruchar8(__clc_size_t, __clc_uint8_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint8_t +__spirv_ocl_vloadn_Ruchar8(__clc_size_t, __clc_uint8_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint8_t +__spirv_ocl_vloadn_Ruchar8(__clc_size_t, __clc_uint8_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint32_t +__spirv_ocl_vloadn_Ruint16(__clc_size_t, __clc_uint32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint32_t +__spirv_ocl_vloadn_Ruint16(__clc_size_t, __clc_uint32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint32_t +__spirv_ocl_vloadn_Ruint16(__clc_size_t, __clc_uint32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint32_t +__spirv_ocl_vloadn_Ruint16(__clc_size_t, __clc_uint32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint32_t +__spirv_ocl_vloadn_Ruint2(__clc_size_t, __clc_uint32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint32_t +__spirv_ocl_vloadn_Ruint2(__clc_size_t, __clc_uint32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint32_t +__spirv_ocl_vloadn_Ruint2(__clc_size_t, __clc_uint32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint32_t +__spirv_ocl_vloadn_Ruint2(__clc_size_t, __clc_uint32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint32_t +__spirv_ocl_vloadn_Ruint3(__clc_size_t, __clc_uint32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint32_t +__spirv_ocl_vloadn_Ruint3(__clc_size_t, __clc_uint32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint32_t +__spirv_ocl_vloadn_Ruint3(__clc_size_t, __clc_uint32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint32_t +__spirv_ocl_vloadn_Ruint3(__clc_size_t, __clc_uint32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint32_t +__spirv_ocl_vloadn_Ruint4(__clc_size_t, __clc_uint32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint32_t +__spirv_ocl_vloadn_Ruint4(__clc_size_t, __clc_uint32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint32_t +__spirv_ocl_vloadn_Ruint4(__clc_size_t, __clc_uint32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint32_t +__spirv_ocl_vloadn_Ruint4(__clc_size_t, __clc_uint32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint32_t +__spirv_ocl_vloadn_Ruint8(__clc_size_t, __clc_uint32_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint32_t +__spirv_ocl_vloadn_Ruint8(__clc_size_t, __clc_uint32_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint32_t +__spirv_ocl_vloadn_Ruint8(__clc_size_t, __clc_uint32_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint32_t +__spirv_ocl_vloadn_Ruint8(__clc_size_t, __clc_uint32_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint64_t +__spirv_ocl_vloadn_Rulong16(__clc_size_t, __clc_uint64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint64_t +__spirv_ocl_vloadn_Rulong16(__clc_size_t, __clc_uint64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint64_t +__spirv_ocl_vloadn_Rulong16(__clc_size_t, __clc_uint64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint64_t +__spirv_ocl_vloadn_Rulong16(__clc_size_t, __clc_uint64_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint64_t +__spirv_ocl_vloadn_Rulong2(__clc_size_t, __clc_uint64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint64_t +__spirv_ocl_vloadn_Rulong2(__clc_size_t, __clc_uint64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint64_t +__spirv_ocl_vloadn_Rulong2(__clc_size_t, __clc_uint64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint64_t +__spirv_ocl_vloadn_Rulong2(__clc_size_t, __clc_uint64_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint64_t +__spirv_ocl_vloadn_Rulong3(__clc_size_t, __clc_uint64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint64_t +__spirv_ocl_vloadn_Rulong3(__clc_size_t, __clc_uint64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint64_t +__spirv_ocl_vloadn_Rulong3(__clc_size_t, __clc_uint64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint64_t +__spirv_ocl_vloadn_Rulong3(__clc_size_t, __clc_uint64_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint64_t +__spirv_ocl_vloadn_Rulong4(__clc_size_t, __clc_uint64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint64_t +__spirv_ocl_vloadn_Rulong4(__clc_size_t, __clc_uint64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint64_t +__spirv_ocl_vloadn_Rulong4(__clc_size_t, __clc_uint64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint64_t +__spirv_ocl_vloadn_Rulong4(__clc_size_t, __clc_uint64_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint64_t +__spirv_ocl_vloadn_Rulong8(__clc_size_t, __clc_uint64_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint64_t +__spirv_ocl_vloadn_Rulong8(__clc_size_t, __clc_uint64_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint64_t +__spirv_ocl_vloadn_Rulong8(__clc_size_t, __clc_uint64_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint64_t +__spirv_ocl_vloadn_Rulong8(__clc_size_t, __clc_uint64_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint16_t +__spirv_ocl_vloadn_Rushort16(__clc_size_t, __clc_uint16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint16_t +__spirv_ocl_vloadn_Rushort16(__clc_size_t, __clc_uint16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint16_t +__spirv_ocl_vloadn_Rushort16(__clc_size_t, __clc_uint16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_uint16_t +__spirv_ocl_vloadn_Rushort16(__clc_size_t, __clc_uint16_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint16_t +__spirv_ocl_vloadn_Rushort2(__clc_size_t, __clc_uint16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint16_t +__spirv_ocl_vloadn_Rushort2(__clc_size_t, __clc_uint16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint16_t +__spirv_ocl_vloadn_Rushort2(__clc_size_t, __clc_uint16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_uint16_t +__spirv_ocl_vloadn_Rushort2(__clc_size_t, __clc_uint16_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint16_t +__spirv_ocl_vloadn_Rushort3(__clc_size_t, __clc_uint16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint16_t +__spirv_ocl_vloadn_Rushort3(__clc_size_t, __clc_uint16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint16_t +__spirv_ocl_vloadn_Rushort3(__clc_size_t, __clc_uint16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_uint16_t +__spirv_ocl_vloadn_Rushort3(__clc_size_t, __clc_uint16_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint16_t +__spirv_ocl_vloadn_Rushort4(__clc_size_t, __clc_uint16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint16_t +__spirv_ocl_vloadn_Rushort4(__clc_size_t, __clc_uint16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint16_t +__spirv_ocl_vloadn_Rushort4(__clc_size_t, __clc_uint16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_uint16_t +__spirv_ocl_vloadn_Rushort4(__clc_size_t, __clc_uint16_t const __constant *); + +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint16_t +__spirv_ocl_vloadn_Rushort8(__clc_size_t, __clc_uint16_t const *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint16_t +__spirv_ocl_vloadn_Rushort8(__clc_size_t, __clc_uint16_t const __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint16_t +__spirv_ocl_vloadn_Rushort8(__clc_size_t, __clc_uint16_t const __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_uint16_t +__spirv_ocl_vloadn_Rushort8(__clc_size_t, __clc_uint16_t const __constant *); + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_half(__clc_fp32_t, __clc_size_t, + __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_half(__clc_fp32_t, __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_half(__clc_fp32_t, __clc_size_t, + __clc_fp16_t __global *); +#endif + +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_half(__clc_fp64_t, __clc_size_t, + __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_half(__clc_fp64_t, __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_half(__clc_fp64_t, __clc_size_t, + __clc_fp16_t __global *); +#endif +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_half_r(__clc_fp32_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_half_r(__clc_fp32_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_half_r(__clc_fp32_t, + __clc_size_t, + __clc_fp16_t __global *, + __clc_uint32_t); +#endif + +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_half_r(__clc_fp64_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_half_r(__clc_fp64_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_half_r(__clc_fp64_t, + __clc_size_t, + __clc_fp16_t __global *, + __clc_uint32_t); +#endif +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstore_halfn(__clc_vec2_fp32_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec2_fp32_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec2_fp32_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstore_halfn(__clc_vec3_fp32_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec3_fp32_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec3_fp32_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstore_halfn(__clc_vec4_fp32_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec4_fp32_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec4_fp32_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstore_halfn(__clc_vec8_fp32_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec8_fp32_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec8_fp32_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstore_halfn(__clc_vec16_fp32_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec16_fp32_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec16_fp32_t, + __clc_size_t, + __clc_fp16_t __global *); +#endif + +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstore_halfn(__clc_vec2_fp64_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec2_fp64_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec2_fp64_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstore_halfn(__clc_vec3_fp64_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec3_fp64_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec3_fp64_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstore_halfn(__clc_vec4_fp64_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec4_fp64_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec4_fp64_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstore_halfn(__clc_vec8_fp64_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec8_fp64_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec8_fp64_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstore_halfn(__clc_vec16_fp64_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec16_fp64_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn(__clc_vec16_fp64_t, + __clc_size_t, + __clc_fp16_t __global *); +#endif +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec2_fp32_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec2_fp32_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec2_fp32_t, + __clc_size_t, + __clc_fp16_t __global *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec3_fp32_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec3_fp32_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec3_fp32_t, + __clc_size_t, + __clc_fp16_t __global *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec4_fp32_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec4_fp32_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec4_fp32_t, + __clc_size_t, + __clc_fp16_t __global *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec8_fp32_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec8_fp32_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec8_fp32_t, + __clc_size_t, + __clc_fp16_t __global *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec16_fp32_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec16_fp32_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec16_fp32_t, + __clc_size_t, + __clc_fp16_t __global *, + __clc_uint32_t); +#endif + +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec2_fp64_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec2_fp64_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec2_fp64_t, + __clc_size_t, + __clc_fp16_t __global *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec3_fp64_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec3_fp64_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec3_fp64_t, + __clc_size_t, + __clc_fp16_t __global *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec4_fp64_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec4_fp64_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec4_fp64_t, + __clc_size_t, + __clc_fp16_t __global *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec8_fp64_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec8_fp64_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec8_fp64_t, + __clc_size_t, + __clc_fp16_t __global *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec16_fp64_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec16_fp64_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstore_halfn_r(__clc_vec16_fp64_t, + __clc_size_t, + __clc_fp16_t __global *, + __clc_uint32_t); +#endif +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn(__clc_vec2_fp32_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec2_fp32_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec2_fp32_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn(__clc_vec3_fp32_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec3_fp32_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec3_fp32_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn(__clc_vec4_fp32_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec4_fp32_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec4_fp32_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn(__clc_vec8_fp32_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec8_fp32_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec8_fp32_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn(__clc_vec16_fp32_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec16_fp32_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec16_fp32_t, + __clc_size_t, + __clc_fp16_t __global *); +#endif + +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn(__clc_vec2_fp64_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec2_fp64_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec2_fp64_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn(__clc_vec3_fp64_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec3_fp64_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec3_fp64_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn(__clc_vec4_fp64_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec4_fp64_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec4_fp64_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn(__clc_vec8_fp64_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec8_fp64_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec8_fp64_t, + __clc_size_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn(__clc_vec16_fp64_t, __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec16_fp64_t, + __clc_size_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn(__clc_vec16_fp64_t, + __clc_size_t, + __clc_fp16_t __global *); +#endif +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec2_fp32_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec2_fp32_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn_r(__clc_vec2_fp32_t, __clc_size_t, + __clc_fp16_t __global *, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec3_fp32_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec3_fp32_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn_r(__clc_vec3_fp32_t, __clc_size_t, + __clc_fp16_t __global *, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec4_fp32_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec4_fp32_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn_r(__clc_vec4_fp32_t, __clc_size_t, + __clc_fp16_t __global *, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec8_fp32_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec8_fp32_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn_r(__clc_vec8_fp32_t, __clc_size_t, + __clc_fp16_t __global *, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec16_fp32_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec16_fp32_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn_r(__clc_vec16_fp32_t, __clc_size_t, + __clc_fp16_t __global *, __clc_uint32_t); +#endif + +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec2_fp64_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec2_fp64_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn_r(__clc_vec2_fp64_t, __clc_size_t, + __clc_fp16_t __global *, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec3_fp64_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec3_fp64_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn_r(__clc_vec3_fp64_t, __clc_size_t, + __clc_fp16_t __global *, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec4_fp64_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec4_fp64_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn_r(__clc_vec4_fp64_t, __clc_size_t, + __clc_fp16_t __global *, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec8_fp64_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec8_fp64_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn_r(__clc_vec8_fp64_t, __clc_size_t, + __clc_fp16_t __global *, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec16_fp64_t, + __clc_size_t, + __clc_fp16_t *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstorea_halfn_r(__clc_vec16_fp64_t, + __clc_size_t, + __clc_fp16_t __local *, + __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstorea_halfn_r(__clc_vec16_fp64_t, __clc_size_t, + __clc_fp16_t __global *, __clc_uint32_t); +#endif +#endif + +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_char_t, + __clc_size_t, __clc_char_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_char_t, __clc_size_t, __clc_char_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_char_t, __clc_size_t, __clc_char_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_char_t, + __clc_size_t, __clc_char_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_char_t, __clc_size_t, __clc_char_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_char_t, __clc_size_t, __clc_char_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_char_t, + __clc_size_t, __clc_char_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_char_t, __clc_size_t, __clc_char_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_char_t, __clc_size_t, __clc_char_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_char_t, + __clc_size_t, __clc_char_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_char_t, __clc_size_t, __clc_char_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_char_t, __clc_size_t, __clc_char_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_char_t, + __clc_size_t, __clc_char_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_char_t, __clc_size_t, __clc_char_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_char_t, __clc_size_t, __clc_char_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_int8_t, + __clc_size_t, __clc_int8_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_int8_t, __clc_size_t, __clc_int8_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_int8_t, __clc_size_t, __clc_int8_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_int8_t, + __clc_size_t, __clc_int8_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_int8_t, __clc_size_t, __clc_int8_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_int8_t, __clc_size_t, __clc_int8_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_int8_t, + __clc_size_t, __clc_int8_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_int8_t, __clc_size_t, __clc_int8_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_int8_t, __clc_size_t, __clc_int8_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_int8_t, + __clc_size_t, __clc_int8_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_int8_t, __clc_size_t, __clc_int8_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_int8_t, __clc_size_t, __clc_int8_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_int8_t, + __clc_size_t, __clc_int8_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_int8_t, __clc_size_t, __clc_int8_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_int8_t, __clc_size_t, __clc_int8_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_int16_t, + __clc_size_t, __clc_int16_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_int16_t, __clc_size_t, __clc_int16_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_int16_t, __clc_size_t, __clc_int16_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_int16_t, + __clc_size_t, __clc_int16_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_int16_t, __clc_size_t, __clc_int16_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_int16_t, __clc_size_t, __clc_int16_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_int16_t, + __clc_size_t, __clc_int16_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_int16_t, __clc_size_t, __clc_int16_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_int16_t, __clc_size_t, __clc_int16_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_int16_t, + __clc_size_t, __clc_int16_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_int16_t, __clc_size_t, __clc_int16_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_int16_t, __clc_size_t, __clc_int16_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_int16_t, + __clc_size_t, __clc_int16_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_int16_t, __clc_size_t, __clc_int16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_int16_t, + __clc_size_t, + __clc_int16_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_int32_t, + __clc_size_t, __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_int32_t, __clc_size_t, __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_int32_t, __clc_size_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_int32_t, + __clc_size_t, __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_int32_t, __clc_size_t, __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_int32_t, __clc_size_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_int32_t, + __clc_size_t, __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_int32_t, __clc_size_t, __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_int32_t, __clc_size_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_int32_t, + __clc_size_t, __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_int32_t, __clc_size_t, __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_int32_t, __clc_size_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_int32_t, + __clc_size_t, __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_int32_t, __clc_size_t, __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_int32_t, + __clc_size_t, + __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_int64_t, + __clc_size_t, __clc_int64_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_int64_t, __clc_size_t, __clc_int64_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_int64_t, __clc_size_t, __clc_int64_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_int64_t, + __clc_size_t, __clc_int64_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_int64_t, __clc_size_t, __clc_int64_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_int64_t, __clc_size_t, __clc_int64_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_int64_t, + __clc_size_t, __clc_int64_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_int64_t, __clc_size_t, __clc_int64_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_int64_t, __clc_size_t, __clc_int64_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_int64_t, + __clc_size_t, __clc_int64_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_int64_t, __clc_size_t, __clc_int64_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_int64_t, __clc_size_t, __clc_int64_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_int64_t, + __clc_size_t, __clc_int64_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_int64_t, __clc_size_t, __clc_int64_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_int64_t, + __clc_size_t, + __clc_int64_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_uint8_t, + __clc_size_t, __clc_uint8_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_uint8_t, __clc_size_t, __clc_uint8_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_uint8_t, __clc_size_t, __clc_uint8_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_uint8_t, + __clc_size_t, __clc_uint8_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_uint8_t, __clc_size_t, __clc_uint8_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_uint8_t, __clc_size_t, __clc_uint8_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_uint8_t, + __clc_size_t, __clc_uint8_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_uint8_t, __clc_size_t, __clc_uint8_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_uint8_t, __clc_size_t, __clc_uint8_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_uint8_t, + __clc_size_t, __clc_uint8_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_uint8_t, __clc_size_t, __clc_uint8_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_uint8_t, __clc_size_t, __clc_uint8_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_uint8_t, + __clc_size_t, __clc_uint8_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_uint8_t, __clc_size_t, __clc_uint8_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_uint8_t, + __clc_size_t, + __clc_uint8_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_uint16_t, __clc_size_t, __clc_uint16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_uint16_t, + __clc_size_t, + __clc_uint16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_uint16_t, + __clc_size_t, + __clc_uint16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_uint16_t, __clc_size_t, __clc_uint16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_uint16_t, + __clc_size_t, + __clc_uint16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_uint16_t, + __clc_size_t, + __clc_uint16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_uint16_t, __clc_size_t, __clc_uint16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_uint16_t, + __clc_size_t, + __clc_uint16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_uint16_t, + __clc_size_t, + __clc_uint16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_uint16_t, __clc_size_t, __clc_uint16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_uint16_t, + __clc_size_t, + __clc_uint16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_uint16_t, + __clc_size_t, + __clc_uint16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_uint16_t, __clc_size_t, __clc_uint16_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_uint16_t, + __clc_size_t, + __clc_uint16_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_uint16_t, + __clc_size_t, + __clc_uint16_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_uint32_t, __clc_size_t, __clc_uint32_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_uint32_t, + __clc_size_t, + __clc_uint32_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_uint32_t, + __clc_size_t, + __clc_uint32_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_uint32_t, __clc_size_t, __clc_uint32_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_uint32_t, + __clc_size_t, + __clc_uint32_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_uint32_t, + __clc_size_t, + __clc_uint32_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_uint32_t, __clc_size_t, __clc_uint32_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_uint32_t, + __clc_size_t, + __clc_uint32_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_uint32_t, + __clc_size_t, + __clc_uint32_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_uint32_t, __clc_size_t, __clc_uint32_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_uint32_t, + __clc_size_t, + __clc_uint32_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_uint32_t, + __clc_size_t, + __clc_uint32_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_uint32_t, __clc_size_t, __clc_uint32_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_uint32_t, + __clc_size_t, + __clc_uint32_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_uint32_t, + __clc_size_t, + __clc_uint32_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_uint64_t, __clc_size_t, __clc_uint64_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_uint64_t, + __clc_size_t, + __clc_uint64_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_uint64_t, + __clc_size_t, + __clc_uint64_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_uint64_t, __clc_size_t, __clc_uint64_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_uint64_t, + __clc_size_t, + __clc_uint64_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_uint64_t, + __clc_size_t, + __clc_uint64_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_uint64_t, __clc_size_t, __clc_uint64_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_uint64_t, + __clc_size_t, + __clc_uint64_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_uint64_t, + __clc_size_t, + __clc_uint64_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_uint64_t, __clc_size_t, __clc_uint64_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_uint64_t, + __clc_size_t, + __clc_uint64_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_uint64_t, + __clc_size_t, + __clc_uint64_t __global *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_uint64_t, __clc_size_t, __clc_uint64_t *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_uint64_t, + __clc_size_t, + __clc_uint64_t __local *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_uint64_t, + __clc_size_t, + __clc_uint64_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_fp32_t, + __clc_size_t, __clc_fp32_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_fp32_t, __clc_size_t, __clc_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_fp32_t, __clc_size_t, __clc_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_fp32_t, + __clc_size_t, __clc_fp32_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_fp32_t, __clc_size_t, __clc_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_fp32_t, __clc_size_t, __clc_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_fp32_t, + __clc_size_t, __clc_fp32_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_fp32_t, __clc_size_t, __clc_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_fp32_t, __clc_size_t, __clc_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_fp32_t, + __clc_size_t, __clc_fp32_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_fp32_t, __clc_size_t, __clc_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_fp32_t, __clc_size_t, __clc_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_fp32_t, + __clc_size_t, __clc_fp32_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_fp32_t, __clc_size_t, __clc_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_fp32_t, __clc_size_t, __clc_fp32_t __global *); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_fp64_t, + __clc_size_t, __clc_fp64_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_fp64_t, __clc_size_t, __clc_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_fp64_t, __clc_size_t, __clc_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_fp64_t, + __clc_size_t, __clc_fp64_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_fp64_t, __clc_size_t, __clc_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_fp64_t, __clc_size_t, __clc_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_fp64_t, + __clc_size_t, __clc_fp64_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_fp64_t, __clc_size_t, __clc_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_fp64_t, __clc_size_t, __clc_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_fp64_t, + __clc_size_t, __clc_fp64_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_fp64_t, __clc_size_t, __clc_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_fp64_t, __clc_size_t, __clc_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_fp64_t, + __clc_size_t, __clc_fp64_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_fp64_t, __clc_size_t, __clc_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_fp64_t, __clc_size_t, __clc_fp64_t __global *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec2_fp16_t, + __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_fp16_t, __clc_size_t, __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec2_fp16_t, __clc_size_t, __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec3_fp16_t, + __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_fp16_t, __clc_size_t, __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec3_fp16_t, __clc_size_t, __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec4_fp16_t, + __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_fp16_t, __clc_size_t, __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec4_fp16_t, __clc_size_t, __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec8_fp16_t, + __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_fp16_t, __clc_size_t, __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec8_fp16_t, __clc_size_t, __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL void __spirv_ocl_vstoren(__clc_vec16_fp16_t, + __clc_size_t, __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_fp16_t, __clc_size_t, __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL void +__spirv_ocl_vstoren(__clc_vec16_fp16_t, __clc_size_t, __clc_fp16_t __global *); +#endif + #endif diff --git a/libclc/generic/lib/async/prefetch.cl b/libclc/generic/lib/async/prefetch.cl index 0d982c0258fd6..be5df106ac4d5 100644 --- a/libclc/generic/lib/async/prefetch.cl +++ b/libclc/generic/lib/async/prefetch.cl @@ -1,3 +1,11 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + #include #include diff --git a/libclc/generic/lib/async/prefetch.inc b/libclc/generic/lib/async/prefetch.inc index 576bdc6ef1a93..b8f17eecdb768 100644 --- a/libclc/generic/lib/async/prefetch.inc +++ b/libclc/generic/lib/async/prefetch.inc @@ -1,3 +1,4 @@ -_CLC_OVERLOAD _CLC_DEF void prefetch(const global __CLC_GENTYPE *p, size_t num_gentypes) { - return __spirv_ocl_prefetch(p, num_gentypes); +_CLC_OVERLOAD _CLC_DEF void prefetch(const global __CLC_GENTYPE *p, + size_t num_gentypes) { + __spirv_ocl_prefetch(p, num_gentypes); } diff --git a/libclc/generic/libspirv/SOURCES b/libclc/generic/libspirv/SOURCES index 42efb20178e6f..7189035ae092d 100644 --- a/libclc/generic/libspirv/SOURCES +++ b/libclc/generic/libspirv/SOURCES @@ -39,12 +39,15 @@ integer/abs.cl integer/abs_diff.cl integer/add_sat.cl integer/clz.cl +integer/ctz.cl integer/hadd.cl integer/mad24.cl +integer/mad_hi.cl integer/mad_sat.cl integer/mul24.cl integer/mul_hi.cl integer/popcount.cl +integer/BitCount.cl integer/rhadd.cl integer/rotate.cl integer/sub_sat.cl @@ -106,5 +109,7 @@ relational/isnan.cl shared/clamp.cl shared/max.cl shared/min.cl +shared/vload.cl +shared/vstore.cl workitem/get_global_id.cl workitem/get_global_size.cl diff --git a/libclc/generic/libspirv/core/integer/clc_rhadd.inc b/libclc/generic/libspirv/core/integer/clc_rhadd.inc index d8de33aa35a8a..3d55b408b6363 100644 --- a/libclc/generic/libspirv/core/integer/clc_rhadd.inc +++ b/libclc/generic/libspirv/core/integer/clc_rhadd.inc @@ -9,8 +9,8 @@ // rhadd = (x+y+1)>>1 // This can be simplified to x>>1 + y>>1 + (1 if either x or y have the 1s bit // set) This saves us having to do any checks for overflow in the addition sums -_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __clc__rhadd(__CLC_GENTYPE x, - __CLC_GENTYPE y) { +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __clc_rhadd(__CLC_GENTYPE x, + __CLC_GENTYPE y) { return (x >> (__CLC_GENTYPE)1) + (y >> (__CLC_GENTYPE)1) + ((x & (__CLC_GENTYPE)1) | (y & (__CLC_GENTYPE)1)); } diff --git a/libclc/generic/include/spirv/integer/clz.inc b/libclc/generic/libspirv/integer/BitCount.cl similarity index 66% rename from libclc/generic/include/spirv/integer/clz.inc rename to libclc/generic/libspirv/integer/BitCount.cl index af7d93303093c..721801a549bca 100644 --- a/libclc/generic/include/spirv/integer/clz.inc +++ b/libclc/generic/libspirv/integer/BitCount.cl @@ -6,4 +6,10 @@ // //===----------------------------------------------------------------------===// -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_clz(__SPIRV_GENTYPE x); +#include + +#define __CLC_FUNC __spirv_BitCount +#define __CLC_IMPL_FUNC __spirv_ocl_popcount + +#define __CLC_BODY "../../lib/clc_unary.inc" +#include diff --git a/libclc/generic/libspirv/integer/ctz.cl b/libclc/generic/libspirv/integer/ctz.cl new file mode 100644 index 0000000000000..43e6879c04867 --- /dev/null +++ b/libclc/generic/libspirv/integer/ctz.cl @@ -0,0 +1,56 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +_CLC_OVERLOAD _CLC_DEF short __spirv_ocl_ctz(short x) { + return x ? __builtin_ctzs(x) : 16; +} + +_CLC_OVERLOAD _CLC_DEF ushort __spirv_ocl_ctz(ushort x) { + return x ? __builtin_ctzs(x) : 16; +} + +_CLC_OVERLOAD _CLC_DEF int __spirv_ocl_ctz(int x) { + return x ? __builtin_ctz(x) : 32; +} + +_CLC_OVERLOAD _CLC_DEF uint __spirv_ocl_ctz(uint x) { + return x ? __builtin_ctz(x) : 32; +} + +_CLC_OVERLOAD _CLC_DEF long __spirv_ocl_ctz(long x) { + return x ? __builtin_ctzl(x) : 64; +} + +_CLC_OVERLOAD _CLC_DEF ulong __spirv_ocl_ctz(ulong x) { + return x ? __builtin_ctzl(x) : 64; +} + +_CLC_OVERLOAD _CLC_DEF char __spirv_ocl_ctz(char x) { + return __spirv_ocl_ctz((ushort)(uchar)x) - 8; +} + +_CLC_OVERLOAD _CLC_DEF schar __spirv_ocl_ctz(schar x) { + return __spirv_ocl_ctz((ushort)(uchar)x) - 8; +} + +_CLC_OVERLOAD _CLC_DEF uchar __spirv_ocl_ctz(uchar x) { + return __spirv_ocl_ctz((ushort)x) - 8; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, char, __spirv_ocl_ctz, char) +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, schar, __spirv_ocl_ctz, schar) +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, uchar, __spirv_ocl_ctz, uchar) +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, short, __spirv_ocl_ctz, short) +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, ushort, __spirv_ocl_ctz, ushort) +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, int, __spirv_ocl_ctz, int) +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, uint, __spirv_ocl_ctz, uint) +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, long, __spirv_ocl_ctz, long) +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, ulong, __spirv_ocl_ctz, ulong) diff --git a/libclc/generic/include/spirv/integer/clz.h b/libclc/generic/libspirv/integer/mad_hi.cl similarity index 75% rename from libclc/generic/include/spirv/integer/clz.h rename to libclc/generic/libspirv/integer/mad_hi.cl index e281f64da94fe..1aa486b59fd64 100644 --- a/libclc/generic/include/spirv/integer/clz.h +++ b/libclc/generic/libspirv/integer/mad_hi.cl @@ -6,5 +6,8 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_BODY -#include +#include +#include + +#define __CLC_BODY +#include diff --git a/libclc/generic/include/spirv/integer/popcount.h b/libclc/generic/libspirv/integer/mad_hi.inc similarity index 52% rename from libclc/generic/include/spirv/integer/popcount.h rename to libclc/generic/libspirv/integer/mad_hi.inc index 52e4bbf395309..45d75a064259a 100644 --- a/libclc/generic/include/spirv/integer/popcount.h +++ b/libclc/generic/libspirv/integer/mad_hi.inc @@ -6,8 +6,17 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_FUNCTION __spirv_ocl_popcount -#define __SPIRV_BODY -#include -#undef __SPIRV_FUNCTION -#undef __SPIRV_BODY +#ifdef __CLC_GEN_S +#define DECL __spirv_ocl_s_mad_hi +#else +#define DECL __spirv_ocl_u_mad_hi +#endif + +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE DECL(__CLC_GENTYPE x, __CLC_GENTYPE y, + __CLC_GENTYPE z) { + return __clc_mad_hi(x, y, z); +} + +#undef DECL +#undef __CLC_AS_SPIRV +#undef __CLC_AS_INTERFACE diff --git a/libclc/generic/libspirv/shared/vload.cl b/libclc/generic/libspirv/shared/vload.cl new file mode 100644 index 0000000000000..54beef922055c --- /dev/null +++ b/libclc/generic/libspirv/shared/vload.cl @@ -0,0 +1,172 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define VLOAD_VECTORIZE(RTYPE, PRIM_TYPE, ADDR_SPACE) \ + typedef PRIM_TYPE less_aligned_##ADDR_SPACE##PRIM_TYPE \ + __attribute__((aligned(sizeof(PRIM_TYPE)))); \ + _CLC_OVERLOAD _CLC_DEF PRIM_TYPE __spirv_ocl_vload_R##RTYPE( \ + size_t offset, const ADDR_SPACE PRIM_TYPE *x) { \ + return *(( \ + const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE *)(&x[offset])); \ + } \ + \ + typedef PRIM_TYPE##2 less_aligned_##ADDR_SPACE##PRIM_TYPE##2 \ + __attribute__((aligned(sizeof(PRIM_TYPE)))); \ + _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##2 __spirv_ocl_vloadn_R##RTYPE##2( \ + size_t offset, const ADDR_SPACE PRIM_TYPE *x) { \ + return *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##2 \ + *)(&x[2 * offset])); \ + } \ + \ + typedef PRIM_TYPE##3 less_aligned_##ADDR_SPACE##PRIM_TYPE##3 \ + __attribute__((aligned(sizeof(PRIM_TYPE)))); \ + _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##3 __spirv_ocl_vloadn_R##RTYPE##3( \ + size_t offset, const ADDR_SPACE PRIM_TYPE *x) { \ + PRIM_TYPE##2 vec = \ + *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##2 \ + *)(&x[3 * offset])); \ + return (PRIM_TYPE##3)(vec.s0, vec.s1, x[offset * 3 + 2]); \ + } \ + \ + typedef PRIM_TYPE##4 less_aligned_##ADDR_SPACE##PRIM_TYPE##4 \ + __attribute__((aligned(sizeof(PRIM_TYPE)))); \ + _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##4 __spirv_ocl_vloadn_R##RTYPE##4( \ + size_t offset, const ADDR_SPACE PRIM_TYPE *x) { \ + return *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##4 \ + *)(&x[4 * offset])); \ + } \ + \ + typedef PRIM_TYPE##8 less_aligned_##ADDR_SPACE##PRIM_TYPE##8 \ + __attribute__((aligned(sizeof(PRIM_TYPE)))); \ + _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##8 __spirv_ocl_vloadn_R##RTYPE##8( \ + size_t offset, const ADDR_SPACE PRIM_TYPE *x) { \ + return *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##8 \ + *)(&x[8 * offset])); \ + } \ + \ + typedef PRIM_TYPE##16 less_aligned_##ADDR_SPACE##PRIM_TYPE##16 \ + __attribute__((aligned(sizeof(PRIM_TYPE)))); \ + _CLC_OVERLOAD _CLC_DEF PRIM_TYPE##16 __spirv_ocl_vloadn_R##RTYPE##16( \ + size_t offset, const ADDR_SPACE PRIM_TYPE *x) { \ + return *((const ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##16 \ + *)(&x[16 * offset])); \ + } + +#define VLOAD_ADDR_SPACES_IMPL(__CLC_RET_GENTYPE, __CLC_SCALAR_GENTYPE) \ + VLOAD_VECTORIZE(__CLC_RET_GENTYPE, __CLC_SCALAR_GENTYPE, __private) \ + VLOAD_VECTORIZE(__CLC_RET_GENTYPE, __CLC_SCALAR_GENTYPE, __local) \ + VLOAD_VECTORIZE(__CLC_RET_GENTYPE, __CLC_SCALAR_GENTYPE, __constant) \ + VLOAD_VECTORIZE(__CLC_RET_GENTYPE, __CLC_SCALAR_GENTYPE, __global) + +#define VLOAD_ADDR_SPACES(__CLC_SCALAR_GENTYPE) \ + VLOAD_ADDR_SPACES_IMPL(__CLC_SCALAR_GENTYPE, __CLC_SCALAR_GENTYPE) + +VLOAD_ADDR_SPACES_IMPL(char, schar) + +#define VLOAD_TYPES() \ + VLOAD_ADDR_SPACES(uchar) \ + VLOAD_ADDR_SPACES(short) \ + VLOAD_ADDR_SPACES(ushort) \ + VLOAD_ADDR_SPACES(int) \ + VLOAD_ADDR_SPACES(uint) \ + VLOAD_ADDR_SPACES(long) \ + VLOAD_ADDR_SPACES(ulong) \ + VLOAD_ADDR_SPACES(float) + +VLOAD_TYPES() + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable +VLOAD_ADDR_SPACES(double) +#endif +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +VLOAD_ADDR_SPACES(half) +#endif + +/* vload_half are legal even without cl_khr_fp16 */ +/* no vload_half for double */ +#if __clang_major__ < 6 +float __clc_vload_half_float_helper__constant(const __constant half *); +float __clc_vload_half_float_helper__global(const __global half *); +float __clc_vload_half_float_helper__local(const __local half *); +float __clc_vload_half_float_helper__private(const __private half *); + +#define VEC_LOAD1(val, AS) \ + val = __clc_vload_half_float_helper##AS(&mem[offset++]); +#else +#define VEC_LOAD1(val, AS) val = __builtin_load_halff(&mem[offset++]); +#endif + +#define VEC_LOAD2(val, AS) \ + VEC_LOAD1(val.lo, AS) \ + VEC_LOAD1(val.hi, AS) +#define VEC_LOAD3(val, AS) \ + VEC_LOAD1(val.s0, AS) \ + VEC_LOAD1(val.s1, AS) \ + VEC_LOAD1(val.s2, AS) +#define VEC_LOAD4(val, AS) \ + VEC_LOAD2(val.lo, AS) \ + VEC_LOAD2(val.hi, AS) +#define VEC_LOAD8(val, AS) \ + VEC_LOAD4(val.lo, AS) \ + VEC_LOAD4(val.hi, AS) +#define VEC_LOAD16(val, AS) \ + VEC_LOAD8(val.lo, AS) \ + VEC_LOAD8(val.hi, AS) + +#define VLOAD_HALF_VEC_IMPL(VEC_SIZE, OFFSET_SIZE, AS) \ + _CLC_OVERLOAD _CLC_DEF float##VEC_SIZE \ + __spirv_ocl_vload_halfn_Rfloat##VEC_SIZE(size_t offset, \ + const AS half *mem) { \ + offset *= VEC_SIZE; \ + float##VEC_SIZE __tmp; \ + VEC_LOAD##VEC_SIZE(__tmp, AS) return __tmp; \ + } \ + _CLC_OVERLOAD _CLC_DEF float##VEC_SIZE \ + __spirv_ocl_vloada_halfn_Rfloat##VEC_SIZE(size_t offset, \ + const AS half *mem) { \ + offset *= OFFSET_SIZE; \ + float##VEC_SIZE __tmp; \ + VEC_LOAD##VEC_SIZE(__tmp, AS) return __tmp; \ + } + +#define VLOAD_HALF_IMPL(AS) \ + _CLC_OVERLOAD _CLC_DEF float __spirv_ocl_vload_half(size_t offset, \ + const AS half *mem) { \ + float __tmp; \ + VEC_LOAD1(__tmp, AS) return __tmp; \ + } + +#define GEN_VLOAD_HALF(AS) \ + VLOAD_HALF_IMPL(AS) \ + VLOAD_HALF_VEC_IMPL(2, 2, AS) \ + VLOAD_HALF_VEC_IMPL(3, 4, AS) \ + VLOAD_HALF_VEC_IMPL(4, 4, AS) \ + VLOAD_HALF_VEC_IMPL(8, 8, AS) \ + VLOAD_HALF_VEC_IMPL(16, 16, AS) + +GEN_VLOAD_HALF(__private) +GEN_VLOAD_HALF(__global) +GEN_VLOAD_HALF(__local) +GEN_VLOAD_HALF(__constant) + +#undef VLOAD_HALF_IMPL +#undef VLOAD_HALF_VEC_IMPL +#undef GEN_VLOAD_HALF +#undef VEC_LOAD16 +#undef VEC_LOAD8 +#undef VEC_LOAD4 +#undef VEC_LOAD3 +#undef VEC_LOAD2 +#undef VEC_LOAD1 +#undef VLOAD_TYPES +#undef VLOAD_ADDR_SPACES +#undef VLOAD_VECTORIZE diff --git a/libclc/generic/libspirv/shared/vstore.cl b/libclc/generic/libspirv/shared/vstore.cl new file mode 100644 index 0000000000000..18363d1594844 --- /dev/null +++ b/libclc/generic/libspirv/shared/vstore.cl @@ -0,0 +1,311 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#pragma OPENCL EXTENSION cl_khr_byte_addressable_store : enable + +#define VSTORE_VECTORIZE(PRIM_TYPE, ADDR_SPACE) \ + typedef PRIM_TYPE less_aligned_##ADDR_SPACE##PRIM_TYPE \ + __attribute__((aligned(sizeof(PRIM_TYPE)))); \ + _CLC_OVERLOAD _CLC_DEF void __spirv_ocl_vstore(PRIM_TYPE vec, size_t offset, \ + ADDR_SPACE PRIM_TYPE *mem) { \ + *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE *)(&mem[offset])) = \ + vec; \ + } \ + \ + typedef PRIM_TYPE##2 less_aligned_##ADDR_SPACE##PRIM_TYPE##2 \ + __attribute__((aligned(sizeof(PRIM_TYPE)))); \ + _CLC_OVERLOAD _CLC_DEF void __spirv_ocl_vstoren( \ + PRIM_TYPE##2 vec, size_t offset, ADDR_SPACE PRIM_TYPE *mem) { \ + *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##2 \ + *)(&mem[2 * offset])) = vec; \ + } \ + \ + _CLC_OVERLOAD _CLC_DEF void __spirv_ocl_vstoren( \ + PRIM_TYPE##3 vec, size_t offset, ADDR_SPACE PRIM_TYPE *mem) { \ + *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##2 \ + *)(&mem[3 * offset])) = (PRIM_TYPE##2)(vec.s0, vec.s1); \ + mem[3 * offset + 2] = vec.s2; \ + } \ + \ + typedef PRIM_TYPE##4 less_aligned_##ADDR_SPACE##PRIM_TYPE##4 \ + __attribute__((aligned(sizeof(PRIM_TYPE)))); \ + _CLC_OVERLOAD _CLC_DEF void __spirv_ocl_vstoren( \ + PRIM_TYPE##4 vec, size_t offset, ADDR_SPACE PRIM_TYPE *mem) { \ + *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##4 \ + *)(&mem[4 * offset])) = vec; \ + } \ + \ + typedef PRIM_TYPE##8 less_aligned_##ADDR_SPACE##PRIM_TYPE##8 \ + __attribute__((aligned(sizeof(PRIM_TYPE)))); \ + _CLC_OVERLOAD _CLC_DEF void __spirv_ocl_vstoren( \ + PRIM_TYPE##8 vec, size_t offset, ADDR_SPACE PRIM_TYPE *mem) { \ + *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##8 \ + *)(&mem[8 * offset])) = vec; \ + } \ + \ + typedef PRIM_TYPE##16 less_aligned_##ADDR_SPACE##PRIM_TYPE##16 \ + __attribute__((aligned(sizeof(PRIM_TYPE)))); \ + _CLC_OVERLOAD _CLC_DEF void __spirv_ocl_vstoren( \ + PRIM_TYPE##16 vec, size_t offset, ADDR_SPACE PRIM_TYPE *mem) { \ + *((ADDR_SPACE less_aligned_##ADDR_SPACE##PRIM_TYPE##16 \ + *)(&mem[16 * offset])) = vec; \ + } + +#define VSTORE_ADDR_SPACES(__CLC_SCALAR___CLC_GENTYPE) \ + VSTORE_VECTORIZE(__CLC_SCALAR___CLC_GENTYPE, __private) \ + VSTORE_VECTORIZE(__CLC_SCALAR___CLC_GENTYPE, __local) \ + VSTORE_VECTORIZE(__CLC_SCALAR___CLC_GENTYPE, __global) + +VSTORE_ADDR_SPACES(schar) +VSTORE_ADDR_SPACES(uchar) +VSTORE_ADDR_SPACES(short) +VSTORE_ADDR_SPACES(ushort) +VSTORE_ADDR_SPACES(int) +VSTORE_ADDR_SPACES(uint) +VSTORE_ADDR_SPACES(long) +VSTORE_ADDR_SPACES(ulong) +VSTORE_ADDR_SPACES(float) + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable +VSTORE_ADDR_SPACES(double) +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable +VSTORE_ADDR_SPACES(half) +#endif + +/* vstore_half are legal even without cl_khr_fp16 */ +#if __clang_major__ < 6 +#define DECLARE_HELPER(STYPE, AS, builtin) \ + void __clc_vstore_half_##STYPE##_helper##AS(STYPE, AS half *); +#else +#define DECLARE_HELPER(STYPE, AS, __builtin) \ + _CLC_DEF void __clc_vstore_half_##STYPE##_helper##AS(STYPE s, AS half *d) { \ + __builtin(s, d); \ + } +#endif + +DECLARE_HELPER(float, __private, __builtin_store_halff); +DECLARE_HELPER(float, __global, __builtin_store_halff); +DECLARE_HELPER(float, __local, __builtin_store_halff); + +#ifdef cl_khr_fp64 +DECLARE_HELPER(double, __private, __builtin_store_half); +DECLARE_HELPER(double, __global, __builtin_store_half); +DECLARE_HELPER(double, __local, __builtin_store_half); +#endif + +#define VEC_STORE1(STYPE, AS, val, ROUNDF) \ + __clc_vstore_half_##STYPE##_helper##AS(ROUNDF(val), &mem[offset++]); + +#define VEC_STORE2(STYPE, AS, val, ROUNDF) \ + VEC_STORE1(STYPE, AS, val.lo, ROUNDF) \ + VEC_STORE1(STYPE, AS, val.hi, ROUNDF) +#define VEC_STORE3(STYPE, AS, val, ROUNDF) \ + VEC_STORE1(STYPE, AS, val.s0, ROUNDF) \ + VEC_STORE1(STYPE, AS, val.s1, ROUNDF) \ + VEC_STORE1(STYPE, AS, val.s2, ROUNDF) +#define VEC_STORE4(STYPE, AS, val, ROUNDF) \ + VEC_STORE2(STYPE, AS, val.lo, ROUNDF) \ + VEC_STORE2(STYPE, AS, val.hi, ROUNDF) +#define VEC_STORE8(STYPE, AS, val, ROUNDF) \ + VEC_STORE4(STYPE, AS, val.lo, ROUNDF) \ + VEC_STORE4(STYPE, AS, val.hi, ROUNDF) +#define VEC_STORE16(STYPE, AS, val, ROUNDF) \ + VEC_STORE8(STYPE, AS, val.lo, ROUNDF) \ + VEC_STORE8(STYPE, AS, val.hi, ROUNDF) + +#define __FUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, STYPE, AS, VEC_SUFFIX) \ + _CLC_OVERLOAD _CLC_DEF void __spirv_ocl_vstore_half##VEC_SUFFIX( \ + TYPE vec, size_t offset, AS half *mem) { \ + offset *= VEC_SIZE; \ + VEC_STORE##VEC_SIZE(STYPE, AS, vec, __clc_noop) \ + } \ + _CLC_OVERLOAD _CLC_DEF void __spirv_ocl_vstorea_half##VEC_SUFFIX( \ + TYPE vec, size_t offset, AS half *mem) { \ + offset *= OFFSET; \ + VEC_STORE##VEC_SIZE(STYPE, AS, vec, __clc_noop) \ + } + +#define __FUNC_ROUND_CASE(CASE, VEC_SIZE, STYPE, AS, ROUNDF) \ + case CASE: \ + VEC_STORE##VEC_SIZE(STYPE, AS, vec, ROUNDF) break; + +#define __FUNC_ROUND(SUFFIX, VEC_SIZE, OFFSET, TYPE, STYPE, AS, VEC_SUFFIX) \ + _CLC_OVERLOAD _CLC_DEF void __spirv_ocl_vstore_half##VEC_SUFFIX##_r( \ + TYPE vec, size_t offset, AS half *mem, unsigned int round_mode) { \ + offset *= VEC_SIZE; \ + switch (round_mode) { \ + __FUNC_ROUND_CASE(SPV_RTE, VEC_SIZE, STYPE, AS, __clc_rte) \ + __FUNC_ROUND_CASE(SPV_RTZ, VEC_SIZE, STYPE, AS, __clc_rtz) \ + __FUNC_ROUND_CASE(SPV_RTP, VEC_SIZE, STYPE, AS, __clc_rtp) \ + __FUNC_ROUND_CASE(SPV_RTN, VEC_SIZE, STYPE, AS, __clc_rtn) \ + default: \ + break; \ + } \ + } \ + _CLC_OVERLOAD _CLC_DEF void __spirv_ocl_vstorea_half##VEC_SUFFIX##_r( \ + TYPE vec, size_t offset, AS half *mem, unsigned int round_mode) { \ + offset *= OFFSET; \ + switch (round_mode) { \ + __FUNC_ROUND_CASE(SPV_RTE, VEC_SIZE, STYPE, AS, __clc_rte) \ + __FUNC_ROUND_CASE(SPV_RTZ, VEC_SIZE, STYPE, AS, __clc_rtz) \ + __FUNC_ROUND_CASE(SPV_RTP, VEC_SIZE, STYPE, AS, __clc_rtp) \ + __FUNC_ROUND_CASE(SPV_RTN, VEC_SIZE, STYPE, AS, __clc_rtn) \ + default: \ + break; \ + } \ + } + +_CLC_DEF _CLC_OVERLOAD float __clc_noop(float x) { return x; } +_CLC_DEF _CLC_OVERLOAD float __clc_rtz(float x) { + /* Remove lower 13 bits to make sure the number is rounded down */ + int mask = 0xffffe000; + const int exp = (as_uint(x) >> 23 & 0xff) - 127; + /* Denormals cannot be flushed, and they use different bit for rounding */ + if (exp < -14) + mask <<= __spirv_ocl_s_min(-(exp + 14), 10); + /* RTZ does not produce Inf for large numbers */ + if (__spirv_ocl_fabs(x) > 65504.0f && !__spirv_IsInf(x)) + return __spirv_ocl_copysign(65504.0f, x); + /* Handle nan corner case */ + if (__spirv_IsNan(x)) + return x; + return as_float(as_uint(x) & mask); +} +_CLC_DEF _CLC_OVERLOAD float __clc_rti(float x) { + const float inf = __spirv_ocl_copysign(INFINITY, x); + /* Set lower 13 bits */ + int mask = (1 << 13) - 1; + const int exp = (as_uint(x) >> 23 & 0xff) - 127; + /* Denormals cannot be flushed, and they use different bit for rounding */ + if (exp < -14) + mask = (1 << (13 + __spirv_ocl_s_min(-(exp + 14), 10))) - 1; + /* Handle nan corner case */ + if (__spirv_IsNan(x)) + return x; + const float next = __spirv_ocl_nextafter(as_float(as_uint(x) | mask), inf); + return ((as_uint(x) & mask) == 0) ? x : next; +} +_CLC_DEF _CLC_OVERLOAD float __clc_rtn(float x) { + return ((as_uint(x) & 0x80000000) == 0) ? __clc_rtz(x) : __clc_rti(x); +} +_CLC_DEF _CLC_OVERLOAD float __clc_rtp(float x) { + return ((as_uint(x) & 0x80000000) == 0) ? __clc_rti(x) : __clc_rtz(x); +} +_CLC_DEF _CLC_OVERLOAD float __clc_rte(float x) { + /* Mantisa + implicit bit */ + const uint mantissa = (as_uint(x) & 0x7fffff) | (1u << 23); + const int exp = (as_uint(x) >> 23 & 0xff) - 127; + int shift = 13; + if (exp < -14) { + /* The default assumes lower 13 bits are rounded, + * but it might be more for denormals. + * Shifting beyond last == 0b, and qr == 00b is not necessary */ + shift += __spirv_ocl_s_min(-(exp + 14), 15); + } + int mask = (1 << shift) - 1; + const uint grs = mantissa & mask; + const uint last = mantissa & (1 << shift); + /* IEEE round up rule is: grs > 101b or grs == 100b and last == 1. + * exp > 15 should round to inf. */ + bool roundup = (grs > (1 << (shift - 1))) || + (grs == (1 << (shift - 1)) && last != 0) || (exp > 15); + return roundup ? __clc_rti(x) : __clc_rtz(x); +} + +#ifdef cl_khr_fp64 +_CLC_DEF _CLC_OVERLOAD double __clc_noop(double x) { return x; } +_CLC_DEF _CLC_OVERLOAD double __clc_rtz(double x) { + /* Remove lower 42 bits to make sure the number is rounded down */ + ulong mask = 0xfffffc0000000000UL; + const int exp = (as_ulong(x) >> 52 & 0x7ff) - 1023; + /* Denormals cannot be flushed, and they use different bit for rounding */ + if (exp < -14) + mask <<= __spirv_ocl_s_min(-(exp + 14), 10); + /* RTZ does not produce Inf for large numbers */ + if (__spirv_ocl_fabs(x) > 65504.0 && !__spirv_IsInf(x)) + return __spirv_ocl_copysign(65504.0, x); + /* Handle nan corner case */ + if (__spirv_IsNan(x)) + return x; + return as_double(as_ulong(x) & mask); +} +_CLC_DEF _CLC_OVERLOAD double __clc_rti(double x) { + const double inf = __spirv_ocl_copysign((double)INFINITY, x); + /* Set lower 42 bits */ + long mask = (1UL << 42UL) - 1UL; + const int exp = (as_ulong(x) >> 52 & 0x7ff) - 1023; + /* Denormals cannot be flushed, and they use different bit for rounding */ + if (exp < -14) + mask = (1UL << (42UL + __spirv_ocl_s_min(-(exp + 14), 10))) - 1; + /* Handle nan corner case */ + if (__spirv_IsNan(x)) + return x; + const double next = __spirv_ocl_nextafter(as_double(as_ulong(x) | mask), inf); + return ((as_ulong(x) & mask) == 0) ? x : next; +} +_CLC_DEF _CLC_OVERLOAD double __clc_rtn(double x) { + return ((as_ulong(x) & 0x8000000000000000UL) == 0) ? __clc_rtz(x) + : __clc_rti(x); +} +_CLC_DEF _CLC_OVERLOAD double __clc_rtp(double x) { + return ((as_ulong(x) & 0x8000000000000000UL) == 0) ? __clc_rti(x) + : __clc_rtz(x); +} +_CLC_DEF _CLC_OVERLOAD double __clc_rte(double x) { + /* Mantisa + implicit bit */ + const ulong mantissa = (as_ulong(x) & 0xfffffffffffff) | (1UL << 52); + const int exp = (as_ulong(x) >> 52 & 0x7ff) - 1023; + int shift = 42; + if (exp < -14) { + /* The default assumes lower 13 bits are rounded, + * but it might be more for denormals. + * Shifting beyond last == 0b, and qr == 00b is not necessary */ + shift += __spirv_ocl_s_min(-(exp + 14), 15); + } + ulong mask = (1UL << shift) - 1UL; + const ulong grs = mantissa & mask; + const ulong last = mantissa & (1UL << shift); + /* IEEE round up rule is: grs > 101b or grs == 100b and last == 1. + * exp > 15 should round to inf. */ + bool roundup = (grs > (1UL << (shift - 1UL))) || + (grs == (1UL << (shift - 1UL)) && last != 0) || (exp > 15); + return roundup ? __clc_rti(x) : __clc_rtz(x); +} +#endif + +#define __XFUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, STYPE, AS, VEC_SUFFIX) \ + __FUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, STYPE, AS, VEC_SUFFIX) \ + __FUNC_ROUND(SUFFIX, VEC_SIZE, OFFSET, TYPE, STYPE, AS, VEC_SUFFIX) + +#define FUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, STYPE, AS, VEC_SUFFIX) \ + __XFUNC(SUFFIX, VEC_SIZE, OFFSET, TYPE, STYPE, AS, VEC_SUFFIX) + +#define FUNC_SCALAR(VEC_SIZE, OFFSET, TYPE, STYPE, AS) \ + __XFUNC(, VEC_SIZE, OFFSET, TYPE, STYPE, AS, ) + +#define __CLC_BODY "vstore_half.inc" +#include +#undef __CLC_BODY +#undef FUNC +#undef __XFUNC +#undef __FUNC +#undef VEC_LOAD16 +#undef VEC_LOAD8 +#undef VEC_LOAD4 +#undef VEC_LOAD3 +#undef VEC_LOAD2 +#undef VEC_LOAD1 +#undef DECLARE_HELPER +#undef VSTORE_ADDR_SPACES +#undef VSTORE_VECTORIZE diff --git a/libclc/generic/libspirv/shared/vstore_half.inc b/libclc/generic/libspirv/shared/vstore_half.inc new file mode 100644 index 0000000000000..e04d948490d6f --- /dev/null +++ b/libclc/generic/libspirv/shared/vstore_half.inc @@ -0,0 +1,32 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// This does not exist for fp16 +#if __CLC_FPSIZE > 16 +#ifdef __CLC_VECSIZE + +#if __CLC_VECSIZE == 3 +#define __CLC_OFFSET 4 +#else +#define __CLC_OFFSET __CLC_VECSIZE +#endif + +FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, + __CLC_SCALAR_GENTYPE, __private, n); +FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, + __CLC_SCALAR_GENTYPE, __local, n); +FUNC(__CLC_VECSIZE, __CLC_VECSIZE, __CLC_OFFSET, __CLC_GENTYPE, + __CLC_SCALAR_GENTYPE, __global, n); + +#undef __CLC_OFFSET +#else +FUNC_SCALAR(1, 1, __CLC_GENTYPE, __CLC_SCALAR_GENTYPE, __private); +FUNC_SCALAR(1, 1, __CLC_GENTYPE, __CLC_SCALAR_GENTYPE, __local); +FUNC_SCALAR(1, 1, __CLC_GENTYPE, __CLC_SCALAR_GENTYPE, __global); +#endif +#endif diff --git a/libclc/generic/include/spirv/integer/rotate.h b/libclc/ptx-nvidiacl/include/intrinsics.h similarity index 56% rename from libclc/generic/include/spirv/integer/rotate.h rename to libclc/ptx-nvidiacl/include/intrinsics.h index 2c24dbbc18fb0..0962545cc6266 100644 --- a/libclc/generic/include/spirv/integer/rotate.h +++ b/libclc/ptx-nvidiacl/include/intrinsics.h @@ -6,5 +6,11 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_BODY -#include +#ifndef PTX_NVIDIACL_INTRINSICS_H +#define PTX_NVIDIACL_INTRINSICS_H + +_CLC_OVERLOAD long __clc_nvvm_mulhi(long x, long y) __asm("llvm.nvvm.mulhi.ll"); +_CLC_OVERLOAD ulong __clc_nvvm_mulhi(ulong x, + ulong y) __asm("llvm.nvvm.mulhi.ull"); + +#endif diff --git a/libclc/ptx-nvidiacl/libspirv/SOURCES b/libclc/ptx-nvidiacl/libspirv/SOURCES index 50ca72e840149..c2eb77ee32b03 100644 --- a/libclc/ptx-nvidiacl/libspirv/SOURCES +++ b/libclc/ptx-nvidiacl/libspirv/SOURCES @@ -1,5 +1,7 @@ atomic/loadstore_helpers.ll cl_khr_int64_extended_atomics/minmax_helpers.ll +integer/mul24.cl +integer/mul_hi.cl synchronization/barrier.cl workitem/get_global_id.cl workitem/get_global_offset.cl diff --git a/libclc/ptx-nvidiacl/libspirv/integer/mul24.cl b/libclc/ptx-nvidiacl/libspirv/integer/mul24.cl new file mode 100644 index 0000000000000..3cda2d7ab23bf --- /dev/null +++ b/libclc/ptx-nvidiacl/libspirv/integer/mul24.cl @@ -0,0 +1,24 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include +#include + +_CLC_OVERLOAD _CLC_DEF int __spirv_ocl_s_mul24(int x, int y) { + return __nvvm_mul24_i(x, y); +} + +_CLC_OVERLOAD _CLC_DEF uint __spirv_ocl_u_mul24(uint x, uint y) { + return __nvvm_mul24_ui(x, y); +} + +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, int, __spirv_ocl_s_mul24, int, + int) +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, uint, __spirv_ocl_u_mul24, uint, + uint) diff --git a/libclc/ptx-nvidiacl/libspirv/integer/mul_hi.cl b/libclc/ptx-nvidiacl/libspirv/integer/mul_hi.cl new file mode 100644 index 0000000000000..e68f5c715a969 --- /dev/null +++ b/libclc/ptx-nvidiacl/libspirv/integer/mul_hi.cl @@ -0,0 +1,59 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include +#include + +#include "../../include/intrinsics.h" + +_CLC_OVERLOAD _CLC_DEF int __spirv_ocl_s_mul_hi(int x, int y) { + return __nvvm_mulhi_i(x, y); +} + +_CLC_OVERLOAD _CLC_DEF uint __spirv_ocl_u_mul_hi(uint x, uint y) { + return __nvvm_mulhi_ui(x, y); +} + +_CLC_OVERLOAD _CLC_DEF long __spirv_ocl_s_mul_hi(long x, long y) { + return __clc_nvvm_mulhi(x, y); +} + +_CLC_OVERLOAD _CLC_DEF ulong __spirv_ocl_u_mul_hi(ulong x, ulong y) { + return __clc_nvvm_mulhi(x, y); +} + +#define __CLC_MUL_HI_IMPL(BGENTYPE, SPV_MUL_HI, GENTYPE, GENSIZE) \ + _CLC_OVERLOAD _CLC_DEF GENTYPE SPV_MUL_HI(GENTYPE x, GENTYPE y) { \ + return (GENTYPE)(SPV_MUL_HI((BGENTYPE)x, (BGENTYPE)y) >> GENSIZE); \ + } + +__CLC_MUL_HI_IMPL(short, __spirv_ocl_s_mul_hi, char, 8) +__CLC_MUL_HI_IMPL(short, __spirv_ocl_s_mul_hi, schar, 8) +__CLC_MUL_HI_IMPL(ushort, __spirv_ocl_u_mul_hi, uchar, 8) +__CLC_MUL_HI_IMPL(int, __spirv_ocl_s_mul_hi, short, 16) +__CLC_MUL_HI_IMPL(uint, __spirv_ocl_u_mul_hi, ushort, 16) + +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, char, __spirv_ocl_s_mul_hi, char, + char) +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, schar, __spirv_ocl_s_mul_hi, + schar, schar) +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, short, __spirv_ocl_s_mul_hi, + short, short) +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, int, __spirv_ocl_s_mul_hi, int, + int) +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, long, __spirv_ocl_s_mul_hi, long, + long) +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, uchar, __spirv_ocl_u_mul_hi, + uchar, uchar) +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, ushort, __spirv_ocl_u_mul_hi, + ushort, ushort) +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, uint, __spirv_ocl_u_mul_hi, uint, + uint) +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, ulong, __spirv_ocl_u_mul_hi, + ulong, ulong) diff --git a/libclc/test/binding/core/BitCount.cl b/libclc/test/binding/core/BitCount.cl new file mode 100644 index 0000000000000..a090a1412edb2 --- /dev/null +++ b/libclc/test/binding/core/BitCount.cl @@ -0,0 +1,256 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_BitCount(__clc_int8_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_BitCount(__clc_vec2_int8_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_BitCount(__clc_vec3_int8_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_BitCount(__clc_vec4_int8_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_BitCount(__clc_vec8_int8_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_BitCount(__clc_vec16_int8_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_BitCount(__clc_uint8_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_BitCount(__clc_vec2_uint8_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_BitCount(__clc_vec3_uint8_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_BitCount(__clc_vec4_uint8_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_BitCount(__clc_vec8_uint8_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_BitCount(__clc_vec16_uint8_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_BitCount(__clc_int16_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_BitCount(__clc_vec2_int16_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_BitCount(__clc_vec3_int16_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_BitCount(__clc_vec4_int16_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_BitCount(__clc_vec8_int16_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_BitCount(__clc_vec16_int16_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_BitCount(__clc_uint16_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_BitCount(__clc_vec2_uint16_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_BitCount(__clc_vec3_uint16_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_BitCount(__clc_vec4_uint16_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_BitCount(__clc_vec8_uint16_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_BitCount(__clc_vec16_uint16_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_BitCount(__clc_int32_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_BitCount(__clc_vec2_int32_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_BitCount(__clc_vec3_int32_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_BitCount(__clc_vec4_int32_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_BitCount(__clc_vec8_int32_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_BitCount(__clc_vec16_int32_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_BitCount(__clc_uint32_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_BitCount(__clc_vec2_uint32_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_BitCount(__clc_vec3_uint32_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_BitCount(__clc_vec4_uint32_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_BitCount(__clc_vec8_uint32_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_BitCount(__clc_vec16_uint32_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_BitCount(__clc_int64_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_BitCount(__clc_vec2_int64_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_BitCount(__clc_vec3_int64_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_BitCount(__clc_vec4_int64_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_BitCount(__clc_vec8_int64_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_BitCount(__clc_vec16_int64_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_BitCount(__clc_uint64_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_BitCount(__clc_vec2_uint64_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_BitCount(__clc_vec3_uint64_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_BitCount(__clc_vec4_uint64_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_BitCount(__clc_vec8_uint64_t args_0) { + return __spirv_BitCount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_BitCount(__clc_vec16_uint64_t args_0) { + return __spirv_BitCount(args_0); +} diff --git a/libclc/test/binding/ocl/clz.cl b/libclc/test/binding/ocl/clz.cl new file mode 100644 index 0000000000000..0994098545574 --- /dev/null +++ b/libclc/test/binding/ocl/clz.cl @@ -0,0 +1,256 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_clz(__clc_int8_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_clz(__clc_vec2_int8_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_clz(__clc_vec3_int8_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_clz(__clc_vec4_int8_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_clz(__clc_vec8_int8_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_clz(__clc_vec16_int8_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_clz(__clc_uint8_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_clz(__clc_vec2_uint8_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_clz(__clc_vec3_uint8_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_clz(__clc_vec4_uint8_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_clz(__clc_vec8_uint8_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_clz(__clc_vec16_uint8_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_clz(__clc_int16_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_clz(__clc_vec2_int16_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_clz(__clc_vec3_int16_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_clz(__clc_vec4_int16_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_clz(__clc_vec8_int16_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_clz(__clc_vec16_int16_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_clz(__clc_uint16_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_clz(__clc_vec2_uint16_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_clz(__clc_vec3_uint16_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_clz(__clc_vec4_uint16_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_clz(__clc_vec8_uint16_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_clz(__clc_vec16_uint16_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_clz(__clc_int32_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_clz(__clc_vec2_int32_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_clz(__clc_vec3_int32_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_clz(__clc_vec4_int32_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_clz(__clc_vec8_int32_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_clz(__clc_vec16_int32_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_clz(__clc_uint32_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_clz(__clc_vec2_uint32_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_clz(__clc_vec3_uint32_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_clz(__clc_vec4_uint32_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_clz(__clc_vec8_uint32_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_clz(__clc_vec16_uint32_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_clz(__clc_int64_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_clz(__clc_vec2_int64_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_clz(__clc_vec3_int64_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_clz(__clc_vec4_int64_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_clz(__clc_vec8_int64_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_clz(__clc_vec16_int64_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_clz(__clc_uint64_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_clz(__clc_vec2_uint64_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_clz(__clc_vec3_uint64_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_clz(__clc_vec4_uint64_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_clz(__clc_vec8_uint64_t args_0) { + return __spirv_ocl_clz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_clz(__clc_vec16_uint64_t args_0) { + return __spirv_ocl_clz(args_0); +} diff --git a/libclc/test/binding/ocl/ctz.cl b/libclc/test/binding/ocl/ctz.cl new file mode 100644 index 0000000000000..a4961fbff6ffb --- /dev/null +++ b/libclc/test/binding/ocl/ctz.cl @@ -0,0 +1,256 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_ctz(__clc_int8_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_ctz(__clc_vec2_int8_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_ctz(__clc_vec3_int8_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_ctz(__clc_vec4_int8_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_ctz(__clc_vec8_int8_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_ctz(__clc_vec16_int8_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_ctz(__clc_uint8_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_ctz(__clc_vec2_uint8_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_ctz(__clc_vec3_uint8_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_ctz(__clc_vec4_uint8_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_ctz(__clc_vec8_uint8_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_ctz(__clc_vec16_uint8_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_ctz(__clc_int16_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_ctz(__clc_vec2_int16_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_ctz(__clc_vec3_int16_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_ctz(__clc_vec4_int16_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_ctz(__clc_vec8_int16_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_ctz(__clc_vec16_int16_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_ctz(__clc_uint16_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_ctz(__clc_vec2_uint16_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_ctz(__clc_vec3_uint16_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_ctz(__clc_vec4_uint16_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_ctz(__clc_vec8_uint16_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_ctz(__clc_vec16_uint16_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_ctz(__clc_int32_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_ctz(__clc_vec2_int32_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_ctz(__clc_vec3_int32_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_ctz(__clc_vec4_int32_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_ctz(__clc_vec8_int32_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_ctz(__clc_vec16_int32_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_ctz(__clc_uint32_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_ctz(__clc_vec2_uint32_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_ctz(__clc_vec3_uint32_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_ctz(__clc_vec4_uint32_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_ctz(__clc_vec8_uint32_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_ctz(__clc_vec16_uint32_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_ctz(__clc_int64_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_ctz(__clc_vec2_int64_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_ctz(__clc_vec3_int64_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_ctz(__clc_vec4_int64_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_ctz(__clc_vec8_int64_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_ctz(__clc_vec16_int64_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_ctz(__clc_uint64_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_ctz(__clc_vec2_uint64_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_ctz(__clc_vec3_uint64_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_ctz(__clc_vec4_uint64_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_ctz(__clc_vec8_uint64_t args_0) { + return __spirv_ocl_ctz(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_ctz(__clc_vec16_uint64_t args_0) { + return __spirv_ocl_ctz(args_0); +} diff --git a/libclc/test/binding/ocl/fabs.cl b/libclc/test/binding/ocl/fabs.cl new file mode 100644 index 0000000000000..6db0080b0fd20 --- /dev/null +++ b/libclc/test/binding/ocl/fabs.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_fabs(__clc_fp32_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_fabs(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_fabs(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_fabs(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_fabs(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_fabs(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_fabs(__clc_fp64_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_fabs(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_fabs(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_fabs(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_fabs(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_fabs(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_fabs(__clc_fp16_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_fabs(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_fabs(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_fabs(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_fabs(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_fabs(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_fabs(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/popcount.cl b/libclc/test/binding/ocl/popcount.cl new file mode 100644 index 0000000000000..929d3a09e4996 --- /dev/null +++ b/libclc/test/binding/ocl/popcount.cl @@ -0,0 +1,256 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_popcount(__clc_int8_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_popcount(__clc_vec2_int8_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_popcount(__clc_vec3_int8_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_popcount(__clc_vec4_int8_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_popcount(__clc_vec8_int8_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_popcount(__clc_vec16_int8_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_popcount(__clc_uint8_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_popcount(__clc_vec2_uint8_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_popcount(__clc_vec3_uint8_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_popcount(__clc_vec4_uint8_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_popcount(__clc_vec8_uint8_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_popcount(__clc_vec16_uint8_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_popcount(__clc_int16_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_popcount(__clc_vec2_int16_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_popcount(__clc_vec3_int16_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_popcount(__clc_vec4_int16_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_popcount(__clc_vec8_int16_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_popcount(__clc_vec16_int16_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_popcount(__clc_uint16_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_popcount(__clc_vec2_uint16_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_popcount(__clc_vec3_uint16_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_popcount(__clc_vec4_uint16_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_popcount(__clc_vec8_uint16_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_popcount(__clc_vec16_uint16_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_popcount(__clc_int32_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_popcount(__clc_vec2_int32_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_popcount(__clc_vec3_int32_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_popcount(__clc_vec4_int32_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_popcount(__clc_vec8_int32_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_popcount(__clc_vec16_int32_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_popcount(__clc_uint32_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_popcount(__clc_vec2_uint32_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_popcount(__clc_vec3_uint32_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_popcount(__clc_vec4_uint32_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_popcount(__clc_vec8_uint32_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_popcount(__clc_vec16_uint32_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_popcount(__clc_int64_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_popcount(__clc_vec2_int64_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_popcount(__clc_vec3_int64_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_popcount(__clc_vec4_int64_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_popcount(__clc_vec8_int64_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_popcount(__clc_vec16_int64_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_popcount(__clc_uint64_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_popcount(__clc_vec2_uint64_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_popcount(__clc_vec3_uint64_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_popcount(__clc_vec4_uint64_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_popcount(__clc_vec8_uint64_t args_0) { + return __spirv_ocl_popcount(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_popcount(__clc_vec16_uint64_t args_0) { + return __spirv_ocl_popcount(args_0); +} diff --git a/libclc/test/binding/ocl/rotate.cl b/libclc/test/binding/ocl/rotate.cl new file mode 100644 index 0000000000000..fcdbc76f5fa61 --- /dev/null +++ b/libclc/test/binding/ocl/rotate.cl @@ -0,0 +1,275 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_rotate(__clc_int8_t args_0, __clc_int8_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_rotate(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_rotate(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_rotate(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_rotate(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_rotate(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_rotate(__clc_uint8_t args_0, __clc_uint8_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_rotate(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_rotate(__clc_vec3_uint8_t args_0, __clc_vec3_uint8_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_rotate(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_rotate(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_rotate(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_rotate(__clc_int16_t args_0, __clc_int16_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_rotate(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_rotate(__clc_vec3_int16_t args_0, __clc_vec3_int16_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_rotate(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_rotate(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_rotate(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_rotate(__clc_uint16_t args_0, __clc_uint16_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_rotate(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_rotate(__clc_vec3_uint16_t args_0, + __clc_vec3_uint16_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_rotate(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_rotate(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_rotate(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_rotate(__clc_int32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_rotate(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_rotate(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_rotate(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_rotate(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_rotate(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_rotate(__clc_uint32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_rotate(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_rotate(__clc_vec3_uint32_t args_0, + __clc_vec3_uint32_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_rotate(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_rotate(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_rotate(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_rotate(__clc_int64_t args_0, __clc_int64_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_rotate(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_rotate(__clc_vec3_int64_t args_0, __clc_vec3_int64_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_rotate(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_rotate(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_rotate(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_rotate(__clc_uint64_t args_0, __clc_uint64_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_rotate(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_rotate(__clc_vec3_uint64_t args_0, + __clc_vec3_uint64_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_rotate(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_rotate(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_rotate(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_rotate(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/s_abs.cl b/libclc/test/binding/ocl/s_abs.cl new file mode 100644 index 0000000000000..61533e8c34469 --- /dev/null +++ b/libclc/test/binding/ocl/s_abs.cl @@ -0,0 +1,136 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_s_abs(__clc_int8_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_s_abs(__clc_vec2_int8_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_s_abs(__clc_vec3_int8_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_s_abs(__clc_vec4_int8_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_s_abs(__clc_vec8_int8_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_s_abs(__clc_vec16_int8_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_s_abs(__clc_int16_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_s_abs(__clc_vec2_int16_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_s_abs(__clc_vec3_int16_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_s_abs(__clc_vec4_int16_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_s_abs(__clc_vec8_int16_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_s_abs(__clc_vec16_int16_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_s_abs(__clc_int32_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_s_abs(__clc_vec2_int32_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_s_abs(__clc_vec3_int32_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_s_abs(__clc_vec4_int32_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_s_abs(__clc_vec8_int32_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_s_abs(__clc_vec16_int32_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_s_abs(__clc_int64_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_s_abs(__clc_vec2_int64_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_s_abs(__clc_vec3_int64_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_s_abs(__clc_vec4_int64_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_s_abs(__clc_vec8_int64_t args_0) { + return __spirv_ocl_s_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_s_abs(__clc_vec16_int64_t args_0) { + return __spirv_ocl_s_abs(args_0); +} diff --git a/libclc/test/binding/ocl/s_abs_diff.cl b/libclc/test/binding/ocl/s_abs_diff.cl new file mode 100644 index 0000000000000..878974fc074e4 --- /dev/null +++ b/libclc/test/binding/ocl/s_abs_diff.cl @@ -0,0 +1,156 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_s_abs_diff(__clc_int8_t args_0, __clc_int8_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_s_abs_diff(__clc_vec2_int8_t args_0, + __clc_vec2_int8_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_s_abs_diff(__clc_vec3_int8_t args_0, + __clc_vec3_int8_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_s_abs_diff(__clc_vec4_int8_t args_0, + __clc_vec4_int8_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_s_abs_diff(__clc_vec8_int8_t args_0, + __clc_vec8_int8_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_s_abs_diff(__clc_vec16_int8_t args_0, + __clc_vec16_int8_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_s_abs_diff(__clc_int16_t args_0, __clc_int16_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_s_abs_diff(__clc_vec2_int16_t args_0, + __clc_vec2_int16_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_s_abs_diff(__clc_vec3_int16_t args_0, + __clc_vec3_int16_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_s_abs_diff(__clc_vec4_int16_t args_0, + __clc_vec4_int16_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_s_abs_diff(__clc_vec8_int16_t args_0, + __clc_vec8_int16_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_s_abs_diff(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_s_abs_diff(__clc_int32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_s_abs_diff(__clc_vec2_int32_t args_0, + __clc_vec2_int32_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_s_abs_diff(__clc_vec3_int32_t args_0, + __clc_vec3_int32_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_s_abs_diff(__clc_vec4_int32_t args_0, + __clc_vec4_int32_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_s_abs_diff(__clc_vec8_int32_t args_0, + __clc_vec8_int32_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_s_abs_diff(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_s_abs_diff(__clc_int64_t args_0, __clc_int64_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_s_abs_diff(__clc_vec2_int64_t args_0, + __clc_vec2_int64_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_s_abs_diff(__clc_vec3_int64_t args_0, + __clc_vec3_int64_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_s_abs_diff(__clc_vec4_int64_t args_0, + __clc_vec4_int64_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_s_abs_diff(__clc_vec8_int64_t args_0, + __clc_vec8_int64_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_s_abs_diff(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1) { + return __spirv_ocl_s_abs_diff(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/s_add_sat.cl b/libclc/test/binding/ocl/s_add_sat.cl new file mode 100644 index 0000000000000..7047dd358154f --- /dev/null +++ b/libclc/test/binding/ocl/s_add_sat.cl @@ -0,0 +1,152 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_s_add_sat(__clc_int8_t args_0, __clc_int8_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_s_add_sat(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_s_add_sat(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_s_add_sat(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_s_add_sat(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_s_add_sat(__clc_vec16_int8_t args_0, + __clc_vec16_int8_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_s_add_sat(__clc_int16_t args_0, __clc_int16_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_s_add_sat(__clc_vec2_int16_t args_0, + __clc_vec2_int16_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_s_add_sat(__clc_vec3_int16_t args_0, + __clc_vec3_int16_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_s_add_sat(__clc_vec4_int16_t args_0, + __clc_vec4_int16_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_s_add_sat(__clc_vec8_int16_t args_0, + __clc_vec8_int16_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_s_add_sat(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_add_sat(__clc_int32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_add_sat(__clc_vec2_int32_t args_0, + __clc_vec2_int32_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_add_sat(__clc_vec3_int32_t args_0, + __clc_vec3_int32_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_add_sat(__clc_vec4_int32_t args_0, + __clc_vec4_int32_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_add_sat(__clc_vec8_int32_t args_0, + __clc_vec8_int32_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_add_sat(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_s_add_sat(__clc_int64_t args_0, __clc_int64_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_s_add_sat(__clc_vec2_int64_t args_0, + __clc_vec2_int64_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_s_add_sat(__clc_vec3_int64_t args_0, + __clc_vec3_int64_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_s_add_sat(__clc_vec4_int64_t args_0, + __clc_vec4_int64_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_s_add_sat(__clc_vec8_int64_t args_0, + __clc_vec8_int64_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_s_add_sat(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1) { + return __spirv_ocl_s_add_sat(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/s_hadd.cl b/libclc/test/binding/ocl/s_hadd.cl new file mode 100644 index 0000000000000..9718e91b23316 --- /dev/null +++ b/libclc/test/binding/ocl/s_hadd.cl @@ -0,0 +1,139 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_s_hadd(__clc_int8_t args_0, __clc_int8_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_s_hadd(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_s_hadd(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_s_hadd(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_s_hadd(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_s_hadd(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_s_hadd(__clc_int16_t args_0, __clc_int16_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_s_hadd(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_s_hadd(__clc_vec3_int16_t args_0, __clc_vec3_int16_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_s_hadd(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_s_hadd(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_s_hadd(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_hadd(__clc_int32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_hadd(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_hadd(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_hadd(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_hadd(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_hadd(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_s_hadd(__clc_int64_t args_0, __clc_int64_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_s_hadd(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_s_hadd(__clc_vec3_int64_t args_0, __clc_vec3_int64_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_s_hadd(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_s_hadd(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_s_hadd(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1) { + return __spirv_ocl_s_hadd(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/s_mad24.cl b/libclc/test/binding/ocl/s_mad24.cl new file mode 100644 index 0000000000000..c5e60f7c8d5c3 --- /dev/null +++ b/libclc/test/binding/ocl/s_mad24.cl @@ -0,0 +1,52 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_mad24(__clc_int32_t args_0, __clc_int32_t args_1, + __clc_int32_t args_2) { + return __spirv_ocl_s_mad24(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_mad24(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1, + __clc_vec2_int32_t args_2) { + return __spirv_ocl_s_mad24(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_mad24(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1, + __clc_vec3_int32_t args_2) { + return __spirv_ocl_s_mad24(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_mad24(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1, + __clc_vec4_int32_t args_2) { + return __spirv_ocl_s_mad24(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_mad24(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1, + __clc_vec8_int32_t args_2) { + return __spirv_ocl_s_mad24(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_mad24(__clc_vec16_int32_t args_0, __clc_vec16_int32_t args_1, + __clc_vec16_int32_t args_2) { + return __spirv_ocl_s_mad24(args_0, args_1, args_2); +} diff --git a/libclc/test/binding/ocl/s_mad_hi.cl b/libclc/test/binding/ocl/s_mad_hi.cl new file mode 100644 index 0000000000000..7ebd56c6f4387 --- /dev/null +++ b/libclc/test/binding/ocl/s_mad_hi.cl @@ -0,0 +1,163 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_s_mad_hi(__clc_int8_t args_0, __clc_int8_t args_1, + __clc_int8_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_s_mad_hi(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1, + __clc_vec2_int8_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_s_mad_hi(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1, + __clc_vec3_int8_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_s_mad_hi(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1, + __clc_vec4_int8_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_s_mad_hi(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1, + __clc_vec8_int8_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_s_mad_hi(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1, + __clc_vec16_int8_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_s_mad_hi(__clc_int16_t args_0, __clc_int16_t args_1, + __clc_int16_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_s_mad_hi(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1, + __clc_vec2_int16_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_s_mad_hi(__clc_vec3_int16_t args_0, __clc_vec3_int16_t args_1, + __clc_vec3_int16_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_s_mad_hi(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1, + __clc_vec4_int16_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_s_mad_hi(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1, + __clc_vec8_int16_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_s_mad_hi(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1, + __clc_vec16_int16_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_mad_hi(__clc_int32_t args_0, __clc_int32_t args_1, + __clc_int32_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_mad_hi(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1, + __clc_vec2_int32_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_mad_hi(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1, + __clc_vec3_int32_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_mad_hi(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1, + __clc_vec4_int32_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_mad_hi(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1, + __clc_vec8_int32_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_mad_hi(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1, + __clc_vec16_int32_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_s_mad_hi(__clc_int64_t args_0, __clc_int64_t args_1, + __clc_int64_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_s_mad_hi(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1, + __clc_vec2_int64_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_s_mad_hi(__clc_vec3_int64_t args_0, __clc_vec3_int64_t args_1, + __clc_vec3_int64_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_s_mad_hi(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1, + __clc_vec4_int64_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_s_mad_hi(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1, + __clc_vec8_int64_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_s_mad_hi(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1, + __clc_vec16_int64_t args_2) { + return __spirv_ocl_s_mad_hi(args_0, args_1, args_2); +} diff --git a/libclc/test/binding/ocl/s_mad_sat.cl b/libclc/test/binding/ocl/s_mad_sat.cl new file mode 100644 index 0000000000000..511b438a1e292 --- /dev/null +++ b/libclc/test/binding/ocl/s_mad_sat.cl @@ -0,0 +1,163 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_s_mad_sat(__clc_int8_t args_0, __clc_int8_t args_1, + __clc_int8_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_s_mad_sat(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1, + __clc_vec2_int8_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_s_mad_sat(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1, + __clc_vec3_int8_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_s_mad_sat(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1, + __clc_vec4_int8_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_s_mad_sat(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1, + __clc_vec8_int8_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_s_mad_sat(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1, + __clc_vec16_int8_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_s_mad_sat(__clc_int16_t args_0, __clc_int16_t args_1, + __clc_int16_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_s_mad_sat(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1, + __clc_vec2_int16_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_s_mad_sat(__clc_vec3_int16_t args_0, __clc_vec3_int16_t args_1, + __clc_vec3_int16_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_s_mad_sat(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1, + __clc_vec4_int16_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_s_mad_sat(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1, + __clc_vec8_int16_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_s_mad_sat(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1, + __clc_vec16_int16_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_mad_sat(__clc_int32_t args_0, __clc_int32_t args_1, + __clc_int32_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_mad_sat(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1, + __clc_vec2_int32_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_mad_sat(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1, + __clc_vec3_int32_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_mad_sat(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1, + __clc_vec4_int32_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_mad_sat(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1, + __clc_vec8_int32_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_mad_sat(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1, + __clc_vec16_int32_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_s_mad_sat(__clc_int64_t args_0, __clc_int64_t args_1, + __clc_int64_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_s_mad_sat(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1, + __clc_vec2_int64_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_s_mad_sat(__clc_vec3_int64_t args_0, __clc_vec3_int64_t args_1, + __clc_vec3_int64_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_s_mad_sat(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1, + __clc_vec4_int64_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_s_mad_sat(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1, + __clc_vec8_int64_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_s_mad_sat(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1, + __clc_vec16_int64_t args_2) { + return __spirv_ocl_s_mad_sat(args_0, args_1, args_2); +} diff --git a/libclc/test/binding/ocl/s_mul24.cl b/libclc/test/binding/ocl/s_mul24.cl new file mode 100644 index 0000000000000..da5b1e979364a --- /dev/null +++ b/libclc/test/binding/ocl/s_mul24.cl @@ -0,0 +1,47 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_mul24(__clc_int32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_s_mul24(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_mul24(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_s_mul24(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_mul24(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_s_mul24(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_mul24(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_s_mul24(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_mul24(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_s_mul24(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_mul24(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1) { + return __spirv_ocl_s_mul24(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/s_mul_hi.cl b/libclc/test/binding/ocl/s_mul_hi.cl new file mode 100644 index 0000000000000..80d31c76e424e --- /dev/null +++ b/libclc/test/binding/ocl/s_mul_hi.cl @@ -0,0 +1,152 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_s_mul_hi(__clc_int8_t args_0, __clc_int8_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_s_mul_hi(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_s_mul_hi(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_s_mul_hi(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_s_mul_hi(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_s_mul_hi(__clc_vec16_int8_t args_0, + __clc_vec16_int8_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_s_mul_hi(__clc_int16_t args_0, __clc_int16_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_s_mul_hi(__clc_vec2_int16_t args_0, + __clc_vec2_int16_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_s_mul_hi(__clc_vec3_int16_t args_0, + __clc_vec3_int16_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_s_mul_hi(__clc_vec4_int16_t args_0, + __clc_vec4_int16_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_s_mul_hi(__clc_vec8_int16_t args_0, + __clc_vec8_int16_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_s_mul_hi(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_mul_hi(__clc_int32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_mul_hi(__clc_vec2_int32_t args_0, + __clc_vec2_int32_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_mul_hi(__clc_vec3_int32_t args_0, + __clc_vec3_int32_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_mul_hi(__clc_vec4_int32_t args_0, + __clc_vec4_int32_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_mul_hi(__clc_vec8_int32_t args_0, + __clc_vec8_int32_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_mul_hi(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_s_mul_hi(__clc_int64_t args_0, __clc_int64_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_s_mul_hi(__clc_vec2_int64_t args_0, + __clc_vec2_int64_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_s_mul_hi(__clc_vec3_int64_t args_0, + __clc_vec3_int64_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_s_mul_hi(__clc_vec4_int64_t args_0, + __clc_vec4_int64_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_s_mul_hi(__clc_vec8_int64_t args_0, + __clc_vec8_int64_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_s_mul_hi(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1) { + return __spirv_ocl_s_mul_hi(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/s_rhadd.cl b/libclc/test/binding/ocl/s_rhadd.cl new file mode 100644 index 0000000000000..8fe05c520b67f --- /dev/null +++ b/libclc/test/binding/ocl/s_rhadd.cl @@ -0,0 +1,139 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_s_rhadd(__clc_int8_t args_0, __clc_int8_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_s_rhadd(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_s_rhadd(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_s_rhadd(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_s_rhadd(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_s_rhadd(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_s_rhadd(__clc_int16_t args_0, __clc_int16_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_s_rhadd(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_s_rhadd(__clc_vec3_int16_t args_0, __clc_vec3_int16_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_s_rhadd(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_s_rhadd(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_s_rhadd(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_rhadd(__clc_int32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_rhadd(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_rhadd(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_rhadd(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_rhadd(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_rhadd(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_s_rhadd(__clc_int64_t args_0, __clc_int64_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_s_rhadd(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_s_rhadd(__clc_vec3_int64_t args_0, __clc_vec3_int64_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_s_rhadd(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_s_rhadd(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_s_rhadd(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1) { + return __spirv_ocl_s_rhadd(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/s_sub_sat.cl b/libclc/test/binding/ocl/s_sub_sat.cl new file mode 100644 index 0000000000000..a13adcce40265 --- /dev/null +++ b/libclc/test/binding/ocl/s_sub_sat.cl @@ -0,0 +1,152 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_s_sub_sat(__clc_int8_t args_0, __clc_int8_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_s_sub_sat(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_s_sub_sat(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_s_sub_sat(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_s_sub_sat(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_s_sub_sat(__clc_vec16_int8_t args_0, + __clc_vec16_int8_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_s_sub_sat(__clc_int16_t args_0, __clc_int16_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_s_sub_sat(__clc_vec2_int16_t args_0, + __clc_vec2_int16_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_s_sub_sat(__clc_vec3_int16_t args_0, + __clc_vec3_int16_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_s_sub_sat(__clc_vec4_int16_t args_0, + __clc_vec4_int16_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_s_sub_sat(__clc_vec8_int16_t args_0, + __clc_vec8_int16_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_s_sub_sat(__clc_vec16_int16_t args_0, + __clc_vec16_int16_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_sub_sat(__clc_int32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_sub_sat(__clc_vec2_int32_t args_0, + __clc_vec2_int32_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_sub_sat(__clc_vec3_int32_t args_0, + __clc_vec3_int32_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_sub_sat(__clc_vec4_int32_t args_0, + __clc_vec4_int32_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_sub_sat(__clc_vec8_int32_t args_0, + __clc_vec8_int32_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_sub_sat(__clc_vec16_int32_t args_0, + __clc_vec16_int32_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_s_sub_sat(__clc_int64_t args_0, __clc_int64_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_s_sub_sat(__clc_vec2_int64_t args_0, + __clc_vec2_int64_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_s_sub_sat(__clc_vec3_int64_t args_0, + __clc_vec3_int64_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_s_sub_sat(__clc_vec4_int64_t args_0, + __clc_vec4_int64_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_s_sub_sat(__clc_vec8_int64_t args_0, + __clc_vec8_int64_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_s_sub_sat(__clc_vec16_int64_t args_0, + __clc_vec16_int64_t args_1) { + return __spirv_ocl_s_sub_sat(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/s_upsample.cl b/libclc/test/binding/ocl/s_upsample.cl new file mode 100644 index 0000000000000..bc3589c417aa1 --- /dev/null +++ b/libclc/test/binding/ocl/s_upsample.cl @@ -0,0 +1,121 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_s_upsample(__clc_int8_t args_0, __clc_uint8_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_s_upsample(__clc_vec2_int8_t args_0, + __clc_vec2_uint8_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_s_upsample(__clc_vec3_int8_t args_0, + __clc_vec3_uint8_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_s_upsample(__clc_vec4_int8_t args_0, + __clc_vec4_uint8_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_s_upsample(__clc_vec8_int8_t args_0, + __clc_vec8_uint8_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_s_upsample(__clc_vec16_int8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_upsample(__clc_int16_t args_0, __clc_uint16_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_upsample(__clc_vec2_int16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_upsample(__clc_vec3_int16_t args_0, + __clc_vec3_uint16_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_upsample(__clc_vec4_int16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_upsample(__clc_vec8_int16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_upsample(__clc_vec16_int16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_s_upsample(__clc_int32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_s_upsample(__clc_vec2_int32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_s_upsample(__clc_vec3_int32_t args_0, + __clc_vec3_uint32_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_s_upsample(__clc_vec4_int32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_s_upsample(__clc_vec8_int32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_s_upsample(__clc_vec16_int32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_s_upsample(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/u_abs.cl b/libclc/test/binding/ocl/u_abs.cl new file mode 100644 index 0000000000000..59f28a6efb149 --- /dev/null +++ b/libclc/test/binding/ocl/u_abs.cl @@ -0,0 +1,136 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_u_abs(__clc_uint8_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_u_abs(__clc_vec2_uint8_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_u_abs(__clc_vec3_uint8_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_u_abs(__clc_vec4_uint8_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_u_abs(__clc_vec8_uint8_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_u_abs(__clc_vec16_uint8_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_abs(__clc_uint16_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_abs(__clc_vec2_uint16_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_abs(__clc_vec3_uint16_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_abs(__clc_vec4_uint16_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_abs(__clc_vec8_uint16_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_abs(__clc_vec16_uint16_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_abs(__clc_uint32_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_abs(__clc_vec2_uint32_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_abs(__clc_vec3_uint32_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_abs(__clc_vec4_uint32_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_abs(__clc_vec8_uint32_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_abs(__clc_vec16_uint32_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_abs(__clc_uint64_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_abs(__clc_vec2_uint64_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_abs(__clc_vec3_uint64_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_abs(__clc_vec4_uint64_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_abs(__clc_vec8_uint64_t args_0) { + return __spirv_ocl_u_abs(args_0); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_abs(__clc_vec16_uint64_t args_0) { + return __spirv_ocl_u_abs(args_0); +} diff --git a/libclc/test/binding/ocl/u_abs_diff.cl b/libclc/test/binding/ocl/u_abs_diff.cl new file mode 100644 index 0000000000000..b6d5438e92974 --- /dev/null +++ b/libclc/test/binding/ocl/u_abs_diff.cl @@ -0,0 +1,156 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_u_abs_diff(__clc_uint8_t args_0, __clc_uint8_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_u_abs_diff(__clc_vec2_uint8_t args_0, + __clc_vec2_uint8_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_u_abs_diff(__clc_vec3_uint8_t args_0, + __clc_vec3_uint8_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_u_abs_diff(__clc_vec4_uint8_t args_0, + __clc_vec4_uint8_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_u_abs_diff(__clc_vec8_uint8_t args_0, + __clc_vec8_uint8_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_u_abs_diff(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_abs_diff(__clc_uint16_t args_0, __clc_uint16_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_abs_diff(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_abs_diff(__clc_vec3_uint16_t args_0, + __clc_vec3_uint16_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_abs_diff(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_abs_diff(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_abs_diff(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_abs_diff(__clc_uint32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_abs_diff(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_abs_diff(__clc_vec3_uint32_t args_0, + __clc_vec3_uint32_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_abs_diff(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_abs_diff(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_abs_diff(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_abs_diff(__clc_uint64_t args_0, __clc_uint64_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_abs_diff(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_abs_diff(__clc_vec3_uint64_t args_0, + __clc_vec3_uint64_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_abs_diff(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_abs_diff(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_abs_diff(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_u_abs_diff(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/u_add_sat.cl b/libclc/test/binding/ocl/u_add_sat.cl new file mode 100644 index 0000000000000..462bb4ffb0e62 --- /dev/null +++ b/libclc/test/binding/ocl/u_add_sat.cl @@ -0,0 +1,156 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_u_add_sat(__clc_uint8_t args_0, __clc_uint8_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_u_add_sat(__clc_vec2_uint8_t args_0, + __clc_vec2_uint8_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_u_add_sat(__clc_vec3_uint8_t args_0, + __clc_vec3_uint8_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_u_add_sat(__clc_vec4_uint8_t args_0, + __clc_vec4_uint8_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_u_add_sat(__clc_vec8_uint8_t args_0, + __clc_vec8_uint8_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_u_add_sat(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_add_sat(__clc_uint16_t args_0, __clc_uint16_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_add_sat(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_add_sat(__clc_vec3_uint16_t args_0, + __clc_vec3_uint16_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_add_sat(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_add_sat(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_add_sat(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_add_sat(__clc_uint32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_add_sat(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_add_sat(__clc_vec3_uint32_t args_0, + __clc_vec3_uint32_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_add_sat(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_add_sat(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_add_sat(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_add_sat(__clc_uint64_t args_0, __clc_uint64_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_add_sat(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_add_sat(__clc_vec3_uint64_t args_0, + __clc_vec3_uint64_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_add_sat(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_add_sat(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_add_sat(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_u_add_sat(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/u_hadd.cl b/libclc/test/binding/ocl/u_hadd.cl new file mode 100644 index 0000000000000..df0055ce7ef37 --- /dev/null +++ b/libclc/test/binding/ocl/u_hadd.cl @@ -0,0 +1,152 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_u_hadd(__clc_uint8_t args_0, __clc_uint8_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_u_hadd(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_u_hadd(__clc_vec3_uint8_t args_0, __clc_vec3_uint8_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_u_hadd(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_u_hadd(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_u_hadd(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_hadd(__clc_uint16_t args_0, __clc_uint16_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_hadd(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_hadd(__clc_vec3_uint16_t args_0, + __clc_vec3_uint16_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_hadd(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_hadd(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_hadd(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_hadd(__clc_uint32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_hadd(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_hadd(__clc_vec3_uint32_t args_0, + __clc_vec3_uint32_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_hadd(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_hadd(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_hadd(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_hadd(__clc_uint64_t args_0, __clc_uint64_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_hadd(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_hadd(__clc_vec3_uint64_t args_0, + __clc_vec3_uint64_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_hadd(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_hadd(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_hadd(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_u_hadd(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/u_mad24.cl b/libclc/test/binding/ocl/u_mad24.cl new file mode 100644 index 0000000000000..bc5fa961e7136 --- /dev/null +++ b/libclc/test/binding/ocl/u_mad24.cl @@ -0,0 +1,53 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_mad24(__clc_uint32_t args_0, __clc_uint32_t args_1, + __clc_uint32_t args_2) { + return __spirv_ocl_u_mad24(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_mad24(__clc_vec2_uint32_t args_0, __clc_vec2_uint32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_u_mad24(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_mad24(__clc_vec3_uint32_t args_0, __clc_vec3_uint32_t args_1, + __clc_vec3_uint32_t args_2) { + return __spirv_ocl_u_mad24(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_mad24(__clc_vec4_uint32_t args_0, __clc_vec4_uint32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_u_mad24(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_mad24(__clc_vec8_uint32_t args_0, __clc_vec8_uint32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_u_mad24(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_mad24(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_u_mad24(args_0, args_1, args_2); +} diff --git a/libclc/test/binding/ocl/u_mad_hi.cl b/libclc/test/binding/ocl/u_mad_hi.cl new file mode 100644 index 0000000000000..59b7370f4febb --- /dev/null +++ b/libclc/test/binding/ocl/u_mad_hi.cl @@ -0,0 +1,176 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_u_mad_hi(__clc_uint8_t args_0, __clc_uint8_t args_1, + __clc_uint8_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_u_mad_hi(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_u_mad_hi(__clc_vec3_uint8_t args_0, __clc_vec3_uint8_t args_1, + __clc_vec3_uint8_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_u_mad_hi(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_u_mad_hi(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_u_mad_hi(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_mad_hi(__clc_uint16_t args_0, __clc_uint16_t args_1, + __clc_uint16_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_mad_hi(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_mad_hi(__clc_vec3_uint16_t args_0, + __clc_vec3_uint16_t args_1, + __clc_vec3_uint16_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_mad_hi(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_mad_hi(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_mad_hi(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_mad_hi(__clc_uint32_t args_0, __clc_uint32_t args_1, + __clc_uint32_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_mad_hi(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_mad_hi(__clc_vec3_uint32_t args_0, + __clc_vec3_uint32_t args_1, + __clc_vec3_uint32_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_mad_hi(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_mad_hi(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_mad_hi(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_mad_hi(__clc_uint64_t args_0, __clc_uint64_t args_1, + __clc_uint64_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_mad_hi(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_mad_hi(__clc_vec3_uint64_t args_0, + __clc_vec3_uint64_t args_1, + __clc_vec3_uint64_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_mad_hi(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_mad_hi(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_mad_hi(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_u_mad_hi(args_0, args_1, args_2); +} diff --git a/libclc/test/binding/ocl/u_mad_sat.cl b/libclc/test/binding/ocl/u_mad_sat.cl new file mode 100644 index 0000000000000..e10767283f5e4 --- /dev/null +++ b/libclc/test/binding/ocl/u_mad_sat.cl @@ -0,0 +1,176 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_u_mad_sat(__clc_uint8_t args_0, __clc_uint8_t args_1, + __clc_uint8_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_u_mad_sat(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_u_mad_sat(__clc_vec3_uint8_t args_0, __clc_vec3_uint8_t args_1, + __clc_vec3_uint8_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_u_mad_sat(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_u_mad_sat(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_u_mad_sat(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_mad_sat(__clc_uint16_t args_0, __clc_uint16_t args_1, + __clc_uint16_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_mad_sat(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_mad_sat(__clc_vec3_uint16_t args_0, + __clc_vec3_uint16_t args_1, + __clc_vec3_uint16_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_mad_sat(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_mad_sat(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_mad_sat(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_mad_sat(__clc_uint32_t args_0, __clc_uint32_t args_1, + __clc_uint32_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_mad_sat(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_mad_sat(__clc_vec3_uint32_t args_0, + __clc_vec3_uint32_t args_1, + __clc_vec3_uint32_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_mad_sat(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_mad_sat(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_mad_sat(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_mad_sat(__clc_uint64_t args_0, __clc_uint64_t args_1, + __clc_uint64_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_mad_sat(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_mad_sat(__clc_vec3_uint64_t args_0, + __clc_vec3_uint64_t args_1, + __clc_vec3_uint64_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_mad_sat(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_mad_sat(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_mad_sat(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_u_mad_sat(args_0, args_1, args_2); +} diff --git a/libclc/test/binding/ocl/u_mul24.cl b/libclc/test/binding/ocl/u_mul24.cl new file mode 100644 index 0000000000000..86e252417e7f1 --- /dev/null +++ b/libclc/test/binding/ocl/u_mul24.cl @@ -0,0 +1,51 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_mul24(__clc_uint32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_u_mul24(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_mul24(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_u_mul24(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_mul24(__clc_vec3_uint32_t args_0, + __clc_vec3_uint32_t args_1) { + return __spirv_ocl_u_mul24(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_mul24(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_u_mul24(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_mul24(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_u_mul24(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_mul24(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_u_mul24(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/u_mul_hi.cl b/libclc/test/binding/ocl/u_mul_hi.cl new file mode 100644 index 0000000000000..94505e6e7c5a5 --- /dev/null +++ b/libclc/test/binding/ocl/u_mul_hi.cl @@ -0,0 +1,156 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_u_mul_hi(__clc_uint8_t args_0, __clc_uint8_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_u_mul_hi(__clc_vec2_uint8_t args_0, + __clc_vec2_uint8_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_u_mul_hi(__clc_vec3_uint8_t args_0, + __clc_vec3_uint8_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_u_mul_hi(__clc_vec4_uint8_t args_0, + __clc_vec4_uint8_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_u_mul_hi(__clc_vec8_uint8_t args_0, + __clc_vec8_uint8_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_u_mul_hi(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_mul_hi(__clc_uint16_t args_0, __clc_uint16_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_mul_hi(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_mul_hi(__clc_vec3_uint16_t args_0, + __clc_vec3_uint16_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_mul_hi(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_mul_hi(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_mul_hi(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_mul_hi(__clc_uint32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_mul_hi(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_mul_hi(__clc_vec3_uint32_t args_0, + __clc_vec3_uint32_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_mul_hi(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_mul_hi(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_mul_hi(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_mul_hi(__clc_uint64_t args_0, __clc_uint64_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_mul_hi(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_mul_hi(__clc_vec3_uint64_t args_0, + __clc_vec3_uint64_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_mul_hi(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_mul_hi(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_mul_hi(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_u_mul_hi(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/u_rhadd.cl b/libclc/test/binding/ocl/u_rhadd.cl new file mode 100644 index 0000000000000..15ce9cc832b82 --- /dev/null +++ b/libclc/test/binding/ocl/u_rhadd.cl @@ -0,0 +1,152 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_u_rhadd(__clc_uint8_t args_0, __clc_uint8_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_u_rhadd(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_u_rhadd(__clc_vec3_uint8_t args_0, __clc_vec3_uint8_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_u_rhadd(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_u_rhadd(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_u_rhadd(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_rhadd(__clc_uint16_t args_0, __clc_uint16_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_rhadd(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_rhadd(__clc_vec3_uint16_t args_0, + __clc_vec3_uint16_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_rhadd(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_rhadd(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_rhadd(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_rhadd(__clc_uint32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_rhadd(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_rhadd(__clc_vec3_uint32_t args_0, + __clc_vec3_uint32_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_rhadd(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_rhadd(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_rhadd(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_rhadd(__clc_uint64_t args_0, __clc_uint64_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_rhadd(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_rhadd(__clc_vec3_uint64_t args_0, + __clc_vec3_uint64_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_rhadd(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_rhadd(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_rhadd(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_u_rhadd(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/u_sub_sat.cl b/libclc/test/binding/ocl/u_sub_sat.cl new file mode 100644 index 0000000000000..2cd1c3be986fd --- /dev/null +++ b/libclc/test/binding/ocl/u_sub_sat.cl @@ -0,0 +1,156 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_u_sub_sat(__clc_uint8_t args_0, __clc_uint8_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_u_sub_sat(__clc_vec2_uint8_t args_0, + __clc_vec2_uint8_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_u_sub_sat(__clc_vec3_uint8_t args_0, + __clc_vec3_uint8_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_u_sub_sat(__clc_vec4_uint8_t args_0, + __clc_vec4_uint8_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_u_sub_sat(__clc_vec8_uint8_t args_0, + __clc_vec8_uint8_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_u_sub_sat(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_sub_sat(__clc_uint16_t args_0, __clc_uint16_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_sub_sat(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_sub_sat(__clc_vec3_uint16_t args_0, + __clc_vec3_uint16_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_sub_sat(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_sub_sat(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_sub_sat(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_sub_sat(__clc_uint32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_sub_sat(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_sub_sat(__clc_vec3_uint32_t args_0, + __clc_vec3_uint32_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_sub_sat(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_sub_sat(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_sub_sat(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_sub_sat(__clc_uint64_t args_0, __clc_uint64_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_sub_sat(__clc_vec2_uint64_t args_0, + __clc_vec2_uint64_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_sub_sat(__clc_vec3_uint64_t args_0, + __clc_vec3_uint64_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_sub_sat(__clc_vec4_uint64_t args_0, + __clc_vec4_uint64_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_sub_sat(__clc_vec8_uint64_t args_0, + __clc_vec8_uint64_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_sub_sat(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_u_sub_sat(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/u_upsample.cl b/libclc/test/binding/ocl/u_upsample.cl new file mode 100644 index 0000000000000..9fa8c7f721980 --- /dev/null +++ b/libclc/test/binding/ocl/u_upsample.cl @@ -0,0 +1,121 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_upsample(__clc_uint8_t args_0, __clc_uint8_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_upsample(__clc_vec2_uint8_t args_0, + __clc_vec2_uint8_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_upsample(__clc_vec3_uint8_t args_0, + __clc_vec3_uint8_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_upsample(__clc_vec4_uint8_t args_0, + __clc_vec4_uint8_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_upsample(__clc_vec8_uint8_t args_0, + __clc_vec8_uint8_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_upsample(__clc_vec16_uint8_t args_0, + __clc_vec16_uint8_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_upsample(__clc_uint16_t args_0, __clc_uint16_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_upsample(__clc_vec2_uint16_t args_0, + __clc_vec2_uint16_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_upsample(__clc_vec3_uint16_t args_0, + __clc_vec3_uint16_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_upsample(__clc_vec4_uint16_t args_0, + __clc_vec4_uint16_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_upsample(__clc_vec8_uint16_t args_0, + __clc_vec8_uint16_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_upsample(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_upsample(__clc_uint32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_upsample(__clc_vec2_uint32_t args_0, + __clc_vec2_uint32_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_upsample(__clc_vec3_uint32_t args_0, + __clc_vec3_uint32_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_upsample(__clc_vec4_uint32_t args_0, + __clc_vec4_uint32_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_upsample(__clc_vec8_uint32_t args_0, + __clc_vec8_uint32_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_upsample(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_u_upsample(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vload_half.cl b/libclc/test/binding/ocl/vload_half.cl new file mode 100644 index 0000000000000..0a40994b78e68 --- /dev/null +++ b/libclc/test/binding/ocl/vload_half.cl @@ -0,0 +1,48 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_vload_half(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vload_half(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_vload_half(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vload_half(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_vload_half(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vload_half(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_vload_half(__clc_size_t args_0, __clc_fp16_t const *args_1) { + return __spirv_ocl_vload_half(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat16.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat16.cl new file mode 100644 index 0000000000000..b31ca3922d986 --- /dev/null +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat16.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_vload_halfn_Rfloat16(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vload_halfn_Rfloat16(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_vload_halfn_Rfloat16(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vload_halfn_Rfloat16(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_vload_halfn_Rfloat16(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vload_halfn_Rfloat16(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_vload_halfn_Rfloat16(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vload_halfn_Rfloat16(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat2.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat2.cl new file mode 100644 index 0000000000000..75a71c427f743 --- /dev/null +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat2.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_vload_halfn_Rfloat2(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vload_halfn_Rfloat2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_vload_halfn_Rfloat2(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vload_halfn_Rfloat2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_vload_halfn_Rfloat2(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vload_halfn_Rfloat2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_vload_halfn_Rfloat2(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vload_halfn_Rfloat2(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat3.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat3.cl new file mode 100644 index 0000000000000..4df587fab979e --- /dev/null +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat3.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_vload_halfn_Rfloat3(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vload_halfn_Rfloat3(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_vload_halfn_Rfloat3(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vload_halfn_Rfloat3(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_vload_halfn_Rfloat3(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vload_halfn_Rfloat3(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_vload_halfn_Rfloat3(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vload_halfn_Rfloat3(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat4.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat4.cl new file mode 100644 index 0000000000000..b9e04485670f5 --- /dev/null +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat4.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_vload_halfn_Rfloat4(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vload_halfn_Rfloat4(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_vload_halfn_Rfloat4(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vload_halfn_Rfloat4(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_vload_halfn_Rfloat4(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vload_halfn_Rfloat4(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_vload_halfn_Rfloat4(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vload_halfn_Rfloat4(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vload_halfn_Rfloat8.cl b/libclc/test/binding/ocl/vload_halfn_Rfloat8.cl new file mode 100644 index 0000000000000..9bc90a1c969c7 --- /dev/null +++ b/libclc/test/binding/ocl/vload_halfn_Rfloat8.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_vload_halfn_Rfloat8(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vload_halfn_Rfloat8(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_vload_halfn_Rfloat8(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vload_halfn_Rfloat8(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_vload_halfn_Rfloat8(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vload_halfn_Rfloat8(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_vload_halfn_Rfloat8(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vload_halfn_Rfloat8(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat16.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat16.cl new file mode 100644 index 0000000000000..33db3c919faa1 --- /dev/null +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat16.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat16(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat16(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat16(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat16(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat16(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat16(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat16(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat16(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat2.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat2.cl new file mode 100644 index 0000000000000..4eebdd6b99c9c --- /dev/null +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat2.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat2(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat2(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat2(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat2(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat2(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat3.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat3.cl new file mode 100644 index 0000000000000..f639dc249280d --- /dev/null +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat3.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat3(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat3(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat3(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat3(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat3(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat3(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat3(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat3(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat4.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat4.cl new file mode 100644 index 0000000000000..38a4c1f4e0ed2 --- /dev/null +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat4.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat4(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat4(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat4(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat4(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat4(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat4(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat4(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat4(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloada_halfn_Rfloat8.cl b/libclc/test/binding/ocl/vloada_halfn_Rfloat8.cl new file mode 100644 index 0000000000000..9e488611ea8ee --- /dev/null +++ b/libclc/test/binding/ocl/vloada_halfn_Rfloat8.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat8(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat8(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat8(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat8(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat8(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat8(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_vloada_halfn_Rfloat8(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vloada_halfn_Rfloat8(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloadn_Rchar16.cl b/libclc/test/binding/ocl/vloadn_Rchar16.cl new file mode 100644 index 0000000000000..6546af7807f81 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rchar16.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_vloadn_Rchar16(__clc_size_t args_0, + __clc_int8_t const __global *args_1) { + return __spirv_ocl_vloadn_Rchar16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_vloadn_Rchar16(__clc_size_t args_0, + __clc_int8_t const __local *args_1) { + return __spirv_ocl_vloadn_Rchar16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_vloadn_Rchar16(__clc_size_t args_0, + __clc_int8_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rchar16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_vloadn_Rchar16(__clc_size_t args_0, + __clc_int8_t const *args_1) { + return __spirv_ocl_vloadn_Rchar16(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rchar2.cl b/libclc/test/binding/ocl/vloadn_Rchar2.cl new file mode 100644 index 0000000000000..f58b7c015f555 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rchar2.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_vloadn_Rchar2(__clc_size_t args_0, + __clc_int8_t const __global *args_1) { + return __spirv_ocl_vloadn_Rchar2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_vloadn_Rchar2(__clc_size_t args_0, + __clc_int8_t const __local *args_1) { + return __spirv_ocl_vloadn_Rchar2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_vloadn_Rchar2(__clc_size_t args_0, + __clc_int8_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rchar2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_vloadn_Rchar2(__clc_size_t args_0, + __clc_int8_t const *args_1) { + return __spirv_ocl_vloadn_Rchar2(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rchar3.cl b/libclc/test/binding/ocl/vloadn_Rchar3.cl new file mode 100644 index 0000000000000..0e98f1b4eaa89 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rchar3.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_vloadn_Rchar3(__clc_size_t args_0, + __clc_int8_t const __global *args_1) { + return __spirv_ocl_vloadn_Rchar3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_vloadn_Rchar3(__clc_size_t args_0, + __clc_int8_t const __local *args_1) { + return __spirv_ocl_vloadn_Rchar3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_vloadn_Rchar3(__clc_size_t args_0, + __clc_int8_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rchar3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_vloadn_Rchar3(__clc_size_t args_0, + __clc_int8_t const *args_1) { + return __spirv_ocl_vloadn_Rchar3(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rchar4.cl b/libclc/test/binding/ocl/vloadn_Rchar4.cl new file mode 100644 index 0000000000000..3b495da48729c --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rchar4.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_vloadn_Rchar4(__clc_size_t args_0, + __clc_int8_t const __global *args_1) { + return __spirv_ocl_vloadn_Rchar4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_vloadn_Rchar4(__clc_size_t args_0, + __clc_int8_t const __local *args_1) { + return __spirv_ocl_vloadn_Rchar4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_vloadn_Rchar4(__clc_size_t args_0, + __clc_int8_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rchar4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_vloadn_Rchar4(__clc_size_t args_0, + __clc_int8_t const *args_1) { + return __spirv_ocl_vloadn_Rchar4(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rchar8.cl b/libclc/test/binding/ocl/vloadn_Rchar8.cl new file mode 100644 index 0000000000000..e1d5e43e315c4 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rchar8.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_vloadn_Rchar8(__clc_size_t args_0, + __clc_int8_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rchar8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_vloadn_Rchar8(__clc_size_t args_0, + __clc_int8_t const *args_1) { + return __spirv_ocl_vloadn_Rchar8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_vloadn_Rchar8(__clc_size_t args_0, + __clc_int8_t const __global *args_1) { + return __spirv_ocl_vloadn_Rchar8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_vloadn_Rchar8(__clc_size_t args_0, + __clc_int8_t const __local *args_1) { + return __spirv_ocl_vloadn_Rchar8(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rdouble16.cl b/libclc/test/binding/ocl/vloadn_Rdouble16.cl new file mode 100644 index 0000000000000..0ad97fd216a31 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rdouble16.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_vloadn_Rdouble16(__clc_size_t args_0, + __clc_fp64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rdouble16(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_vloadn_Rdouble16(__clc_size_t args_0, + __clc_fp64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rdouble16(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_vloadn_Rdouble16(__clc_size_t args_0, + __clc_fp64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rdouble16(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_vloadn_Rdouble16(__clc_size_t args_0, + __clc_fp64_t const *args_1) { + return __spirv_ocl_vloadn_Rdouble16(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloadn_Rdouble2.cl b/libclc/test/binding/ocl/vloadn_Rdouble2.cl new file mode 100644 index 0000000000000..f6649500a4ea3 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rdouble2.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_vloadn_Rdouble2(__clc_size_t args_0, + __clc_fp64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rdouble2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_vloadn_Rdouble2(__clc_size_t args_0, + __clc_fp64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rdouble2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_vloadn_Rdouble2(__clc_size_t args_0, + __clc_fp64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rdouble2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_vloadn_Rdouble2(__clc_size_t args_0, + __clc_fp64_t const *args_1) { + return __spirv_ocl_vloadn_Rdouble2(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloadn_Rdouble3.cl b/libclc/test/binding/ocl/vloadn_Rdouble3.cl new file mode 100644 index 0000000000000..e707c46029169 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rdouble3.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_vloadn_Rdouble3(__clc_size_t args_0, + __clc_fp64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rdouble3(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_vloadn_Rdouble3(__clc_size_t args_0, + __clc_fp64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rdouble3(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_vloadn_Rdouble3(__clc_size_t args_0, + __clc_fp64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rdouble3(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_vloadn_Rdouble3(__clc_size_t args_0, + __clc_fp64_t const *args_1) { + return __spirv_ocl_vloadn_Rdouble3(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloadn_Rdouble4.cl b/libclc/test/binding/ocl/vloadn_Rdouble4.cl new file mode 100644 index 0000000000000..e96d26212017e --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rdouble4.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_vloadn_Rdouble4(__clc_size_t args_0, + __clc_fp64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rdouble4(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_vloadn_Rdouble4(__clc_size_t args_0, + __clc_fp64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rdouble4(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_vloadn_Rdouble4(__clc_size_t args_0, + __clc_fp64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rdouble4(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_vloadn_Rdouble4(__clc_size_t args_0, + __clc_fp64_t const *args_1) { + return __spirv_ocl_vloadn_Rdouble4(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloadn_Rdouble8.cl b/libclc/test/binding/ocl/vloadn_Rdouble8.cl new file mode 100644 index 0000000000000..4b11bf4341ae9 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rdouble8.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_vloadn_Rdouble8(__clc_size_t args_0, + __clc_fp64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rdouble8(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_vloadn_Rdouble8(__clc_size_t args_0, + __clc_fp64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rdouble8(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_vloadn_Rdouble8(__clc_size_t args_0, + __clc_fp64_t const *args_1) { + return __spirv_ocl_vloadn_Rdouble8(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_vloadn_Rdouble8(__clc_size_t args_0, + __clc_fp64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rdouble8(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloadn_Rfloat16.cl b/libclc/test/binding/ocl/vloadn_Rfloat16.cl new file mode 100644 index 0000000000000..40d1b35dbeeb3 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rfloat16.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_vloadn_Rfloat16(__clc_size_t args_0, + __clc_fp32_t const __global *args_1) { + return __spirv_ocl_vloadn_Rfloat16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_vloadn_Rfloat16(__clc_size_t args_0, + __clc_fp32_t const __local *args_1) { + return __spirv_ocl_vloadn_Rfloat16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_vloadn_Rfloat16(__clc_size_t args_0, + __clc_fp32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rfloat16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_vloadn_Rfloat16(__clc_size_t args_0, + __clc_fp32_t const *args_1) { + return __spirv_ocl_vloadn_Rfloat16(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rfloat2.cl b/libclc/test/binding/ocl/vloadn_Rfloat2.cl new file mode 100644 index 0000000000000..0d6a3edcbb5b3 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rfloat2.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_vloadn_Rfloat2(__clc_size_t args_0, + __clc_fp32_t const __global *args_1) { + return __spirv_ocl_vloadn_Rfloat2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_vloadn_Rfloat2(__clc_size_t args_0, + __clc_fp32_t const __local *args_1) { + return __spirv_ocl_vloadn_Rfloat2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_vloadn_Rfloat2(__clc_size_t args_0, + __clc_fp32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rfloat2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_vloadn_Rfloat2(__clc_size_t args_0, + __clc_fp32_t const *args_1) { + return __spirv_ocl_vloadn_Rfloat2(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rfloat3.cl b/libclc/test/binding/ocl/vloadn_Rfloat3.cl new file mode 100644 index 0000000000000..b6f24c83beb28 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rfloat3.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_vloadn_Rfloat3(__clc_size_t args_0, + __clc_fp32_t const __global *args_1) { + return __spirv_ocl_vloadn_Rfloat3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_vloadn_Rfloat3(__clc_size_t args_0, + __clc_fp32_t const __local *args_1) { + return __spirv_ocl_vloadn_Rfloat3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_vloadn_Rfloat3(__clc_size_t args_0, + __clc_fp32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rfloat3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_vloadn_Rfloat3(__clc_size_t args_0, + __clc_fp32_t const *args_1) { + return __spirv_ocl_vloadn_Rfloat3(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rfloat4.cl b/libclc/test/binding/ocl/vloadn_Rfloat4.cl new file mode 100644 index 0000000000000..bec9eb5c07e73 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rfloat4.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_vloadn_Rfloat4(__clc_size_t args_0, + __clc_fp32_t const __global *args_1) { + return __spirv_ocl_vloadn_Rfloat4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_vloadn_Rfloat4(__clc_size_t args_0, + __clc_fp32_t const __local *args_1) { + return __spirv_ocl_vloadn_Rfloat4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_vloadn_Rfloat4(__clc_size_t args_0, + __clc_fp32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rfloat4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_vloadn_Rfloat4(__clc_size_t args_0, + __clc_fp32_t const *args_1) { + return __spirv_ocl_vloadn_Rfloat4(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rfloat8.cl b/libclc/test/binding/ocl/vloadn_Rfloat8.cl new file mode 100644 index 0000000000000..d0c628af2214b --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rfloat8.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_vloadn_Rfloat8(__clc_size_t args_0, + __clc_fp32_t const __local *args_1) { + return __spirv_ocl_vloadn_Rfloat8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_vloadn_Rfloat8(__clc_size_t args_0, + __clc_fp32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rfloat8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_vloadn_Rfloat8(__clc_size_t args_0, + __clc_fp32_t const *args_1) { + return __spirv_ocl_vloadn_Rfloat8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_vloadn_Rfloat8(__clc_size_t args_0, + __clc_fp32_t const __global *args_1) { + return __spirv_ocl_vloadn_Rfloat8(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rhalf16.cl b/libclc/test/binding/ocl/vloadn_Rhalf16.cl new file mode 100644 index 0000000000000..2144975b239ad --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rhalf16.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_vloadn_Rhalf16(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rhalf16(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_vloadn_Rhalf16(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rhalf16(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_vloadn_Rhalf16(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rhalf16(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_vloadn_Rhalf16(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vloadn_Rhalf16(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloadn_Rhalf2.cl b/libclc/test/binding/ocl/vloadn_Rhalf2.cl new file mode 100644 index 0000000000000..332f062a88f23 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rhalf2.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_vloadn_Rhalf2(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rhalf2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_vloadn_Rhalf2(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rhalf2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_vloadn_Rhalf2(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rhalf2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_vloadn_Rhalf2(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vloadn_Rhalf2(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloadn_Rhalf3.cl b/libclc/test/binding/ocl/vloadn_Rhalf3.cl new file mode 100644 index 0000000000000..cbf0f3dbfe1ee --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rhalf3.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_vloadn_Rhalf3(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rhalf3(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_vloadn_Rhalf3(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rhalf3(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_vloadn_Rhalf3(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rhalf3(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_vloadn_Rhalf3(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vloadn_Rhalf3(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloadn_Rhalf4.cl b/libclc/test/binding/ocl/vloadn_Rhalf4.cl new file mode 100644 index 0000000000000..6cb20be089d0e --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rhalf4.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_vloadn_Rhalf4(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rhalf4(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_vloadn_Rhalf4(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rhalf4(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_vloadn_Rhalf4(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rhalf4(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_vloadn_Rhalf4(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vloadn_Rhalf4(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloadn_Rhalf8.cl b/libclc/test/binding/ocl/vloadn_Rhalf8.cl new file mode 100644 index 0000000000000..d309241dcba19 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rhalf8.cl @@ -0,0 +1,49 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_vloadn_Rhalf8(__clc_size_t args_0, + __clc_fp16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rhalf8(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_vloadn_Rhalf8(__clc_size_t args_0, + __clc_fp16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rhalf8(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_vloadn_Rhalf8(__clc_size_t args_0, + __clc_fp16_t const *args_1) { + return __spirv_ocl_vloadn_Rhalf8(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_vloadn_Rhalf8(__clc_size_t args_0, + __clc_fp16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rhalf8(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/vloadn_Rint16.cl b/libclc/test/binding/ocl/vloadn_Rint16.cl new file mode 100644 index 0000000000000..7d0916e0dbeb4 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rint16.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_vloadn_Rint16(__clc_size_t args_0, + __clc_int32_t const __global *args_1) { + return __spirv_ocl_vloadn_Rint16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_vloadn_Rint16(__clc_size_t args_0, + __clc_int32_t const __local *args_1) { + return __spirv_ocl_vloadn_Rint16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_vloadn_Rint16(__clc_size_t args_0, + __clc_int32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rint16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_vloadn_Rint16(__clc_size_t args_0, + __clc_int32_t const *args_1) { + return __spirv_ocl_vloadn_Rint16(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rint2.cl b/libclc/test/binding/ocl/vloadn_Rint2.cl new file mode 100644 index 0000000000000..ff7c6830f498f --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rint2.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_vloadn_Rint2(__clc_size_t args_0, + __clc_int32_t const __global *args_1) { + return __spirv_ocl_vloadn_Rint2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_vloadn_Rint2(__clc_size_t args_0, + __clc_int32_t const __local *args_1) { + return __spirv_ocl_vloadn_Rint2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_vloadn_Rint2(__clc_size_t args_0, + __clc_int32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rint2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_vloadn_Rint2(__clc_size_t args_0, + __clc_int32_t const *args_1) { + return __spirv_ocl_vloadn_Rint2(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rint3.cl b/libclc/test/binding/ocl/vloadn_Rint3.cl new file mode 100644 index 0000000000000..c1e35284ef794 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rint3.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_vloadn_Rint3(__clc_size_t args_0, + __clc_int32_t const __global *args_1) { + return __spirv_ocl_vloadn_Rint3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_vloadn_Rint3(__clc_size_t args_0, + __clc_int32_t const __local *args_1) { + return __spirv_ocl_vloadn_Rint3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_vloadn_Rint3(__clc_size_t args_0, + __clc_int32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rint3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_vloadn_Rint3(__clc_size_t args_0, + __clc_int32_t const *args_1) { + return __spirv_ocl_vloadn_Rint3(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rint4.cl b/libclc/test/binding/ocl/vloadn_Rint4.cl new file mode 100644 index 0000000000000..6785a05487c14 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rint4.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_vloadn_Rint4(__clc_size_t args_0, + __clc_int32_t const __global *args_1) { + return __spirv_ocl_vloadn_Rint4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_vloadn_Rint4(__clc_size_t args_0, + __clc_int32_t const __local *args_1) { + return __spirv_ocl_vloadn_Rint4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_vloadn_Rint4(__clc_size_t args_0, + __clc_int32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rint4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_vloadn_Rint4(__clc_size_t args_0, + __clc_int32_t const *args_1) { + return __spirv_ocl_vloadn_Rint4(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rint8.cl b/libclc/test/binding/ocl/vloadn_Rint8.cl new file mode 100644 index 0000000000000..8bd8c40db914c --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rint8.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_vloadn_Rint8(__clc_size_t args_0, + __clc_int32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rint8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_vloadn_Rint8(__clc_size_t args_0, + __clc_int32_t const *args_1) { + return __spirv_ocl_vloadn_Rint8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_vloadn_Rint8(__clc_size_t args_0, + __clc_int32_t const __global *args_1) { + return __spirv_ocl_vloadn_Rint8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_vloadn_Rint8(__clc_size_t args_0, + __clc_int32_t const __local *args_1) { + return __spirv_ocl_vloadn_Rint8(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rlong16.cl b/libclc/test/binding/ocl/vloadn_Rlong16.cl new file mode 100644 index 0000000000000..1d07461d2d987 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rlong16.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_vloadn_Rlong16(__clc_size_t args_0, + __clc_int64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rlong16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_vloadn_Rlong16(__clc_size_t args_0, + __clc_int64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rlong16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_vloadn_Rlong16(__clc_size_t args_0, + __clc_int64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rlong16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_vloadn_Rlong16(__clc_size_t args_0, + __clc_int64_t const *args_1) { + return __spirv_ocl_vloadn_Rlong16(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rlong2.cl b/libclc/test/binding/ocl/vloadn_Rlong2.cl new file mode 100644 index 0000000000000..50ff62d9d048d --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rlong2.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_vloadn_Rlong2(__clc_size_t args_0, + __clc_int64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rlong2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_vloadn_Rlong2(__clc_size_t args_0, + __clc_int64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rlong2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_vloadn_Rlong2(__clc_size_t args_0, + __clc_int64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rlong2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_vloadn_Rlong2(__clc_size_t args_0, + __clc_int64_t const *args_1) { + return __spirv_ocl_vloadn_Rlong2(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rlong3.cl b/libclc/test/binding/ocl/vloadn_Rlong3.cl new file mode 100644 index 0000000000000..da75f66a3e701 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rlong3.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_vloadn_Rlong3(__clc_size_t args_0, + __clc_int64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rlong3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_vloadn_Rlong3(__clc_size_t args_0, + __clc_int64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rlong3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_vloadn_Rlong3(__clc_size_t args_0, + __clc_int64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rlong3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_vloadn_Rlong3(__clc_size_t args_0, + __clc_int64_t const *args_1) { + return __spirv_ocl_vloadn_Rlong3(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rlong4.cl b/libclc/test/binding/ocl/vloadn_Rlong4.cl new file mode 100644 index 0000000000000..dd27e737ee849 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rlong4.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_vloadn_Rlong4(__clc_size_t args_0, + __clc_int64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rlong4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_vloadn_Rlong4(__clc_size_t args_0, + __clc_int64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rlong4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_vloadn_Rlong4(__clc_size_t args_0, + __clc_int64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rlong4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_vloadn_Rlong4(__clc_size_t args_0, + __clc_int64_t const *args_1) { + return __spirv_ocl_vloadn_Rlong4(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rlong8.cl b/libclc/test/binding/ocl/vloadn_Rlong8.cl new file mode 100644 index 0000000000000..618c02f8ff49b --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rlong8.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_vloadn_Rlong8(__clc_size_t args_0, + __clc_int64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rlong8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_vloadn_Rlong8(__clc_size_t args_0, + __clc_int64_t const *args_1) { + return __spirv_ocl_vloadn_Rlong8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_vloadn_Rlong8(__clc_size_t args_0, + __clc_int64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rlong8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_vloadn_Rlong8(__clc_size_t args_0, + __clc_int64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rlong8(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rshort16.cl b/libclc/test/binding/ocl/vloadn_Rshort16.cl new file mode 100644 index 0000000000000..a7a5d19ed45ac --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rshort16.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_vloadn_Rshort16(__clc_size_t args_0, + __clc_int16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rshort16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_vloadn_Rshort16(__clc_size_t args_0, + __clc_int16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rshort16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_vloadn_Rshort16(__clc_size_t args_0, + __clc_int16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rshort16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_vloadn_Rshort16(__clc_size_t args_0, + __clc_int16_t const *args_1) { + return __spirv_ocl_vloadn_Rshort16(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rshort2.cl b/libclc/test/binding/ocl/vloadn_Rshort2.cl new file mode 100644 index 0000000000000..ef2fd456f68c0 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rshort2.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_vloadn_Rshort2(__clc_size_t args_0, + __clc_int16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rshort2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_vloadn_Rshort2(__clc_size_t args_0, + __clc_int16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rshort2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_vloadn_Rshort2(__clc_size_t args_0, + __clc_int16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rshort2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_vloadn_Rshort2(__clc_size_t args_0, + __clc_int16_t const *args_1) { + return __spirv_ocl_vloadn_Rshort2(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rshort3.cl b/libclc/test/binding/ocl/vloadn_Rshort3.cl new file mode 100644 index 0000000000000..839286a98e2c8 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rshort3.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_vloadn_Rshort3(__clc_size_t args_0, + __clc_int16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rshort3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_vloadn_Rshort3(__clc_size_t args_0, + __clc_int16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rshort3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_vloadn_Rshort3(__clc_size_t args_0, + __clc_int16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rshort3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_vloadn_Rshort3(__clc_size_t args_0, + __clc_int16_t const *args_1) { + return __spirv_ocl_vloadn_Rshort3(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rshort4.cl b/libclc/test/binding/ocl/vloadn_Rshort4.cl new file mode 100644 index 0000000000000..adda23573fa62 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rshort4.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_vloadn_Rshort4(__clc_size_t args_0, + __clc_int16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rshort4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_vloadn_Rshort4(__clc_size_t args_0, + __clc_int16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rshort4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_vloadn_Rshort4(__clc_size_t args_0, + __clc_int16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rshort4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_vloadn_Rshort4(__clc_size_t args_0, + __clc_int16_t const *args_1) { + return __spirv_ocl_vloadn_Rshort4(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rshort8.cl b/libclc/test/binding/ocl/vloadn_Rshort8.cl new file mode 100644 index 0000000000000..f904198815a4c --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rshort8.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_vloadn_Rshort8(__clc_size_t args_0, + __clc_int16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rshort8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_vloadn_Rshort8(__clc_size_t args_0, + __clc_int16_t const *args_1) { + return __spirv_ocl_vloadn_Rshort8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_vloadn_Rshort8(__clc_size_t args_0, + __clc_int16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rshort8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_vloadn_Rshort8(__clc_size_t args_0, + __clc_int16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rshort8(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Ruchar16.cl b/libclc/test/binding/ocl/vloadn_Ruchar16.cl new file mode 100644 index 0000000000000..9cfdef5896c72 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Ruchar16.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_vloadn_Ruchar16(__clc_size_t args_0, + __clc_uint8_t const __global *args_1) { + return __spirv_ocl_vloadn_Ruchar16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_vloadn_Ruchar16(__clc_size_t args_0, + __clc_uint8_t const __local *args_1) { + return __spirv_ocl_vloadn_Ruchar16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_vloadn_Ruchar16(__clc_size_t args_0, + __clc_uint8_t const __constant *args_1) { + return __spirv_ocl_vloadn_Ruchar16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_vloadn_Ruchar16(__clc_size_t args_0, + __clc_uint8_t const *args_1) { + return __spirv_ocl_vloadn_Ruchar16(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Ruchar2.cl b/libclc/test/binding/ocl/vloadn_Ruchar2.cl new file mode 100644 index 0000000000000..576bc31d8b9dd --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Ruchar2.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_vloadn_Ruchar2(__clc_size_t args_0, + __clc_uint8_t const __global *args_1) { + return __spirv_ocl_vloadn_Ruchar2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_vloadn_Ruchar2(__clc_size_t args_0, + __clc_uint8_t const __local *args_1) { + return __spirv_ocl_vloadn_Ruchar2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_vloadn_Ruchar2(__clc_size_t args_0, + __clc_uint8_t const __constant *args_1) { + return __spirv_ocl_vloadn_Ruchar2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_vloadn_Ruchar2(__clc_size_t args_0, + __clc_uint8_t const *args_1) { + return __spirv_ocl_vloadn_Ruchar2(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Ruchar3.cl b/libclc/test/binding/ocl/vloadn_Ruchar3.cl new file mode 100644 index 0000000000000..591cedba711c7 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Ruchar3.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_vloadn_Ruchar3(__clc_size_t args_0, + __clc_uint8_t const __global *args_1) { + return __spirv_ocl_vloadn_Ruchar3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_vloadn_Ruchar3(__clc_size_t args_0, + __clc_uint8_t const __local *args_1) { + return __spirv_ocl_vloadn_Ruchar3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_vloadn_Ruchar3(__clc_size_t args_0, + __clc_uint8_t const __constant *args_1) { + return __spirv_ocl_vloadn_Ruchar3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_vloadn_Ruchar3(__clc_size_t args_0, + __clc_uint8_t const *args_1) { + return __spirv_ocl_vloadn_Ruchar3(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Ruchar4.cl b/libclc/test/binding/ocl/vloadn_Ruchar4.cl new file mode 100644 index 0000000000000..bc33821019382 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Ruchar4.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_vloadn_Ruchar4(__clc_size_t args_0, + __clc_uint8_t const __global *args_1) { + return __spirv_ocl_vloadn_Ruchar4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_vloadn_Ruchar4(__clc_size_t args_0, + __clc_uint8_t const __local *args_1) { + return __spirv_ocl_vloadn_Ruchar4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_vloadn_Ruchar4(__clc_size_t args_0, + __clc_uint8_t const __constant *args_1) { + return __spirv_ocl_vloadn_Ruchar4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_vloadn_Ruchar4(__clc_size_t args_0, + __clc_uint8_t const *args_1) { + return __spirv_ocl_vloadn_Ruchar4(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Ruchar8.cl b/libclc/test/binding/ocl/vloadn_Ruchar8.cl new file mode 100644 index 0000000000000..a17ab9455b039 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Ruchar8.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_vloadn_Ruchar8(__clc_size_t args_0, + __clc_uint8_t const __constant *args_1) { + return __spirv_ocl_vloadn_Ruchar8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_vloadn_Ruchar8(__clc_size_t args_0, + __clc_uint8_t const *args_1) { + return __spirv_ocl_vloadn_Ruchar8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_vloadn_Ruchar8(__clc_size_t args_0, + __clc_uint8_t const __global *args_1) { + return __spirv_ocl_vloadn_Ruchar8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_vloadn_Ruchar8(__clc_size_t args_0, + __clc_uint8_t const __local *args_1) { + return __spirv_ocl_vloadn_Ruchar8(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Ruint16.cl b/libclc/test/binding/ocl/vloadn_Ruint16.cl new file mode 100644 index 0000000000000..dab1f055cc3de --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Ruint16.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_vloadn_Ruint16(__clc_size_t args_0, + __clc_uint32_t const __global *args_1) { + return __spirv_ocl_vloadn_Ruint16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_vloadn_Ruint16(__clc_size_t args_0, + __clc_uint32_t const __local *args_1) { + return __spirv_ocl_vloadn_Ruint16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_vloadn_Ruint16(__clc_size_t args_0, + __clc_uint32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Ruint16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_vloadn_Ruint16(__clc_size_t args_0, + __clc_uint32_t const *args_1) { + return __spirv_ocl_vloadn_Ruint16(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Ruint2.cl b/libclc/test/binding/ocl/vloadn_Ruint2.cl new file mode 100644 index 0000000000000..62a42e8bb7710 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Ruint2.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_vloadn_Ruint2(__clc_size_t args_0, + __clc_uint32_t const __global *args_1) { + return __spirv_ocl_vloadn_Ruint2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_vloadn_Ruint2(__clc_size_t args_0, + __clc_uint32_t const __local *args_1) { + return __spirv_ocl_vloadn_Ruint2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_vloadn_Ruint2(__clc_size_t args_0, + __clc_uint32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Ruint2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_vloadn_Ruint2(__clc_size_t args_0, + __clc_uint32_t const *args_1) { + return __spirv_ocl_vloadn_Ruint2(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Ruint3.cl b/libclc/test/binding/ocl/vloadn_Ruint3.cl new file mode 100644 index 0000000000000..c25b855432110 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Ruint3.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_vloadn_Ruint3(__clc_size_t args_0, + __clc_uint32_t const __global *args_1) { + return __spirv_ocl_vloadn_Ruint3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_vloadn_Ruint3(__clc_size_t args_0, + __clc_uint32_t const __local *args_1) { + return __spirv_ocl_vloadn_Ruint3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_vloadn_Ruint3(__clc_size_t args_0, + __clc_uint32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Ruint3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_vloadn_Ruint3(__clc_size_t args_0, + __clc_uint32_t const *args_1) { + return __spirv_ocl_vloadn_Ruint3(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Ruint4.cl b/libclc/test/binding/ocl/vloadn_Ruint4.cl new file mode 100644 index 0000000000000..bfe0c2c18b35c --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Ruint4.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_vloadn_Ruint4(__clc_size_t args_0, + __clc_uint32_t const __global *args_1) { + return __spirv_ocl_vloadn_Ruint4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_vloadn_Ruint4(__clc_size_t args_0, + __clc_uint32_t const __local *args_1) { + return __spirv_ocl_vloadn_Ruint4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_vloadn_Ruint4(__clc_size_t args_0, + __clc_uint32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Ruint4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_vloadn_Ruint4(__clc_size_t args_0, + __clc_uint32_t const *args_1) { + return __spirv_ocl_vloadn_Ruint4(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Ruint8.cl b/libclc/test/binding/ocl/vloadn_Ruint8.cl new file mode 100644 index 0000000000000..a717af10dfbef --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Ruint8.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_vloadn_Ruint8(__clc_size_t args_0, + __clc_uint32_t const __constant *args_1) { + return __spirv_ocl_vloadn_Ruint8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_vloadn_Ruint8(__clc_size_t args_0, + __clc_uint32_t const *args_1) { + return __spirv_ocl_vloadn_Ruint8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_vloadn_Ruint8(__clc_size_t args_0, + __clc_uint32_t const __global *args_1) { + return __spirv_ocl_vloadn_Ruint8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_vloadn_Ruint8(__clc_size_t args_0, + __clc_uint32_t const __local *args_1) { + return __spirv_ocl_vloadn_Ruint8(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rulong16.cl b/libclc/test/binding/ocl/vloadn_Rulong16.cl new file mode 100644 index 0000000000000..13161c2422342 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rulong16.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_vloadn_Rulong16(__clc_size_t args_0, + __clc_uint64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rulong16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_vloadn_Rulong16(__clc_size_t args_0, + __clc_uint64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rulong16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_vloadn_Rulong16(__clc_size_t args_0, + __clc_uint64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rulong16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_vloadn_Rulong16(__clc_size_t args_0, + __clc_uint64_t const *args_1) { + return __spirv_ocl_vloadn_Rulong16(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rulong2.cl b/libclc/test/binding/ocl/vloadn_Rulong2.cl new file mode 100644 index 0000000000000..c0e3ce3d36d64 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rulong2.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_vloadn_Rulong2(__clc_size_t args_0, + __clc_uint64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rulong2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_vloadn_Rulong2(__clc_size_t args_0, + __clc_uint64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rulong2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_vloadn_Rulong2(__clc_size_t args_0, + __clc_uint64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rulong2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_vloadn_Rulong2(__clc_size_t args_0, + __clc_uint64_t const *args_1) { + return __spirv_ocl_vloadn_Rulong2(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rulong3.cl b/libclc/test/binding/ocl/vloadn_Rulong3.cl new file mode 100644 index 0000000000000..9696af075ecf8 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rulong3.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_vloadn_Rulong3(__clc_size_t args_0, + __clc_uint64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rulong3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_vloadn_Rulong3(__clc_size_t args_0, + __clc_uint64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rulong3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_vloadn_Rulong3(__clc_size_t args_0, + __clc_uint64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rulong3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_vloadn_Rulong3(__clc_size_t args_0, + __clc_uint64_t const *args_1) { + return __spirv_ocl_vloadn_Rulong3(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rulong4.cl b/libclc/test/binding/ocl/vloadn_Rulong4.cl new file mode 100644 index 0000000000000..bff4382e872dd --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rulong4.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_vloadn_Rulong4(__clc_size_t args_0, + __clc_uint64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rulong4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_vloadn_Rulong4(__clc_size_t args_0, + __clc_uint64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rulong4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_vloadn_Rulong4(__clc_size_t args_0, + __clc_uint64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rulong4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_vloadn_Rulong4(__clc_size_t args_0, + __clc_uint64_t const *args_1) { + return __spirv_ocl_vloadn_Rulong4(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rulong8.cl b/libclc/test/binding/ocl/vloadn_Rulong8.cl new file mode 100644 index 0000000000000..afe7f1c088831 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rulong8.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_vloadn_Rulong8(__clc_size_t args_0, + __clc_uint64_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rulong8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_vloadn_Rulong8(__clc_size_t args_0, + __clc_uint64_t const *args_1) { + return __spirv_ocl_vloadn_Rulong8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_vloadn_Rulong8(__clc_size_t args_0, + __clc_uint64_t const __global *args_1) { + return __spirv_ocl_vloadn_Rulong8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_vloadn_Rulong8(__clc_size_t args_0, + __clc_uint64_t const __local *args_1) { + return __spirv_ocl_vloadn_Rulong8(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rushort16.cl b/libclc/test/binding/ocl/vloadn_Rushort16.cl new file mode 100644 index 0000000000000..a90f18047c1b8 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rushort16.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_vloadn_Rushort16(__clc_size_t args_0, + __clc_uint16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rushort16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_vloadn_Rushort16(__clc_size_t args_0, + __clc_uint16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rushort16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_vloadn_Rushort16(__clc_size_t args_0, + __clc_uint16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rushort16(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_vloadn_Rushort16(__clc_size_t args_0, + __clc_uint16_t const *args_1) { + return __spirv_ocl_vloadn_Rushort16(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rushort2.cl b/libclc/test/binding/ocl/vloadn_Rushort2.cl new file mode 100644 index 0000000000000..e411dc1007551 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rushort2.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_vloadn_Rushort2(__clc_size_t args_0, + __clc_uint16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rushort2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_vloadn_Rushort2(__clc_size_t args_0, + __clc_uint16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rushort2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_vloadn_Rushort2(__clc_size_t args_0, + __clc_uint16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rushort2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_vloadn_Rushort2(__clc_size_t args_0, + __clc_uint16_t const *args_1) { + return __spirv_ocl_vloadn_Rushort2(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rushort3.cl b/libclc/test/binding/ocl/vloadn_Rushort3.cl new file mode 100644 index 0000000000000..8e46cac14aeb2 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rushort3.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_vloadn_Rushort3(__clc_size_t args_0, + __clc_uint16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rushort3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_vloadn_Rushort3(__clc_size_t args_0, + __clc_uint16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rushort3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_vloadn_Rushort3(__clc_size_t args_0, + __clc_uint16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rushort3(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_vloadn_Rushort3(__clc_size_t args_0, + __clc_uint16_t const *args_1) { + return __spirv_ocl_vloadn_Rushort3(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rushort4.cl b/libclc/test/binding/ocl/vloadn_Rushort4.cl new file mode 100644 index 0000000000000..db263ae414254 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rushort4.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_vloadn_Rushort4(__clc_size_t args_0, + __clc_uint16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rushort4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_vloadn_Rushort4(__clc_size_t args_0, + __clc_uint16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rushort4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_vloadn_Rushort4(__clc_size_t args_0, + __clc_uint16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rushort4(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_vloadn_Rushort4(__clc_size_t args_0, + __clc_uint16_t const *args_1) { + return __spirv_ocl_vloadn_Rushort4(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vloadn_Rushort8.cl b/libclc/test/binding/ocl/vloadn_Rushort8.cl new file mode 100644 index 0000000000000..a9b3bca0d3543 --- /dev/null +++ b/libclc/test/binding/ocl/vloadn_Rushort8.cl @@ -0,0 +1,40 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_vloadn_Rushort8(__clc_size_t args_0, + __clc_uint16_t const __constant *args_1) { + return __spirv_ocl_vloadn_Rushort8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_vloadn_Rushort8(__clc_size_t args_0, + __clc_uint16_t const *args_1) { + return __spirv_ocl_vloadn_Rushort8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_vloadn_Rushort8(__clc_size_t args_0, + __clc_uint16_t const __global *args_1) { + return __spirv_ocl_vloadn_Rushort8(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_vloadn_Rushort8(__clc_size_t args_0, + __clc_uint16_t const __local *args_1) { + return __spirv_ocl_vloadn_Rushort8(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/vstore_half.cl b/libclc/test/binding/ocl/vstore_half.cl new file mode 100644 index 0000000000000..93f8f29ad93a7 --- /dev/null +++ b/libclc/test/binding/ocl/vstore_half.cl @@ -0,0 +1,71 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_half(__clc_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstore_half(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_half(__clc_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstore_half(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_half(__clc_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstore_half(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_half(__clc_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstore_half(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_half(__clc_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstore_half(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_half(__clc_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstore_half(args_0, args_1, args_2); +} + +#endif +#endif diff --git a/libclc/test/binding/ocl/vstore_half_r.cl b/libclc/test/binding/ocl/vstore_half_r.cl new file mode 100644 index 0000000000000..dbeaeef6cf92d --- /dev/null +++ b/libclc/test/binding/ocl/vstore_half_r.cl @@ -0,0 +1,75 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_half_r(__clc_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_half_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_half_r(__clc_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_half_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_half_r(__clc_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_half_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_half_r(__clc_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_half_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_half_r(__clc_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstore_half_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_half_r(__clc_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstore_half_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif diff --git a/libclc/test/binding/ocl/vstore_halfn.cl b/libclc/test/binding/ocl/vstore_halfn.cl new file mode 100644 index 0000000000000..36c3f9c385f26 --- /dev/null +++ b/libclc/test/binding/ocl/vstore_halfn.cl @@ -0,0 +1,287 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstore_halfn(args_0, args_1, args_2); +} + +#endif +#endif diff --git a/libclc/test/binding/ocl/vstore_halfn_r.cl b/libclc/test/binding/ocl/vstore_halfn_r.cl new file mode 100644 index 0000000000000..3d27011cacace --- /dev/null +++ b/libclc/test/binding/ocl/vstore_halfn_r.cl @@ -0,0 +1,307 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstore_halfn_r(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstore_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif diff --git a/libclc/test/binding/ocl/vstorea_halfn.cl b/libclc/test/binding/ocl/vstorea_halfn.cl new file mode 100644 index 0000000000000..b29c072061904 --- /dev/null +++ b/libclc/test/binding/ocl/vstorea_halfn.cl @@ -0,0 +1,287 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstorea_halfn(args_0, args_1, args_2); +} + +#endif +#endif diff --git a/libclc/test/binding/ocl/vstorea_halfn_r.cl b/libclc/test/binding/ocl/vstorea_halfn_r.cl new file mode 100644 index 0000000000000..bf5b79bfa0127 --- /dev/null +++ b/libclc/test/binding/ocl/vstorea_halfn_r.cl @@ -0,0 +1,307 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2, + __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#ifdef cl_khr_fp16 +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstorea_halfn_r(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2, __clc_uint32_t args_3) { + __spirv_ocl_vstorea_halfn_r(args_0, args_1, args_2, args_3); +} + +#endif +#endif diff --git a/libclc/test/binding/ocl/vstoren.cl b/libclc/test/binding/ocl/vstoren.cl new file mode 100644 index 0000000000000..1fbb77269e07e --- /dev/null +++ b/libclc/test/binding/ocl/vstoren.cl @@ -0,0 +1,1067 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_int8_t args_0, __clc_size_t args_1, + __clc_int8_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_int16_t args_0, __clc_size_t args_1, + __clc_int16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_int32_t args_0, __clc_size_t args_1, + __clc_int32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_int64_t args_0, __clc_size_t args_1, + __clc_int64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_int8_t args_0, __clc_size_t args_1, + __clc_int8_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_int16_t args_0, __clc_size_t args_1, + __clc_int16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_int32_t args_0, __clc_size_t args_1, + __clc_int32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_int64_t args_0, __clc_size_t args_1, + __clc_int64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_int8_t args_0, __clc_size_t args_1, + __clc_int8_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_int16_t args_0, __clc_size_t args_1, + __clc_int16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_int32_t args_0, __clc_size_t args_1, + __clc_int32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_int64_t args_0, __clc_size_t args_1, + __clc_int64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec8_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_int8_t args_0, __clc_size_t args_1, + __clc_int8_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_int16_t args_0, __clc_size_t args_1, + __clc_int16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_int32_t args_0, __clc_size_t args_1, + __clc_int32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_int64_t args_0, __clc_size_t args_1, + __clc_int64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_int8_t args_0, __clc_size_t args_1, + __clc_int8_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_int16_t args_0, __clc_size_t args_1, + __clc_int16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_int32_t args_0, __clc_size_t args_1, + __clc_int32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_int64_t args_0, __clc_size_t args_1, + __clc_int64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_int8_t args_0, __clc_size_t args_1, + __clc_int8_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_int16_t args_0, __clc_size_t args_1, + __clc_int16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_int32_t args_0, __clc_size_t args_1, + __clc_int32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_int64_t args_0, __clc_size_t args_1, + __clc_int64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec16_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_int8_t args_0, __clc_size_t args_1, + __clc_int8_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_int16_t args_0, __clc_size_t args_1, + __clc_int16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_int32_t args_0, __clc_size_t args_1, + __clc_int32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_int64_t args_0, __clc_size_t args_1, + __clc_int64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_int8_t args_0, __clc_size_t args_1, + __clc_int8_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_int16_t args_0, __clc_size_t args_1, + __clc_int16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_int32_t args_0, __clc_size_t args_1, + __clc_int32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_int64_t args_0, __clc_size_t args_1, + __clc_int64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_int8_t args_0, __clc_size_t args_1, + __clc_int8_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_int16_t args_0, __clc_size_t args_1, + __clc_int16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_int32_t args_0, __clc_size_t args_1, + __clc_int32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_int64_t args_0, __clc_size_t args_1, + __clc_int64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec2_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_int8_t args_0, __clc_size_t args_1, + __clc_int8_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_int16_t args_0, __clc_size_t args_1, + __clc_int16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_int32_t args_0, __clc_size_t args_1, + __clc_int32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_int64_t args_0, __clc_size_t args_1, + __clc_int64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_int8_t args_0, __clc_size_t args_1, + __clc_int8_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_int16_t args_0, __clc_size_t args_1, + __clc_int16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_int32_t args_0, __clc_size_t args_1, + __clc_int32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_int64_t args_0, __clc_size_t args_1, + __clc_int64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_int8_t args_0, __clc_size_t args_1, + __clc_int8_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_int16_t args_0, __clc_size_t args_1, + __clc_int16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_int32_t args_0, __clc_size_t args_1, + __clc_int32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_int64_t args_0, __clc_size_t args_1, + __clc_int64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec3_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_int8_t args_0, __clc_size_t args_1, + __clc_int8_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_int16_t args_0, __clc_size_t args_1, + __clc_int16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_int32_t args_0, __clc_size_t args_1, + __clc_int32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_int64_t args_0, __clc_size_t args_1, + __clc_int64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t __global *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_int8_t args_0, __clc_size_t args_1, + __clc_int8_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_int16_t args_0, __clc_size_t args_1, + __clc_int16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_int32_t args_0, __clc_size_t args_1, + __clc_int32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_int64_t args_0, __clc_size_t args_1, + __clc_int64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t __local *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_int8_t args_0, __clc_size_t args_1, + __clc_int8_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_uint8_t args_0, __clc_size_t args_1, + __clc_uint8_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_int16_t args_0, __clc_size_t args_1, + __clc_int16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_uint16_t args_0, __clc_size_t args_1, + __clc_uint16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_int32_t args_0, __clc_size_t args_1, + __clc_int32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_uint32_t args_0, __clc_size_t args_1, + __clc_uint32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_int64_t args_0, __clc_size_t args_1, + __clc_int64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_uint64_t args_0, __clc_size_t args_1, + __clc_uint64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_fp32_t args_0, __clc_size_t args_1, + __clc_fp32_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_fp64_t args_0, __clc_size_t args_1, + __clc_fp64_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) void +test___spirv_ocl_vstoren(__clc_vec4_fp16_t args_0, __clc_size_t args_1, + __clc_fp16_t *args_2) { + __spirv_ocl_vstoren(args_0, args_1, args_2); +} + +#endif diff --git a/libclc/utils/gen-libclc-test.py b/libclc/utils/gen-libclc-test.py index 0a9d51dea6608..3bf5e5c2186b3 100755 --- a/libclc/utils/gen-libclc-test.py +++ b/libclc/utils/gen-libclc-test.py @@ -13,11 +13,30 @@ def ignore_function(fun): whitelist = [ + "abs", + "abs_diff", + "add_sat", + "BitCount", + "clz", "ControlBarrier", + "ctz", "GroupAsyncCopy", "GroupWaitEvents", + "hadd", + "mad24", + "mad_hi", + "mad_sat", "MemoryBarrier", - "prefetch" + "mul24", + "mul_hi", + "popcount", + "prefetch", + "rhadd", + "rotate", + "sub_sat", + "upsample", + "vload", + "vstore" ] return not any([fun.find(b) != -1 for b in whitelist]) diff --git a/sycl/test/built-ins/scalar_integer.cpp b/sycl/test/built-ins/scalar_integer.cpp index bb3b7fc416d02..18dd76294022a 100644 --- a/sycl/test/built-ins/scalar_integer.cpp +++ b/sycl/test/built-ins/scalar_integer.cpp @@ -4,9 +4,6 @@ // RUN: %GPU_RUN_PLACEHOLDER %t.out // RUN: %ACC_RUN_PLACEHOLDER %t.out -// TODO: ptxas fatal : Unresolved extern function '_Z17__spirv_ocl_s_maxii' -// XFAIL: cuda - #include #include diff --git a/sycl/test/built-ins/vector_integer.cpp b/sycl/test/built-ins/vector_integer.cpp index c5b13f447a959..5a3a3dd0c80cf 100644 --- a/sycl/test/built-ins/vector_integer.cpp +++ b/sycl/test/built-ins/vector_integer.cpp @@ -4,9 +4,6 @@ // RUN: %GPU_RUN_PLACEHOLDER %t.out // RUN: %ACC_RUN_PLACEHOLDER %t.out -// TODO: ptxas fatal : Unresolved extern function '_Z17__spirv_ocl_s_maxDv2_iS_' -// XFAIL: cuda - #include #include