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| 1 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | +/* |
| 3 | + * Copyright (c) 2024 Rockchip Electronics Co., Ltd. |
| 4 | + * |
| 5 | + */ |
| 6 | + |
| 7 | +/ { |
| 8 | + rk628f_dc: rk628f-dc { |
| 9 | + compatible = "rockchip,dummy-codec"; |
| 10 | + #sound-dai-cells = <0>; |
| 11 | + }; |
| 12 | + |
| 13 | + rkvtunnel: rkvtunnel { |
| 14 | + compatible = "rockchip,video-tunnel"; |
| 15 | + status = "okay"; |
| 16 | + }; |
| 17 | + |
| 18 | + hdmiin-sound { |
| 19 | + compatible = "simple-audio-card"; |
| 20 | + simple-audio-card,format = "i2s"; |
| 21 | + simple-audio-card,name = "rockchip,hdmiin"; |
| 22 | + simple-audio-card,bitclock-master = <&dailink0_master>; |
| 23 | + simple-audio-card,frame-master = <&dailink0_master>; |
| 24 | + status = "okay"; |
| 25 | + simple-audio-card,cpu { |
| 26 | + sound-dai = <&sai4>; |
| 27 | + }; |
| 28 | + dailink0_master: simple-audio-card,codec { |
| 29 | + sound-dai = <&rk628f_dc>; |
| 30 | + }; |
| 31 | + }; |
| 32 | + |
| 33 | + //vcc_mipicsi1: vcc-mipicsi1-regulator { |
| 34 | + // compatible = "regulator-fixed"; |
| 35 | + // gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; |
| 36 | + // pinctrl-names = "default"; |
| 37 | + // pinctrl-0 = <&mipicsi1_pwr>; |
| 38 | + // regulator-name = "vcc_mipicsi1"; |
| 39 | + // enable-active-high; |
| 40 | + //}; |
| 41 | +}; |
| 42 | + |
| 43 | +&csi2_dphy0 { |
| 44 | + status = "okay"; |
| 45 | + |
| 46 | + ports { |
| 47 | + #address-cells = <1>; |
| 48 | + #size-cells = <0>; |
| 49 | + port@0 { |
| 50 | + reg = <0>; |
| 51 | + #address-cells = <1>; |
| 52 | + #size-cells = <0>; |
| 53 | + |
| 54 | + hdmi_mipi_in: endpoint@1 { |
| 55 | + reg = <1>; |
| 56 | + remote-endpoint = <&hdmiin_out>; |
| 57 | + data-lanes = <1 2 3 4>; |
| 58 | + }; |
| 59 | + }; |
| 60 | + port@1 { |
| 61 | + reg = <1>; |
| 62 | + #address-cells = <1>; |
| 63 | + #size-cells = <0>; |
| 64 | + |
| 65 | + csidphy0_out: endpoint@0 { |
| 66 | + reg = <0>; |
| 67 | + remote-endpoint = <&mipi1_csi2_input>; |
| 68 | + }; |
| 69 | + }; |
| 70 | + }; |
| 71 | +}; |
| 72 | + |
| 73 | +&csi2_dphy0_hw { |
| 74 | + status = "okay"; |
| 75 | +}; |
| 76 | + |
| 77 | +&csi2_dphy1_hw { |
| 78 | + status = "okay"; |
| 79 | +}; |
| 80 | + |
| 81 | +&i2c5 { |
| 82 | + status = "okay"; |
| 83 | + pinctrl-0 = <&i2c5m3_xfer>; |
| 84 | + clock-frequency = <100000>; |
| 85 | + //clock-frequency = <400000>; |
| 86 | + |
| 87 | + rk628_csi: rk628_csi@51 { |
| 88 | + reg = <0x51>; |
| 89 | + compatible = "rockchip,rk628-csi-v4l2"; |
| 90 | + status = "okay"; |
| 91 | + //clocks = <&cru REF_CLK0_OUT_PLL>; |
| 92 | + //clock-names = "xvclk"; |
| 93 | + pinctrl-names = "default"; |
| 94 | + //pinctrl-0 = <&rk628_hdmiin_pin &ref_clk0_clk0>; |
| 95 | + pinctrl-0 = <&rk628_hdmiin_pin>; |
| 96 | + power-domains = <&power RK3576_PD_VI>; |
| 97 | + interrupt-parent = <&gpio4>; |
| 98 | + interrupts = <RK_PA0 IRQ_TYPE_EDGE_RISING>; |
| 99 | + enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; |
| 100 | + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; |
| 101 | + plugin-det-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; |
| 102 | + continues-clk = <1>; |
| 103 | + |
| 104 | + rockchip,camera-module-index = <0>; |
| 105 | + rockchip,camera-module-facing = "back"; |
| 106 | + rockchip,camera-module-name = "HDMI-MIPI1"; |
| 107 | + rockchip,camera-module-lens-name = "RK628-CSI"; |
| 108 | + |
| 109 | + multi-dev-info { |
| 110 | + dev-idx-l = <1>; |
| 111 | + dev-idx-r = <3>; |
| 112 | + combine-idx = <1>; |
| 113 | + pixel-offset = <0>; |
| 114 | + dev-num = <2>; |
| 115 | + }; |
| 116 | + |
| 117 | + port { |
| 118 | + hdmiin_out: endpoint { |
| 119 | + remote-endpoint = <&hdmi_mipi_in>; |
| 120 | + data-lanes = <1 2 3 4>; |
| 121 | + }; |
| 122 | + }; |
| 123 | + }; |
| 124 | +}; |
| 125 | + |
| 126 | +&mipi1_csi2 { |
| 127 | + status = "okay"; |
| 128 | + |
| 129 | + ports { |
| 130 | + #address-cells = <1>; |
| 131 | + #size-cells = <0>; |
| 132 | + |
| 133 | + port@0 { |
| 134 | + reg = <0>; |
| 135 | + #address-cells = <1>; |
| 136 | + #size-cells = <0>; |
| 137 | + |
| 138 | + mipi1_csi2_input: endpoint@1 { |
| 139 | + reg = <1>; |
| 140 | + remote-endpoint = <&csidphy0_out>; |
| 141 | + }; |
| 142 | + }; |
| 143 | + |
| 144 | + port@1 { |
| 145 | + reg = <1>; |
| 146 | + #address-cells = <1>; |
| 147 | + #size-cells = <0>; |
| 148 | + |
| 149 | + mipi1_csi2_output: endpoint@0 { |
| 150 | + reg = <0>; |
| 151 | + remote-endpoint = <&cif_mipi_in1>; |
| 152 | + }; |
| 153 | + }; |
| 154 | + }; |
| 155 | +}; |
| 156 | + |
| 157 | +&rkcif { |
| 158 | + status = "okay"; |
| 159 | +}; |
| 160 | + |
| 161 | +&rkcif_mipi_lvds1 { |
| 162 | + status = "okay"; |
| 163 | + |
| 164 | + port { |
| 165 | + cif_mipi_in1: endpoint { |
| 166 | + remote-endpoint = <&mipi1_csi2_output>; |
| 167 | + }; |
| 168 | + }; |
| 169 | +}; |
| 170 | + |
| 171 | +&rkcif_mmu { |
| 172 | + status = "okay"; |
| 173 | +}; |
| 174 | + |
| 175 | +&sai4 { |
| 176 | + pinctrl-names = "default"; |
| 177 | + pinctrl-0 = <&sai4m0_lrck |
| 178 | + &sai4m0_sclk |
| 179 | + &sai4m0_sdi>; |
| 180 | + status = "okay"; |
| 181 | +}; |
| 182 | + |
| 183 | +&pinctrl { |
| 184 | + hdmiin { |
| 185 | + //mipicsi1_pwr: mipicsi1-pwr { |
| 186 | + // rockchip,pins = |
| 187 | + // /* 628H camera power en */ |
| 188 | + // <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; |
| 189 | + //}; |
| 190 | + |
| 191 | + rk628_hdmiin_pin: rk628-hdmiin-pin { |
| 192 | + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, |
| 193 | + <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, |
| 194 | + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, |
| 195 | + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; |
| 196 | + }; |
| 197 | + }; |
| 198 | +}; |
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