bpf, arm32: Fix JIT bswap32 code on pre-ARMv6

Current JIT includes fall-back code for byte-swapping on older ARM archs,
but fails tests from module test_bpf:

test_bpf: torvalds#299 ALU_END_FROM_BE 64: 0x0123456789abcdef >> 32 -> 0x01234567 jited:1 ret 4530944 != -271733879 (0x452300 != 0xefcdab89)FAIL (1 times)
test_bpf: torvalds#303 ALU_END_FROM_BE 64: 0xfedcba9876543210 >> 32 -> 0xfedcba98 jited:1 ret 12246016 != 271733878 (0xbadc00 != 0x10325476)FAIL (1 times)
test_bpf: torvalds#315 BSWAP 64: 0x0123456789abcdef >> 32 -> 0xefcdab89 jited:1 ret 4530944 != -271733879 (0x452300 != 0xefcdab89)FAIL (1 times)
test_bpf: torvalds#319 BSWAP 64: 0xfedcba9876543210 >> 32 -> 0x10325476 jited:1 ret 12246016 != 271733878 (0xbadc00 != 0x10325476)FAIL (1 times)

These problems can be traced back to emit_rev32(). Rewrite as simpler code,
going from 10 insns to 4 and dropping use of 2 temp registers, while also
fixing the test failures above.

Signed-off-by: Tony Ambardar <[email protected]>

Author: guidosarducci

arch/arm/net/bpf_jit_32.c

@@ -1754,18 +1754,10 @@ static inline void emit_rev32(const u8 rd, const u8 rn, struct jit_ctx *ctx)
 #if __LINUX_ARM_ARCH__ < 6
 	const s8 *tmp2 = bpf2a32[TMP_REG_2];
 
-	emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx);
-	emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 24), ctx);
-	emit(ARM_ORR_SI(ARM_IP, tmp2[0], tmp2[1], SRTYPE_LSL, 24), ctx);
-
-	emit(ARM_MOV_SI(tmp2[1], rn, SRTYPE_LSR, 8), ctx);
-	emit(ARM_AND_I(tmp2[1], tmp2[1], 0xff), ctx);
-	emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 16), ctx);
-	emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx);
-	emit(ARM_MOV_SI(tmp2[0], tmp2[0], SRTYPE_LSL, 8), ctx);
-	emit(ARM_ORR_SI(tmp2[0], tmp2[0], tmp2[1], SRTYPE_LSL, 16), ctx);
-	emit(ARM_ORR_R(rd, ARM_IP, tmp2[0]), ctx);
-
+	emit(ARM_MOV_SI(rd, rn, SRTYPE_ROR, 8), ctx);
+	emit(ARM_EOR_SI(tmp2[1], rn, rn, SRTYPE_ROR, 16), ctx);
+	emit(ARM_BIC_I(tmp2[1], tmp2[1], imm8m(0xff0000)), ctx);
+	emit(ARM_EOR_SI(rd, rd, tmp2[1], SRTYPE_LSR, 8), ctx);
 #else /* ARMv6+ */
 	emit(ARM_REV(rd, rn), ctx);
 #endif