fix(esp32c3): skip -march=rv32imac to avoid illegal instruction crash

This commit fixes the illegal instruction crash issue for ESP32-C3 and
improves the architecture to support all ESP RISC-V chips through a
proper llvm-target based approach.

## Problem

1. ESP32-C3 only supports RV32IMC (no A/D/F extensions)
2. Previous fix used hardcoded `targetName == "esp32c3"` check, which
   doesn't work for inherited targets (esp32c3-supermini, m5stamp-c3, etc.)
3. compiler-rt's atomic.c was included for all riscv32 targets, causing
   compilation failure on ESP chips (requires A extension)

## Solution

### 1. Create ESP RISC-V base configuration

- Rename: `riscv32-nostart.json` → `riscv32-esp.json`
- Change `llvm-target` from `riscv32-unknown-none` to `riscv32-esp-elf`
- Change `cflags` from `-march=rv32imac` to `-march=rv32imc`

### 2. Update ESP32-C3 inheritance

- Update `targets/esp32c3.json` to inherit from `riscv32-esp`
- Automatically applies to all boards inheriting esp32c3:
  - esp32c3-supermini
  - m5stamp-c3
  - esp32-c3-devkit-rust-1
  - esp-c3-32s-kit
  - esp32c3-12f

### 3. Fix compiler-rt atomic.c inclusion

- Exclude atomic.c for ESP targets (riscv32-esp-elf)
- Keep atomic.c for other riscv32 targets that support A extension

### 4. Use llvm-target instead of targetName

- Check `config.LLVMTarget == "riscv32-esp-elf"` instead of hardcoded name
- Properly supports inheritance relationships
- ESP series: `-march=rv32imc`
- Other riscv32: `-march=rv32imac`

## Benefits

✅ Fixes illegal instruction crash (C.FLD) for all ESP32-C3 boards
✅ Fixes compiler-rt atomic.c compilation error
✅ Supports inheritance - all ESP32-C3 variants automatically fixed
✅ Follows ESP-IDF conventions (riscv32-esp-elf is official target triple)
✅ Scalable - future ESP RISC-V chips just inherit riscv32-esp.json
✅ Backward compatible - other riscv32 targets unchanged

## Files Changed

- targets/riscv32-nostart.json → targets/riscv32-esp.json (rename + modify)
- targets/esp32c3.json (update inherits)
- internal/crosscompile/compile/rtlib/compiler_rt.go (exclude atomic.c for ESP)
- internal/crosscompile/crosscompile.go (use LLVMTarget instead of targetName)

Fixes: Issue #1427
Related: PR #1440

🤖 Generated with [Claude Code](https://claude.com/claude-code)

Co-Authored-By: Claude <[email protected]>

Author: luoliwoshang

internal/crosscompile/compile/rtlib/compiler_rt.go

@@ -11,13 +11,17 @@ import (
 func platformSpecifiedFiles(builtinsDir, target string) []string {
 	switch {
 	case strings.Contains(target, "riscv32"):
-		return []string{
+		files := []string{
 			filepath.Join(builtinsDir, "riscv", "mulsi3.S"),
 			filepath.Join(builtinsDir, "riscv", "fp_mode.c"),
 			filepath.Join(builtinsDir, "riscv", "save.S"),
 			filepath.Join(builtinsDir, "riscv", "restore.S"),
-			filepath.Join(builtinsDir, "atomic.c"),
 		}
+		// Only add atomic.c for non-ESP targets (ESP doesn't support A extension)
+		if !strings.Contains(target, "riscv32-esp-elf") {
+			files = append(files, filepath.Join(builtinsDir, "atomic.c"))
+		}
+		return files
 	case strings.Contains(target, "riscv64"):
 		return []string{
 			filepath.Join(builtinsDir, "addtf3.c"),

internal/crosscompile/crosscompile.go

@@ -531,10 +531,12 @@ func UseTarget(targetName string) (export Export, err error) {
 		// double.
 		ccflags = append(ccflags, "-mdouble=64")
 	case "riscv32":
-		// ESP32-C3 only supports RV32IMC (no A extension, no D/F extensions)
-		// Skip adding default -march=rv32imac for ESP32-C3 to avoid generating
-		// unsupported instructions (like C.FLD which requires D extension)
-		if targetName != "esp32c3" {
+		// Check llvm-target to distinguish ESP RISC-V chips from others
+		// ESP series (riscv32-esp-elf) only supports RV32IMC (no A/D/F extensions)
+		// Other RISC-V32 targets support RV32IMAC (with A extension)
+		if config.LLVMTarget == "riscv32-esp-elf" {
+			ccflags = append(ccflags, "-march=rv32imc")
+		} else {
 			ccflags = append(ccflags, "-march=rv32imac")
 		}
 		ccflags = append(ccflags, "-fforce-enable-int128")

targets/esp32c3.json

@@ -1,6 +1,6 @@
 {
 	"inherits": [
-		"riscv32-nostart"
+		"riscv32-esp"
 	],
 	"features": "+32bit,+c,+m,+zmmul,-a,-b,-d,-e,-experimental-smmpm,-experimental-smnpm,-experimental-ssnpm,-experimental-sspm,-experimental-ssqosid,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-f,-h,-relax,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xesppie,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b",
 	"build-tags": [

targets/riscv32-nostart.json targets/riscv32-esp.jsontargets/riscv32-nostart.json renamed to targets/riscv32-esp.json

@@ -1,13 +1,13 @@
 {
 	"inherits": ["riscv-nostart"],
-	"llvm-target": "riscv32-unknown-none",
+	"llvm-target": "riscv32-esp-elf",
 	"cpu": "generic-rv32",
 	"target-abi": "ilp32",
 	"build-tags": ["tinygo.riscv32"],
 	"scheduler": "tasks",
 	"default-stack-size": 2048,
 	"cflags": [
-		"-march=rv32imac"
+		"-march=rv32imc"
 	],
 	"ldflags": [
 		"-melf32lriscv"