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Description
The ESR 0x96004010 was generated by an Arm system that supports FEAT_PFAR. When plugging this into the decoder it returns Invalid ESR, res0 is 0x1
Based on the docs the encoding is
- EC = 0x25 (Data abort)
- IL = 1 (32-bit instruction)
- ISS
- ISV = 0 (No valid instruction syndrome. ISS[23:14] are RES0.)
- DFSC = 0b010000 (Synchronous external abort)
- ISS[14] = 0b1
Since ISV == 0 but ISS[14] is non-zero, the decoder raises an error expecting all the bits to be 0.
However, the docs provide an alternate encoding for bit 14
When FEAT_PFAR is implemented and (DFSC == 0b010000, or DFSC IN {0b01001x}, or DFSC IN {0b0101xx}):
PFV, bit [14]
PFV Meaning
0b0
PFAR_EL1 is UNKNOWN.
0b1
PFAR_EL1 is valid.
There are also a handful of other cases where ISV == 0 that aren't currently handled
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