From a8ed82ebef1f7b0b514b9f9548dc8b88856b2ccf Mon Sep 17 00:00:00 2001 From: Jan Kotas Date: Sun, 28 Aug 2022 15:42:24 -0700 Subject: [PATCH 1/5] Fix use of uninitialized memory for Vector3 constants --- src/coreclr/jit/codegenarm64.cpp | 4 ++++ src/coreclr/jit/codegenxarch.cpp | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 6850014a1d710a..0f9fbab0735e19 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -2413,6 +2413,10 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre regNumber addrReg = tree->GetSingleTempReg(); simd16_t constValue = vecCon->gtSimd16Val; + + if (tree->TypeGet() == TYP_SIMD12) + constValue.u32[3] = 0; + CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue); emit->emitIns_R_C(INS_ldr, attr, targetReg, addrReg, hnd, 0); diff --git a/src/coreclr/jit/codegenxarch.cpp b/src/coreclr/jit/codegenxarch.cpp index d5bbe76dc1e528..22928fbdc2908b 100644 --- a/src/coreclr/jit/codegenxarch.cpp +++ b/src/coreclr/jit/codegenxarch.cpp @@ -562,6 +562,10 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre case TYP_SIMD16: { simd16_t constValue = vecCon->gtSimd16Val; + + if (tree->TypeGet() == TYP_SIMD12) + constValue.u32[3] = 0; + CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue); emit->emitIns_R_C(ins_Load(targetType), attr, targetReg, hnd, 0); From 9836fa337621062b5282bb9ef5b9e6c0c005c6e6 Mon Sep 17 00:00:00 2001 From: Jan Kotas Date: Tue, 30 Aug 2022 22:30:37 -0700 Subject: [PATCH 2/5] Formatting --- src/coreclr/jit/codegenarm64.cpp | 4 ++-- src/coreclr/jit/codegenxarch.cpp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 0f9fbab0735e19..07cceed23595ca 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -2412,12 +2412,12 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre // Get a temp integer register to compute long address. regNumber addrReg = tree->GetSingleTempReg(); - simd16_t constValue = vecCon->gtSimd16Val; + simd16_t constValue = vecCon->gtSimd16Val; if (tree->TypeGet() == TYP_SIMD12) constValue.u32[3] = 0; - CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue); + CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue); emit->emitIns_R_C(INS_ldr, attr, targetReg, addrReg, hnd, 0); } diff --git a/src/coreclr/jit/codegenxarch.cpp b/src/coreclr/jit/codegenxarch.cpp index 22928fbdc2908b..421994a31a2b1a 100644 --- a/src/coreclr/jit/codegenxarch.cpp +++ b/src/coreclr/jit/codegenxarch.cpp @@ -561,12 +561,12 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre case TYP_SIMD12: case TYP_SIMD16: { - simd16_t constValue = vecCon->gtSimd16Val; + simd16_t constValue = vecCon->gtSimd16Val; if (tree->TypeGet() == TYP_SIMD12) constValue.u32[3] = 0; - CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue); + CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue); emit->emitIns_R_C(ins_Load(targetType), attr, targetReg, hnd, 0); break; From 136b27de33eee4072b236cf81186b240a816019a Mon Sep 17 00:00:00 2001 From: Jan Kotas Date: Wed, 31 Aug 2022 07:21:46 -0700 Subject: [PATCH 3/5] Update src/coreclr/jit/codegenarm64.cpp Co-authored-by: Jakob Botsch Nielsen --- src/coreclr/jit/codegenarm64.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 07cceed23595ca..40d6e7cbbadbdf 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -2412,10 +2412,12 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre // Get a temp integer register to compute long address. regNumber addrReg = tree->GetSingleTempReg(); - simd16_t constValue = vecCon->gtSimd16Val; + simd16_t constValue = {}; - if (tree->TypeGet() == TYP_SIMD12) - constValue.u32[3] = 0; + if (vecCon->TypeIs(TYP_SIMD12)) + memcpy(&constValue, &vecCon->gtSimd12Val, sizeof(simd12_t)); + else + constValue = vecCon->gtSimd16Val; CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue); From 3b225cd986b48349a15ead51f2c292210b22396c Mon Sep 17 00:00:00 2001 From: Jan Kotas Date: Wed, 31 Aug 2022 07:24:17 -0700 Subject: [PATCH 4/5] Apply the same fix for x64 --- src/coreclr/jit/codegenxarch.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/coreclr/jit/codegenxarch.cpp b/src/coreclr/jit/codegenxarch.cpp index 421994a31a2b1a..6cfe068be76b68 100644 --- a/src/coreclr/jit/codegenxarch.cpp +++ b/src/coreclr/jit/codegenxarch.cpp @@ -561,10 +561,12 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre case TYP_SIMD12: case TYP_SIMD16: { - simd16_t constValue = vecCon->gtSimd16Val; + simd16_t constValue = {}; - if (tree->TypeGet() == TYP_SIMD12) - constValue.u32[3] = 0; + if (vecCon->TypeIs(TYP_SIMD12)) + memcpy(&constValue, &vecCon->gtSimd12Val, sizeof(simd12_t)); + else + constValue = vecCon->gtSimd16Val; CORINFO_FIELD_HANDLE hnd = emit->emitSimd16Const(constValue); From a894efa7406b53afd70f83721f11fae7f3326eab Mon Sep 17 00:00:00 2001 From: Jan Kotas Date: Wed, 31 Aug 2022 07:43:26 -0700 Subject: [PATCH 5/5] PR feedback --- src/coreclr/jit/instr.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/coreclr/jit/instr.cpp b/src/coreclr/jit/instr.cpp index 6d9494e59b541b..572a556c0858d6 100644 --- a/src/coreclr/jit/instr.cpp +++ b/src/coreclr/jit/instr.cpp @@ -765,7 +765,13 @@ CodeGen::OperandDesc CodeGen::genOperandDesc(GenTree* op) case TYP_SIMD12: case TYP_SIMD16: { - simd16_t constValue = op->AsVecCon()->gtSimd16Val; + simd16_t constValue = {}; + + if (op->TypeIs(TYP_SIMD12)) + memcpy(&constValue, &op->AsVecCon()->gtSimd12Val, sizeof(simd12_t)); + else + constValue = op->AsVecCon()->gtSimd16Val; + return OperandDesc(emit->emitSimd16Const(constValue)); }