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TamarChristinaArmTamarChristinaArm
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Arm64: Implement shift and insert intrinsics (#36818)
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-8
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48 files changed

+18957
-8
lines changed

‎src/coreclr/src/jit/hwintrinsic.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@ enum HWIntrinsicFlag : unsigned int
104104
HW_Flag_NoRMWSemantics = 0x4000,
105105

106106
// NoContainment
107-
// the intrinsic cannot be handled by comtainment,
107+
// the intrinsic cannot be handled by containment,
108108
// all the intrinsic that have explicit memory load/store semantics should have this flag
109109
HW_Flag_NoContainment = 0x8000,
110110

‎src/coreclr/src/jit/hwintrinsicarm64.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -218,6 +218,8 @@ void HWIntrinsicInfo::lookupImmBounds(
218218
break;
219219

220220
case NI_AdvSimd_ShiftLeftLogical:
221+
case NI_AdvSimd_ShiftLeftLogicalAndInsert:
222+
case NI_AdvSimd_ShiftLeftLogicalAndInsertScalar:
221223
case NI_AdvSimd_ShiftLeftLogicalSaturate:
222224
case NI_AdvSimd_ShiftLeftLogicalSaturateScalar:
223225
case NI_AdvSimd_ShiftLeftLogicalSaturateUnsigned:
@@ -231,6 +233,7 @@ void HWIntrinsicInfo::lookupImmBounds(
231233
immUpperBound = BITS_PER_BYTE * genTypeSize(baseType) - 1;
232234
break;
233235

236+
case NI_AdvSimd_ShiftRightAndInsert:
234237
case NI_AdvSimd_ShiftRightArithmetic:
235238
case NI_AdvSimd_ShiftRightArithmeticAdd:
236239
case NI_AdvSimd_ShiftRightArithmeticAddScalar:
@@ -250,6 +253,7 @@ void HWIntrinsicInfo::lookupImmBounds(
250253
case NI_AdvSimd_ShiftRightLogical:
251254
case NI_AdvSimd_ShiftRightLogicalAdd:
252255
case NI_AdvSimd_ShiftRightLogicalAddScalar:
256+
case NI_AdvSimd_ShiftRightLogicalAndInsertScalar:
253257
case NI_AdvSimd_ShiftRightLogicalNarrowingLower:
254258
case NI_AdvSimd_ShiftRightLogicalNarrowingSaturateLower:
255259
case NI_AdvSimd_ShiftRightLogicalNarrowingSaturateUpper:

‎src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -333,6 +333,14 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
333333
}
334334
break;
335335

336+
case NI_AdvSimd_ShiftLeftLogicalAndInsertScalar:
337+
ins = INS_sli;
338+
break;
339+
340+
case NI_AdvSimd_ShiftRightLogicalAndInsertScalar:
341+
ins = INS_sri;
342+
break;
343+
336344
case NI_AdvSimd_SubtractWideningLower:
337345
assert(varTypeIsIntegral(intrin.baseType));
338346
if (intrin.op1->TypeGet() == TYP_SIMD8)
@@ -716,9 +724,11 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
716724
}
717725
break;
718726

727+
case NI_AdvSimd_ShiftLeftLogicalAndInsertScalar:
719728
case NI_AdvSimd_ShiftRightArithmeticAddScalar:
720729
case NI_AdvSimd_ShiftRightArithmeticRoundedAddScalar:
721730
case NI_AdvSimd_ShiftRightLogicalAddScalar:
731+
case NI_AdvSimd_ShiftRightLogicalAndInsertScalar:
722732
case NI_AdvSimd_ShiftRightLogicalRoundedAddScalar:
723733
opt = INS_OPTS_NONE;
724734
emitSize = emitTypeSize(intrin.baseType);
@@ -736,6 +746,8 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
736746
case NI_AdvSimd_ShiftRightLogicalRoundedAdd:
737747
case NI_AdvSimd_ShiftRightLogicalRoundedNarrowingSaturateUpper:
738748
case NI_AdvSimd_ShiftRightLogicalRoundedNarrowingUpper:
749+
case NI_AdvSimd_ShiftLeftLogicalAndInsert:
750+
case NI_AdvSimd_ShiftRightAndInsert:
739751
{
740752
assert(isRMW);
741753

‎src/coreclr/src/jit/hwintrinsiclistarm64.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -179,6 +179,8 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftArithmeticSaturate,
179179
HARDWARE_INTRINSIC(AdvSimd, ShiftArithmeticSaturateScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sqshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_NoFlag)
180180
HARDWARE_INTRINSIC(AdvSimd, ShiftArithmeticScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_NoFlag)
181181
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogical, -1, 2, {INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_shl, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen)
182+
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalAndInsert, -1, 3, {INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli, INS_sli}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
183+
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalAndInsertScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sli, INS_sli, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
182184
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturate, -1, 2, {INS_sqshl, INS_uqshl, INS_sqshl, INS_uqshl, INS_sqshl, INS_uqshl, INS_sqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen)
183185
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturateScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SpecialCodeGen)
184186
HARDWARE_INTRINSIC(AdvSimd, ShiftLeftLogicalSaturateUnsigned, -1, 2, {INS_sqshlu, INS_invalid, INS_sqshlu, INS_invalid, INS_sqshlu, INS_invalid, INS_sqshlu, INS_invalid, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_BaseTypeFromFirstArg|HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen)
@@ -194,6 +196,8 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalRoundedScalar,
194196
HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalSaturate, -1, 2, {INS_uqshl, INS_uqshl, INS_uqshl, INS_uqshl, INS_uqshl, INS_uqshl, INS_uqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoFlag)
195197
HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalSaturateScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_uqshl, INS_uqshl, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_NoFlag)
196198
HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalScalar, 8, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ushl, INS_ushl, INS_invalid, INS_invalid}, HW_Category_SIMDScalar, HW_Flag_NoFlag)
199+
HARDWARE_INTRINSIC(AdvSimd, ShiftRightAndInsert, -1, 3, {INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
200+
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalAndInsertScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sri, INS_sri, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
197201
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmetic, -1, 2, {INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen)
198202
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticAdd, -1, 3, {INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
199203
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticAddScalar, 8, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ssra, INS_invalid, INS_invalid, INS_invalid}, HW_Category_IMM, HW_Flag_SupportsContainment|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)

‎src/coreclr/src/jit/lowerarmarch.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1426,6 +1426,9 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
14261426

14271427
case NI_AdvSimd_ExtractVector64:
14281428
case NI_AdvSimd_ExtractVector128:
1429+
case NI_AdvSimd_ShiftLeftLogicalAndInsert:
1430+
case NI_AdvSimd_ShiftLeftLogicalAndInsertScalar:
1431+
case NI_AdvSimd_ShiftRightAndInsert:
14291432
case NI_AdvSimd_ShiftRightArithmeticAdd:
14301433
case NI_AdvSimd_ShiftRightArithmeticAddScalar:
14311434
case NI_AdvSimd_ShiftRightArithmeticNarrowingSaturateUnsignedUpper:
@@ -1436,6 +1439,7 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node)
14361439
case NI_AdvSimd_ShiftRightArithmeticRoundedNarrowingSaturateUpper:
14371440
case NI_AdvSimd_ShiftRightLogicalAdd:
14381441
case NI_AdvSimd_ShiftRightLogicalAddScalar:
1442+
case NI_AdvSimd_ShiftRightLogicalAndInsertScalar:
14391443
case NI_AdvSimd_ShiftRightLogicalNarrowingSaturateUpper:
14401444
case NI_AdvSimd_ShiftRightLogicalNarrowingUpper:
14411445
case NI_AdvSimd_ShiftRightLogicalRoundedAdd:

‎src/coreclr/src/jit/lsraarm64.cpp‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1040,6 +1040,9 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree)
10401040

10411041
case NI_AdvSimd_ExtractVector64:
10421042
case NI_AdvSimd_ExtractVector128:
1043+
case NI_AdvSimd_ShiftLeftLogicalAndInsert:
1044+
case NI_AdvSimd_ShiftLeftLogicalAndInsertScalar:
1045+
case NI_AdvSimd_ShiftRightAndInsert:
10431046
case NI_AdvSimd_ShiftRightArithmeticAdd:
10441047
case NI_AdvSimd_ShiftRightArithmeticAddScalar:
10451048
case NI_AdvSimd_ShiftRightArithmeticNarrowingSaturateUnsignedUpper:
@@ -1050,6 +1053,7 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree)
10501053
case NI_AdvSimd_ShiftRightArithmeticRoundedNarrowingSaturateUpper:
10511054
case NI_AdvSimd_ShiftRightLogicalAdd:
10521055
case NI_AdvSimd_ShiftRightLogicalAddScalar:
1056+
case NI_AdvSimd_ShiftRightLogicalAndInsertScalar:
10531057
case NI_AdvSimd_ShiftRightLogicalNarrowingSaturateUpper:
10541058
case NI_AdvSimd_ShiftRightLogicalNarrowingUpper:
10551059
case NI_AdvSimd_ShiftRightLogicalRoundedAdd:

‎src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_r.csproj‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -752,6 +752,38 @@
752752
<Compile Include="PopCount.Vector128.SByte.cs" />
753753
<Compile Include="ReciprocalEstimate.Vector64.Single.cs" />
754754
<Compile Include="ReciprocalEstimate.Vector64.UInt32.cs" />
755+
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.Byte.cs" />
756+
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.Int16.cs" />
757+
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.Int32.cs" />
758+
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.SByte.cs" />
759+
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.UInt16.cs" />
760+
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.UInt32.cs" />
761+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Byte.cs" />
762+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Int16.cs" />
763+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Int32.cs" />
764+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Int64.cs" />
765+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.SByte.cs" />
766+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.UInt16.cs" />
767+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.UInt32.cs" />
768+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.UInt64.cs" />
769+
<Compile Include="ShiftLeftLogicalAndInsertScalar.Vector64.Int64.cs" />
770+
<Compile Include="ShiftLeftLogicalAndInsertScalar.Vector64.UInt64.cs" />
771+
<Compile Include="ShiftRightAndInsert.Vector64.Byte.cs" />
772+
<Compile Include="ShiftRightAndInsert.Vector64.Int16.cs" />
773+
<Compile Include="ShiftRightAndInsert.Vector64.Int32.cs" />
774+
<Compile Include="ShiftRightAndInsert.Vector64.SByte.cs" />
775+
<Compile Include="ShiftRightAndInsert.Vector64.UInt16.cs" />
776+
<Compile Include="ShiftRightAndInsert.Vector64.UInt32.cs" />
777+
<Compile Include="ShiftRightAndInsert.Vector128.Byte.cs" />
778+
<Compile Include="ShiftRightAndInsert.Vector128.Int16.cs" />
779+
<Compile Include="ShiftRightAndInsert.Vector128.Int32.cs" />
780+
<Compile Include="ShiftRightAndInsert.Vector128.Int64.cs" />
781+
<Compile Include="ShiftRightAndInsert.Vector128.SByte.cs" />
782+
<Compile Include="ShiftRightAndInsert.Vector128.UInt16.cs" />
783+
<Compile Include="ShiftRightAndInsert.Vector128.UInt32.cs" />
784+
<Compile Include="ShiftRightAndInsert.Vector128.UInt64.cs" />
785+
<Compile Include="ShiftRightLogicalAndInsertScalar.Vector64.Int64.cs" />
786+
<Compile Include="ShiftRightLogicalAndInsertScalar.Vector64.UInt64.cs" />
755787
<Compile Include="ReciprocalEstimate.Vector128.Single.cs" />
756788
<Compile Include="ReciprocalEstimate.Vector128.UInt32.cs" />
757789
<Compile Include="ReciprocalSquareRootEstimate.Vector64.Single.cs" />

‎src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_ro.csproj‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -752,6 +752,38 @@
752752
<Compile Include="PopCount.Vector128.SByte.cs" />
753753
<Compile Include="ReciprocalEstimate.Vector64.Single.cs" />
754754
<Compile Include="ReciprocalEstimate.Vector64.UInt32.cs" />
755+
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.Byte.cs" />
756+
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.Int16.cs" />
757+
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.Int32.cs" />
758+
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.SByte.cs" />
759+
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.UInt16.cs" />
760+
<Compile Include="ShiftLeftLogicalAndInsert.Vector64.UInt32.cs" />
761+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Byte.cs" />
762+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Int16.cs" />
763+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Int32.cs" />
764+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.Int64.cs" />
765+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.SByte.cs" />
766+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.UInt16.cs" />
767+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.UInt32.cs" />
768+
<Compile Include="ShiftLeftLogicalAndInsert.Vector128.UInt64.cs" />
769+
<Compile Include="ShiftLeftLogicalAndInsertScalar.Vector64.Int64.cs" />
770+
<Compile Include="ShiftLeftLogicalAndInsertScalar.Vector64.UInt64.cs" />
771+
<Compile Include="ShiftRightAndInsert.Vector64.Byte.cs" />
772+
<Compile Include="ShiftRightAndInsert.Vector64.Int16.cs" />
773+
<Compile Include="ShiftRightAndInsert.Vector64.Int32.cs" />
774+
<Compile Include="ShiftRightAndInsert.Vector64.SByte.cs" />
775+
<Compile Include="ShiftRightAndInsert.Vector64.UInt16.cs" />
776+
<Compile Include="ShiftRightAndInsert.Vector64.UInt32.cs" />
777+
<Compile Include="ShiftRightAndInsert.Vector128.Byte.cs" />
778+
<Compile Include="ShiftRightAndInsert.Vector128.Int16.cs" />
779+
<Compile Include="ShiftRightAndInsert.Vector128.Int32.cs" />
780+
<Compile Include="ShiftRightAndInsert.Vector128.Int64.cs" />
781+
<Compile Include="ShiftRightAndInsert.Vector128.SByte.cs" />
782+
<Compile Include="ShiftRightAndInsert.Vector128.UInt16.cs" />
783+
<Compile Include="ShiftRightAndInsert.Vector128.UInt32.cs" />
784+
<Compile Include="ShiftRightAndInsert.Vector128.UInt64.cs" />
785+
<Compile Include="ShiftRightLogicalAndInsertScalar.Vector64.Int64.cs" />
786+
<Compile Include="ShiftRightLogicalAndInsertScalar.Vector64.UInt64.cs" />
755787
<Compile Include="ReciprocalEstimate.Vector128.Single.cs" />
756788
<Compile Include="ReciprocalEstimate.Vector128.UInt32.cs" />
757789
<Compile Include="ReciprocalSquareRootEstimate.Vector64.Single.cs" />

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