Add basic support for GT_CLS_VAR_ADDR to the ARM64 JIT

Author: tannergooding

src/coreclr/src/jit/emitarm64.cpp

@@ -12718,7 +12718,7 @@ void emitter::emitInsLoadStoreOp(instruction ins, emitAttr attr, regNumber dataR
 
     if (addr->isContained())
     {
-        assert(addr->OperGet() == GT_LCL_VAR_ADDR || addr->OperGet() == GT_LEA);
+        assert(addr->OperGet() == GT_CLS_VAR_ADDR || addr->OperGet() == GT_LCL_VAR_ADDR || addr->OperGet() == GT_LEA);
 
         int   offset = 0;
         DWORD lsl    = 0;
@@ -12795,7 +12795,13 @@ void emitter::emitInsLoadStoreOp(instruction ins, emitAttr attr, regNumber dataR
         }
         else // no Index register
         {
-            if (emitIns_valid_imm_for_ldst_offset(offset, emitTypeSize(indir->TypeGet())))
+            if (addr->OperGet() == GT_CLS_VAR_ADDR)
+            {
+                // Get a temp integer register to compute long address.
+                regNumber addrReg = indir->GetSingleTempReg();
+                emitIns_R_C(ins, attr, dataReg, addrReg, addr->AsClsVar()->gtClsVarHnd, 0);
+            }
+            else if (emitIns_valid_imm_for_ldst_offset(offset, emitTypeSize(indir->TypeGet())))
             {
                 // Then load/store dataReg from/to [memBase + offset]
                 emitIns_R_R_I(ins, attr, dataReg, memBase->GetRegNum(), offset);

src/coreclr/src/jit/lowerarmarch.cpp

@@ -857,10 +857,12 @@ void Lowering::ContainCheckIndir(GenTreeIndir* indirNode)
     }
 #endif // FEATURE_SIMD
 
-    GenTree* addr          = indirNode->Addr();
-    bool     makeContained = true;
+    GenTree* addr = indirNode->Addr();
+
     if ((addr->OperGet() == GT_LEA) && IsSafeToContainMem(indirNode, addr))
     {
+        bool makeContained = true;
+
 #ifdef TARGET_ARM
         // ARM floating-point load/store doesn't support a form similar to integer
         // ldr Rdst, [Rbase + Roffset] with offset in a register. The only supported
@@ -884,12 +886,23 @@ void Lowering::ContainCheckIndir(GenTreeIndir* indirNode)
                 }
             }
         }
-#endif
+#endif // TARGET_ARM
+
         if (makeContained)
         {
             MakeSrcContained(indirNode, addr);
         }
     }
+#ifdef TARGET_ARM64
+    else if (addr->OperGet() == GT_CLS_VAR_ADDR)
+    {
+        // These nodes go into an addr mode:
+        // - GT_CLS_VAR_ADDR turns into a constant.
+
+        // make this contained, it turns into a constant that goes into an addr mode
+        MakeSrcContained(indirNode, addr);
+    }
+#endif // TARGET_ARM64
 }
 
 //------------------------------------------------------------------------

src/coreclr/src/jit/lsraarmarch.cpp

@@ -74,23 +74,32 @@ int LinearScan::BuildIndir(GenTreeIndir* indirTree)
 
     if (addr->isContained())
     {
-        assert(addr->OperGet() == GT_LEA);
-        GenTreeAddrMode* lea = addr->AsAddrMode();
-        index                = lea->Index();
-        cns                  = lea->Offset();
-
-        // On ARM we may need a single internal register
-        // (when both conditions are true then we still only need a single internal register)
-        if ((index != nullptr) && (cns != 0))
+        if (addr->OperGet() == GT_LEA)
         {
-            // ARM does not support both Index and offset so we need an internal register
-            buildInternalIntRegisterDefForNode(indirTree);
+            GenTreeAddrMode* lea = addr->AsAddrMode();
+            index                = lea->Index();
+            cns                  = lea->Offset();
+
+            // On ARM we may need a single internal register
+            // (when both conditions are true then we still only need a single internal register)
+            if ((index != nullptr) && (cns != 0))
+            {
+                // ARM does not support both Index and offset so we need an internal register
+                buildInternalIntRegisterDefForNode(indirTree);
+            }
+            else if (!emitter::emitIns_valid_imm_for_ldst_offset(cns, emitTypeSize(indirTree)))
+            {
+                // This offset can't be contained in the ldr/str instruction, so we need an internal register
+                buildInternalIntRegisterDefForNode(indirTree);
+            }
         }
-        else if (!emitter::emitIns_valid_imm_for_ldst_offset(cns, emitTypeSize(indirTree)))
+#ifdef TARGET_ARM64
+        else if (addr->OperGet() == GT_CLS_VAR_ADDR)
         {
-            // This offset can't be contained in the ldr/str instruction, so we need an internal register
+            // Reserve int to load constant from memory (IF_LARGELDC)
             buildInternalIntRegisterDefForNode(indirTree);
         }
+#endif // TARGET_ARM64
     }
 
 #ifdef FEATURE_SIMD