11Freescale i.MX General Power Controller
22=======================================
33
4- The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
5- counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
6- domains.
4+ The i.MX6 General Power Control (GPC) block contains DVFS load tracking
5+ counters and Power Gating Control (PGC).
76
87Required properties:
98- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
109- reg: should be register base and length as documented in the
1110 datasheet
12- - interrupts: Should contain GPC interrupt request 1
13- - pu-supply: Link to the LDO regulator powering the PU power domain
14- - clocks: Clock phandles to devices in the PU power domain that need
15- to be enabled during domain power-up for reset propagation.
16- - #power-domain-cells: Should be 1, see below:
11+ - interrupts: Should contain one interrupt specifier for the GPC interrupt
12+ - clocks: Must contain an entry for each entry in clock-names.
13+ See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
14+ - clock-names: Must include the following entries:
15+ - ipg
1716
18- The gpc node is a power-controller as documented by the generic power domain
19- bindings in Documentation/devicetree/bindings/power/power_domain.txt.
17+ The power domains are generic power domain providers as documented in
18+ Documentation/devicetree/bindings/power/power_domain.txt. They are described as
19+ subnodes of the power gating controller 'pgc' node of the GPC and should
20+ contain the following:
21+
22+ Required properties:
23+ - reg: the DOMAIN_INDEX as used by the client devices to refer to this
24+ power domain
25+ The following DOMAIN_INDEX values are valid for i.MX6Q:
26+ ARM_DOMAIN 0
27+ PU_DOMAIN 1
28+ The following additional DOMAIN_INDEX value is valid for i.MX6SL:
29+ DISPLAY_DOMAIN 2
30+
31+ - #power-domain-cells: Should be 0
32+
33+ Optional properties:
34+ - clocks: a number of phandles to clocks that need to be enabled during domain
35+ power-up sequencing to ensure reset propagation into devices located inside
36+ this power domain
37+ - power-supply: a phandle to the regulator powering this domain
2038
2139Example:
2240
@@ -25,35 +43,43 @@ Example:
2543 reg = <0x020dc000 0x4000>;
2644 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
2745 <0 90 IRQ_TYPE_LEVEL_HIGH>;
28- pu-supply = <®_pu>;
29- clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
30- <&clks IMX6QDL_CLK_GPU3D_SHADER>,
31- <&clks IMX6QDL_CLK_GPU2D_CORE>,
32- <&clks IMX6QDL_CLK_GPU2D_AXI>,
33- <&clks IMX6QDL_CLK_OPENVG_AXI>,
34- <&clks IMX6QDL_CLK_VPU_AXI>;
35- #power-domain-cells = <1>;
46+ clocks = <&clks IMX6QDL_CLK_IPG>;
47+ clock-names = "ipg";
48+
49+ pgc {
50+ #address-cells = <1>;
51+ #size-cells = <0>;
52+
53+ power-domain@0 {
54+ reg = <0>;
55+ #power-domain-cells = <0>;
56+ };
57+ pd_pu: power-domain@1 {
58+ reg = <1>;
59+ #power-domain-cells = <0>;
60+ power-supply = <®_pu>;
61+ clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
62+ <&clks IMX6QDL_CLK_GPU3D_SHADER>,
63+ <&clks IMX6QDL_CLK_GPU2D_CORE>,
64+ <&clks IMX6QDL_CLK_GPU2D_AXI>,
65+ <&clks IMX6QDL_CLK_OPENVG_AXI>,
66+ <&clks IMX6QDL_CLK_VPU_AXI>;
67+ };
68+ };
3669 };
3770
3871
3972Specifying power domain for IP modules
4073======================================
4174
4275IP cores belonging to a power domain should contain a 'power-domains' property
43- that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying
44- the power domain the device belongs to.
76+ that is a phandle pointing to the power domain the device belongs to.
4577
4678Example of a device that is part of the PU power domain:
4779
4880 vpu: vpu@02040000 {
4981 reg = <0x02040000 0x3c000>;
5082 /* ... */
51- power-domains = <&gpc 1 >;
83+ power-domains = <&pd_pu >;
5284 /* ... */
5385 };
54-
55- The following DOMAIN_INDEX values are valid for i.MX6Q:
56- ARM_DOMAIN 0
57- PU_DOMAIN 1
58- The following additional DOMAIN_INDEX value is valid for i.MX6SL:
59- DISPLAY_DOMAIN 2
0 commit comments