enhance: add v2 and v4 feature gates

Author: andelf

Cargo.toml

@@ -8,8 +8,8 @@ documentation = "https://docs.rs/qingke"
 homepage = "https://github.com/ch32-rs/qingke"
 categories = ["embedded", "no-std", "hardware-support"]
 license = "MIT/Apache-2.0"
-version = "0.5.0" # for rt and macros
-edition = "2021"
+version = "0.6.0" # for rt and macros
+edition = "2024"
 
 [package]
 name = "qingke"
@@ -27,17 +27,19 @@ readme = "README.md"
 
 [dependencies]
 bit_field = "0.10.2"
-riscv = "0.12.0"
+riscv = "0.15.0"
 cfg-if = "1.0"
 critical-section = { version = "1.2.0", features = [
     "restore-state-bool",
 ], optional = true }
-defmt = { version = "0.3.8", optional = true }
+defmt = { version = "1.0.1", optional = true }
 
 [features]
 critical-section-impl = ["dep:critical-section"]
 defmt = ["dep:defmt"]
+v2 = []
 v3 = []
+v4 = []
 unsafe-trust-wch-atomics = []
 
 [package.metadata.docs.rs]

qingke-rt/Cargo.toml

@@ -14,9 +14,9 @@ readme = "README.md"
 
 
 [features]
-v2 = []
+v2 = ["qingke/v2"]
 v3 = ["qingke/v3"]
-v4 = []
+v4 = ["qingke/v4"]
 
 u-mode = []
 # v5 is not released yet
@@ -25,8 +25,8 @@ u-mode = []
 highcode = []
 
 [dependencies]
-qingke-rt-macros = {  version = "0.5.0", path = "./macros" }
-qingke = { version = "0.5.0", path = "../", features = ["critical-section-impl"] }
+qingke-rt-macros = {  version = "0.6.0", path = "./macros" }
+qingke = { version = "0.6.0", path = "../", features = ["critical-section-impl"] }
 
 [package.metadata.docs.rs]
 targets = ["riscv32imc-unknown-none-elf"]

src/critical_section_impl.rs

@@ -6,7 +6,7 @@ set_impl!(SingleHartCriticalSection);
 unsafe impl Impl for SingleHartCriticalSection {
     unsafe fn acquire() -> RawRestoreState {
         cfg_if::cfg_if! {
-            if #[cfg(qingke_v2)] {
+            if #[cfg(feature = "v2")] {
                 // CH32V003 (qingke_v2) does not have gintenr register
                 // Use standard RISC-V mstatus.MIE instead
                 let mut mstatus: usize;
@@ -24,7 +24,7 @@ unsafe impl Impl for SingleHartCriticalSection {
         // Only re-enable interrupts if they were enabled before the critical section.
         if irq_state {
             cfg_if::cfg_if! {
-                if #[cfg(qingke_v2)] {
+                if #[cfg(feature = "v2")] {
                     core::arch::asm!("csrsi mstatus, 0b1000");
                 } else {
                     use crate::register::gintenr;

src/register/gintenr.rs

@@ -6,34 +6,34 @@
 //!
 //! Write 0x08 to enable global interrupt
 //!
-//! NOTE: This register is NOT available on qingke_v2 (CH32V003).
-//! Use mstatus.MIE instead for qingke_v2.
+//! NOTE: This register is NOT available on v2 (CH32V003).
+//! Use mstatus.MIE instead for v2.
 
-#[cfg(not(qingke_v2))]
+#[cfg(not(feature = "v2"))]
 use core::arch::asm;
 
-#[cfg(not(qingke_v2))]
+#[cfg(not(feature = "v2"))]
 #[inline]
 pub fn read() -> usize {
     let ans: usize;
     unsafe { asm!("csrr {}, 0x800", out(reg) ans) };
     ans
 }
 
-#[cfg(not(qingke_v2))]
+#[cfg(not(feature = "v2"))]
 #[inline]
 pub unsafe fn write(bits: usize) {
     asm!("csrw 0x800, {}", in(reg) bits);
 }
 
-#[cfg(not(qingke_v2))]
+#[cfg(not(feature = "v2"))]
 #[inline]
 pub unsafe fn set_enable() {
     let mask = 0x8;
     asm!("csrs 0x800, {}", in(reg) mask);
 }
 
-#[cfg(not(qingke_v2))]
+#[cfg(not(feature = "v2"))]
 #[inline]
 /// Disable interrupt and return the old `GINTENR` value
 pub fn set_disable() -> usize {