Skip to content

Commit dd0b3b8

Browse files
Rot127Rot127
committed
Add writeback information to STC and LDC instructions.
1 parent a1d688c commit dd0b3b8

File tree

4 files changed

+27
-18
lines changed

4 files changed

+27
-18
lines changed

‎llvm/lib/Target/ARM/ARMInstrFormats.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1405,8 +1405,8 @@ class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
14051405
}
14061406

14071407
class T2I<dag oops, dag iops, InstrItinClass itin,
1408-
string opc, string asm, list<dag> pattern, AddrMode am = AddrModeNone>
1409-
: Thumb2I<oops, iops, am, 4, itin, opc, asm, "", pattern>;
1408+
string opc, string asm, list<dag> pattern, AddrMode am = AddrModeNone, string constraints = "">
1409+
: Thumb2I<oops, iops, am, 4, itin, opc, asm, constraints, pattern>;
14101410
class T2Ii12<dag oops, dag iops, InstrItinClass itin,
14111411
string opc, string asm, list<dag> pattern>
14121412
: Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;

‎llvm/lib/Target/ARM/ARMInstrInfo.td‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5437,25 +5437,25 @@ def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
54375437
}
54385438

54395439
class ACI<dag oops, dag iops, string opc, string asm,
5440-
list<dag> pattern, IndexMode im = IndexModeNone,
5440+
list<dag> pattern, string cstrs = "", IndexMode im = IndexModeNone,
54415441
AddrMode am = AddrModeNone>
54425442
: I<oops, iops, am, 4, im, BrFrm, NoItinerary,
5443-
opc, asm, "", pattern> {
5443+
opc, asm, cstrs, pattern> {
54445444
let Inst{27-25} = 0b110;
54455445
}
54465446
class ACInoP<dag oops, dag iops, string opc, string asm,
5447-
list<dag> pattern, IndexMode im = IndexModeNone,
5447+
list<dag> pattern, string constraints = "", IndexMode im = IndexModeNone,
54485448
AddrMode am = AddrModeNone>
54495449
: InoP<oops, iops, am, 4, im, BrFrm, NoItinerary,
5450-
opc, asm, "", pattern> {
5450+
opc, asm, constraints, pattern> {
54515451
let Inst{31-28} = 0b1111;
54525452
let Inst{27-25} = 0b110;
54535453
}
54545454

54555455
let DecoderNamespace = "CoProc" in {
54565456
multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
54575457
def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
5458-
asm, "\t$cop, $CRd, $addr", pattern, IndexModeNone,
5458+
asm, "\t$cop, $CRd, $addr", pattern, "", IndexModeNone,
54595459
AddrMode5> {
54605460
bits<13> addr;
54615461
bits<4> cop;
@@ -5471,8 +5471,8 @@ multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
54715471
let Inst{7-0} = addr{7-0};
54725472
let DecoderMethod = "DecodeCopMemInstruction";
54735473
}
5474-
def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
5475-
asm, "\t$cop, $CRd, $addr!", [], IndexModePre> {
5474+
def _PRE : ACI<(outs GPR:$Rn_wb), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
5475+
asm, "\t$cop, $CRd, $addr!", [], "$addr.base = $Rn_wb", IndexModePre> {
54765476
bits<13> addr;
54775477
bits<4> cop;
54785478
bits<4> CRd;
@@ -5489,7 +5489,7 @@ multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
54895489
}
54905490
def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
54915491
postidx_imm8s4:$offset),
5492-
asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> {
5492+
asm, "\t$cop, $CRd, $addr, $offset", [], "", IndexModePost> {
54935493
bits<9> offset;
54945494
bits<4> addr;
54955495
bits<4> cop;
@@ -5527,7 +5527,7 @@ multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
55275527
}
55285528
multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> {
55295529
def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
5530-
asm, "\t$cop, $CRd, $addr", pattern, IndexModeNone,
5530+
asm, "\t$cop, $CRd, $addr", pattern, "", IndexModeNone,
55315531
AddrMode5> {
55325532
bits<13> addr;
55335533
bits<4> cop;
@@ -5543,8 +5543,8 @@ multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> {
55435543
let Inst{7-0} = addr{7-0};
55445544
let DecoderMethod = "DecodeCopMemInstruction";
55455545
}
5546-
def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
5547-
asm, "\t$cop, $CRd, $addr!", [], IndexModePre> {
5546+
def _PRE : ACInoP<(outs GPR:$Rn_wb), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
5547+
asm, "\t$cop, $CRd, $addr!", [], "$addr.base = $Rn_wb", IndexModePre> {
55485548
bits<13> addr;
55495549
bits<4> cop;
55505550
bits<4> CRd;
@@ -5561,7 +5561,7 @@ multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> {
55615561
}
55625562
def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
55635563
postidx_imm8s4:$offset),
5564-
asm, "\t$cop, $CRd, $addr, $offset", [], IndexModePost> {
5564+
asm, "\t$cop, $CRd, $addr, $offset", [], "", IndexModePost> {
55655565
bits<9> offset;
55665566
bits<4> addr;
55675567
bits<4> cop;

‎llvm/lib/Target/ARM/ARMInstrThumb2.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4317,8 +4317,8 @@ def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
43174317
// Coprocessor load/store -- for disassembly only
43184318
//
43194319
class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm,
4320-
list<dag> pattern, AddrMode am = AddrModeNone>
4321-
: T2I<oops, iops, NoItinerary, opc, asm, pattern, am> {
4320+
list<dag> pattern, AddrMode am = AddrModeNone, string constraints = "">
4321+
: T2I<oops, iops, NoItinerary, opc, asm, pattern, am, constraints> {
43224322
let Inst{31-28} = op31_28;
43234323
let Inst{27-25} = 0b110;
43244324
}
@@ -4342,8 +4342,8 @@ multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm, list<dag>
43424342
let DecoderMethod = "DecodeCopMemInstruction";
43434343
}
43444344
def _PRE : T2CI<op31_28,
4345-
(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4346-
asm, "\t$cop, $CRd, $addr!", []> {
4345+
(outs GPR:$Rn_wb), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4346+
asm, "\t$cop, $CRd, $addr!", [], AddrMode5, "$addr.base = $Rn_wb"> {
43474347
bits<13> addr;
43484348
bits<4> cop;
43494349
bits<4> CRd;

‎llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1862,12 +1862,17 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
18621862
const MCDisassembler *Decoder) {
18631863
DecodeStatus S = MCDisassembler::Success;
18641864

1865+
unsigned P = fieldFromInstruction_4(Insn, 24, 1);
1866+
unsigned W = fieldFromInstruction_4(Insn, 21, 1);
18651867
unsigned pred = fieldFromInstruction(Insn, 28, 4);
18661868
unsigned CRd = fieldFromInstruction(Insn, 12, 4);
18671869
unsigned coproc = fieldFromInstruction(Insn, 8, 4);
18681870
unsigned imm = fieldFromInstruction(Insn, 0, 8);
18691871
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
18701872
unsigned U = fieldFromInstruction(Insn, 23, 1);
1873+
// Pre-Indexed implies writeback to Rn
1874+
bool IsPreIndexed = (P == 1) && (W == 1);
1875+
18711876
const FeatureBitset &featureBits =
18721877
((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
18731878

@@ -1943,6 +1948,10 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
19431948
if (featureBits[ARM::HasV8Ops] && (coproc != 14))
19441949
return MCDisassembler::Fail;
19451950

1951+
if (IsPreIndexed)
1952+
// Dummy operand for Rn_wb.
1953+
MCOperand_CreateImm0(Inst, (0));
1954+
19461955
Inst.addOperand(MCOperand::createImm(coproc));
19471956
Inst.addOperand(MCOperand::createImm(CRd));
19481957
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))

0 commit comments

Comments
 (0)