How to compile Calyx such that the output is appropriate for Vivado synthesis?

[gussmith23]

Hi all, I'm trying to compile the examples and then run them through synthesis manually in Vivado, so that I can attempt to get timing estimates. I already know that a design such as examples/futil/dot-product.futil can be run through Vivado synthesis, because fud e --to resource-estimate examples/futil/dot-product.futil produces results. However, when I try doing fud e --to verilog examples/futil/dot-product.futil and then loading the results into Vivado and doing synthesis, I get errors:

****** Vivado v2021.2 (64-bit)
  **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
  **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

Vivado% read_verilog -sv tmp.v 
/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v
Vivado% synth_design -mode "out_of_context" -top "main" -part "xczu3eg-sbva484-1-e"
Command: synth_design -mode out_of_context -top main -part xczu3eg-sbva484-1-e
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xczu3eg'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu3eg'
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 125269
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2590.254 ; gain = 0.000 ; free physical = 50370 ; free virtual = 69648
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'main' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5838]
ERROR: [Synth 8-27] string type not supported [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5844]
ERROR: [Synth 8-6156] failed synthesizing module 'main' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5838]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2590.254 ; gain = 0.000 ; free physical = 50061 ; free virtual = 69338
---------------------------------------------------------------------------------
synthesize failed
INFO: [Common 17-83] Releasing license: Synthesis
6 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Vivado Synthesis failed

If I delete the unsynthesizable code, then I get:

****** Vivado v2021.2 (64-bit)
  **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021
  **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

Vivado% read_verilog -sv tmp.v
/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v
Vivado% synth_design -mode "out_of_context" -top "main" -part "xczu3eg-sbva484-1-e"
Command: synth_design -mode out_of_context -top main -part xczu3eg-sbva484-1-e
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xczu3eg'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu3eg'
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 125457
---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2590.254 ; gain = 0.000 ; free physical = 50379 ; free virtual = 69657
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'main' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5838]
INFO: [Synth 8-6157] synthesizing module 'std_mem_d1' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5635]
	Parameter WIDTH bound to: 32 - type: integer 
	Parameter SIZE bound to: 8 - type: integer 
	Parameter IDX_SIZE bound to: 4 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'std_mem_d1' (1#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5635]
INFO: [Synth 8-6157] synthesizing module 'std_reg' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5612]
	Parameter WIDTH bound to: 32 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'std_reg' (2#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5612]
INFO: [Synth 8-6157] synthesizing module 'std_add' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5468]
	Parameter WIDTH bound to: 32 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'lakeroad_xilinx_ultrascale_plus_add32' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:2727]
INFO: [Synth 8-6157] synthesizing module 'LUT6_2' [/tools/Xilinx/Vivado/2021.2/scripts/rt/data/unisim_comp.v:62905]
	Parameter INIT bound to: 64'b0110000000000000000000000000000010100000000000000000000000000000 
INFO: [Synth 8-6155] done synthesizing module 'LUT6_2' (3#1) [/tools/Xilinx/Vivado/2021.2/scripts/rt/data/unisim_comp.v:62905]
INFO: [Synth 8-6157] synthesizing module 'CARRY8' [/tools/Xilinx/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1505]
INFO: [Synth 8-6155] done synthesizing module 'CARRY8' (4#1) [/tools/Xilinx/Vivado/2021.2/scripts/rt/data/unisim_comp.v:1505]
INFO: [Synth 8-6155] done synthesizing module 'lakeroad_xilinx_ultrascale_plus_add32' (5#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:2727]
INFO: [Synth 8-6155] done synthesizing module 'std_add' (6#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5468]
INFO: [Synth 8-6157] synthesizing module 'std_add__parameterized0' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5468]
	Parameter WIDTH bound to: 4 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'lakeroad_xilinx_ultrascale_plus_add4' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:2477]
INFO: [Synth 8-6155] done synthesizing module 'lakeroad_xilinx_ultrascale_plus_add4' (7#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:2477]
INFO: [Synth 8-6155] done synthesizing module 'std_add__parameterized0' (7#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5468]
INFO: [Synth 8-6157] synthesizing module 'std_const' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5340]
	Parameter WIDTH bound to: 4 - type: integer 
	Parameter VALUE bound to: 4'b0000 
INFO: [Synth 8-6155] done synthesizing module 'std_const' (8#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5340]
INFO: [Synth 8-6157] synthesizing module 'std_const__parameterized0' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5340]
	Parameter WIDTH bound to: 4 - type: integer 
	Parameter VALUE bound to: 4'b0111 
INFO: [Synth 8-6155] done synthesizing module 'std_const__parameterized0' (8#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5340]
INFO: [Synth 8-6157] synthesizing module 'std_const__parameterized1' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5340]
	Parameter WIDTH bound to: 1 - type: integer 
	Parameter VALUE bound to: 1'b0 
INFO: [Synth 8-6155] done synthesizing module 'std_const__parameterized1' (8#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5340]
INFO: [Synth 8-6157] synthesizing module 'std_const__parameterized2' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5340]
	Parameter WIDTH bound to: 4 - type: integer 
	Parameter VALUE bound to: 4'b0001 
INFO: [Synth 8-6155] done synthesizing module 'std_const__parameterized2' (8#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5340]
INFO: [Synth 8-6157] synthesizing module 'std_reg__parameterized0' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5612]
	Parameter WIDTH bound to: 4 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'std_reg__parameterized0' (8#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5612]
INFO: [Synth 8-6157] synthesizing module 'std_le' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5568]
	Parameter WIDTH bound to: 4 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'std_le' (9#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5568]
INFO: [Synth 8-6157] synthesizing module 'std_mult_pipe' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:354]
	Parameter WIDTH bound to: 32 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'std_fp_mult_pipe' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:27]
	Parameter WIDTH bound to: 32 - type: integer 
	Parameter INT_WIDTH bound to: 32 - type: integer 
	Parameter FRAC_WIDTH bound to: 0 - type: integer 
	Parameter SIGNED bound to: 0 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'std_fp_mult_pipe' (10#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:27]
INFO: [Synth 8-6155] done synthesizing module 'std_mult_pipe' (11#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:354]
INFO: [Synth 8-6157] synthesizing module 'std_mem_d1__parameterized0' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5635]
	Parameter WIDTH bound to: 32 - type: integer 
	Parameter SIZE bound to: 1 - type: integer 
	Parameter IDX_SIZE bound to: 1 - type: integer 
WARNING: [Synth 8-4767] Trying to implement RAM 'mem_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
	1: Only 1 word in RAM 
RAM "mem_reg" dissolved into registers
INFO: [Synth 8-6155] done synthesizing module 'std_mem_d1__parameterized0' (11#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5635]
INFO: [Synth 8-6157] synthesizing module 'std_reg__parameterized1' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5612]
	Parameter WIDTH bound to: 1 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'std_reg__parameterized1' (11#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5612]
INFO: [Synth 8-6157] synthesizing module 'std_wire' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5349]
	Parameter WIDTH bound to: 1 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'std_wire' (12#1) [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5349]
ERROR: [Synth 8-6058] Synth Error: Multiple assignment to port `fsm.in'.  [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:6378]
ERROR: [Synth 8-6156] failed synthesizing module 'main' [/home/gus/lakeroad-evaluation/calyx-xilinx-ultrascale-plus/tmp.v:5838]
---------------------------------------------------------------------------------
Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2590.254 ; gain = 0.000 ; free physical = 50059 ; free virtual = 69337
---------------------------------------------------------------------------------
synthesize failed
INFO: [Common 17-83] Releasing license: Synthesis
44 Infos, 1 Warnings, 0 Critical Warnings and 3 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Vivado Synthesis failed

Is there anything special I need to do to compile these designs to be usable in Vivado? It's been years since I've used Vivado with any regularity, so there may also be stuff I can do on the Vivado side.

[rachitnigam]

Yup, synthesis requires a different compilation flow than normal simulation. You want to run something like cargo run -- <file> -p external (if you're just running the calyx compiler) or fud e --to synth-verilog <file> to get synthesizable verilog.

You can use the fud ... -vv flag to make fud print out the commands it's running and fud .. -n to do a "dry run" and see which stages are used in the process of generating resource-estimate and recreate the commands yourself.

[gussmith23]

woohoo!!