QEMU: qemu support booting 32bit linux 5.4 with opensbi

	qemu source: atclnx01:/home/project/git_repo/toolchain/qemu.git
	qemu branch: andes-v5-v3.1.0

	// important !!!!!!
	// opensbi MUST using this revision, otherwise the system will hang.
	opensbi revision: 15ed1e74526d85f94c2cda338c572e36e249c803

	command:
		sudo qemu-system-riscv32 \
			-smp 2 \
			-machine 'andes_ae350'\
			-nographic \
			-m 1G \
			-kernel /local/dylan/vcu118_32bit/bin/fw_payload.elf \
			-netdev type=tap,id=net0 \
			-device virtio-net-device,netdev=net0

Author: Dylan-Jhong

arch/riscv/Kconfig.socs

@@ -10,4 +10,11 @@ config SOC_SIFIVE
        help
          This enables support for SiFive SoC platform hardware.
 
+config ANDES_QEMU_SUPPORT
+	bool "Andes QEMU SUPPORT"
+	depends on SOC_SIFIVE
+	default n
+	help
+	  Andes QEMU Support.
+
 endmenu

arch/riscv/boot/dts/ae350_c1_32.dts

@@ -0,0 +1,302 @@
+/dts-v1/;
+
+/ {
+	compatible = "andestech,ae350";
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+	dma-coherent;
+
+	cpus {
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		timebase-frequency = <0x3938700>;
+
+		cpu@0 {
+			device_type = "cpu";
+			reg = <0x0>;
+			status = "okay";
+			compatible = "riscv";
+			riscv,isa = "rv32i2p0m2p0a2p0c2p0xv5-0p0";
+			riscv,priv-major = <0x1>;
+			riscv,priv-minor = <0xa>;
+			mmu-type = "riscv,sv32";
+			clock-frequency = <0x3938700>;
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <0x20>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <0x20>;
+			next-level-cache = <0x1>;
+
+			interrupt-controller {
+				#interrupt-cells = <0x1>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+				phandle = <0x2>;
+			};
+		};
+	};
+
+	l2-cache@e0500000 {
+		compatible = "cache";
+		cache-level = <0x2>;
+		cache-size = <0x40000>;
+		reg = <0x0 0xe0500000 0x0 0x40000>;
+		andes,inst-prefetch = <0x3>;
+		andes,data-prefetch = <0x3>;
+		andes,tag-ram-ctl = <0x0 0x0>;
+		andes,data-ram-ctl = <0x0 0x0>;
+		phandle = <0x1>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x40000000>;
+	};
+
+	soc {
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		compatible = "andestech,riscv-ae350-soc";
+		ranges;
+
+		interrupt-controller@e4000000 {
+			compatible = "riscv,plic0";
+			#address-cells = <0x2>;
+			#interrupt-cells = <0x2>;
+			interrupt-controller;
+			reg = <0x0 0xe4000000 0x0 0x2000000>;
+			riscv,ndev = <0x47>;
+			interrupts-extended = <0x2 0xb 0x2 0x9>;
+			phandle = <0x3>;
+		};
+
+		interrupt-controller@e6400000 {
+			compatible = "riscv,plic1";
+			#address-cells = <0x2>;
+			#interrupt-cells = <0x2>;
+			interrupt-controller;
+			reg = <0x0 0xe6400000 0x0 0x400000>;
+			riscv,ndev = <0x1>;
+			interrupts-extended = <0x2 0x3>;
+		};
+
+		plmt0@e6000000 {
+			compatible = "riscv,plmt0";
+			reg = <0x0 0xe6000000 0x0 0x100000>;
+			interrupts-extended = <0x2 0x7>;
+		};
+	};
+
+	virt_100mhz {
+		#clock-cells = <0x0>;
+		compatible = "fixed-clock";
+		clock-frequency = <0x5f5e100>;
+		phandle = <0x4>;
+	};
+
+	smu@f0100000 {
+		compatible = "andestech,atcsmu";
+		reg = <0x0 0xf0100000 0x0 0x1000>;
+	};
+
+	wdt@f0500000 {
+		compatible = "andestech,atcwdt200";
+		interrupts = <0x0 0x4>;
+		reg = <0x0 0xf0500000 0x0 0x1000>;
+		clock-frequency = <0xe4e1c0>;
+		interrupt-parent = <0x3>;
+	};
+
+	timer@f0400000 {
+		compatible = "andestech,atcpit100";
+		reg = <0x0 0xf0400000 0x0 0x1000>;
+		clock-frequency = <0x3938700>;
+		interrupts = <0x3 0x4>;
+		interrupt-parent = <0x3>;
+	};
+
+	serial@f0300000 {
+		compatible = "andestech,uart16550", "ns16550a";
+		reg = <0x0 0xf0300000 0x0 0x1000>;
+		interrupts = <0x9 0x4>;
+		clock-frequency = <0x12c0000>;
+		reg-shift = <0x2>;
+		reg-offset = <0x20>;
+		no-loopback-test = <0x1>;
+		interrupt-parent = <0x3>;
+	};
+
+	gpio@f0700000 {
+		compatible = "andestech,atcgpio100";
+		reg = <0x0 0xf0700000 0x0 0x1000>;
+		interrupts = <0x7 0x4>;
+		interrupt-parent = <0x3>;
+	};
+
+	rtc@f0600000 {
+		compatible = "andestech,atcrtc100";
+		reg = <0x0 0xf0600000 0x0 0x1000>;
+		interrupts = <0x1 0x4 0x2 0x4>;
+		interrupt-parent = <0x3>;
+		wakeup-source;
+	};
+
+	mac@e0100000 {
+		compatible = "andestech,atmac100";
+		reg = <0x0 0xe0100000 0x0 0x1000>;
+		interrupts = <0x13 0x4>;
+		interrupt-parent = <0x3>;
+	};
+
+	mmc@f0e00000 {
+		compatible = "andestech,atfsdc010";
+		max-frequency = <0x5f5e100>;
+		clock-freq-min-max = <0x61a80 0x5f5e100>;
+		fifo-depth = <0x10>;
+		reg = <0x0 0xf0e00000 0x0 0x1000>;
+		interrupts = <0x12 0x4>;
+		cap-sd-highspeed;
+		interrupt-parent = <0x3>;
+	};
+
+	dma@f0c00000 {
+		compatible = "andestech,atcdmac300";
+		reg = <0x0 0xf0c00000 0x0 0x1000>;
+		interrupts = <0xa 0x4 0x40 0x4 0x41 0x4 0x42 0x4 0x43 0x4 0x44 0x4 0x45 0x4 0x46 0x4 0x47 0x4>;
+		dma-channels = <0x8>;
+		interrupt-parent = <0x3>;
+	};
+
+	lcd@e0200000 {
+		compatible = "andestech,atflcdc100";
+		reg = <0x0 0xe0200000 0x0 0x1000>;
+		interrupts = <0x14 0x4>;
+		interrupt-parent = <0x3>;
+	};
+
+	smc@e0400000 {
+		compatible = "andestech,atfsmc020";
+		reg = <0x0 0xe0400000 0x0 0x1000>;
+	};
+
+	snd@f0d00000 {
+		compatible = "andestech,atfac97";
+		reg = <0x0 0xf0d00000 0x0 0x1000>;
+		interrupts = <0x11 0x4>;
+		interrupt-parent = <0x3>;
+	};
+
+	pmu {
+		device_type = "pmu";
+		compatible = "riscv,andes-pmu";
+	};
+
+	virtio_mmio@fe007000 {
+		interrupts = <0x17 0x4>;
+		interrupt-parent = <0x3>;
+		reg = <0x0 0xfe007000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe006000 {
+		interrupts = <0x16 0x4>;
+		interrupt-parent = <0x3>;
+		reg = <0x0 0xfe006000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe005000 {
+		interrupts = <0x15 0x4>;
+		interrupt-parent = <0x3>;
+		reg = <0x0 0xfe005000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe004000 {
+		interrupts = <0x14 0x4>;
+		interrupt-parent = <0x3>;
+		reg = <0x0 0xfe004000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe003000 {
+		interrupts = <0x13 0x4>;
+		interrupt-parent = <0x3>;
+		reg = <0x0 0xfe003000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe002000 {
+		interrupts = <0x12 0x4>;
+		interrupt-parent = <0x3>;
+		reg = <0x0 0xfe002000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe001000 {
+		interrupts = <0x11 0x4>;
+		interrupt-parent = <0x3>;
+		reg = <0x0 0xfe001000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	virtio_mmio@fe000000 {
+		interrupts = <0x10 0x4>;
+		interrupt-parent = <0x3>;
+		reg = <0x0 0xfe000000 0x0 0x1000>;
+		compatible = "virtio,mmio";
+	};
+
+	nor@0,0 {
+		compatible = "cfi-flash";
+		reg = <0x0 0x88000000 0x0 0x1000>;
+		bank-width = <0x2>;
+		device-width = <0x1>;
+	};
+
+	spi@f0b00000 {
+		compatible = "andestech,atcspi200";
+		reg = <0x0 0xf0b00000 0x0 0x1000>;
+		#address-cells = <0x1>;
+		#size-cells = <0x0>;
+		num-cs = <0x1>;
+		clocks = <0x4>;
+		interrupts = <0x4 0x4>;
+		interrupt-parent = <0x3>;
+
+		flash@0 {
+			compatible = "spi-flash";
+			spi-max-frequency = <0x2faf080>;
+			reg = <0x0>;
+			spi-cpol;
+			spi-cpha;
+		};
+	};
+
+	pwm@f0400000 {
+		compatible = "andestech,atcpit100-pwm";
+		reg = <0x0 0xf0400000 0x0 0x1000>;
+		clock-frequency = <0x3938700>;
+		interrupts = <0x3 0x4>;
+		interrupt-parent = <0x3>;
+		pwm-cells = <0x2>;
+	};
+
+	i2c@f0a00000 {
+		compatible = "andestech,atciic100";
+		reg = <0x0 0xf0a00000 0x0 0x1000>;
+		interrupts = <0x6 0x4>;
+		interrupt-parent = <0x3>;
+	};
+
+	aliases {
+		uart0 = "/serial@f0300000";
+		spi0 = "/spi@f0b00000";
+		i2c0 = "/i2c@f0a00000";
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,38400n8 earlycon=sbi debug loglevel=7";
+		stdout-path = "uart0:38400n8";
+	};
+};