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Leo Yu-Chi LiangMina-Chou
Leo Yu-Chi Liang
authored and
Mina-Chou
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riscv: dts: andes: Add ax46mpv and ax66 serires dts support (torvalds#255)
Add ax46mpv and ax66 device tree files Reformed from the following patches on ast-v5_4_0-branch: - (a1f2c9b) rscv: dts: andes: Add DTBs in the Makefile (torvalds#257) Reviewed-on: https://gitea.andestech.com/RD-SW/linux/pulls/255 Reviewed-by: Tim Shih-Ting OuYang <[email protected]> Reviewed-by: randolph <[email protected]>
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‎arch/riscv/boot/dts/andes/Makefile‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,11 @@ dtb-$(CONFIG_ARCH_ANDES) += ax45mpv_c4_d_dsp_ae350.dtb
1717
dtb-$(CONFIG_ARCH_ANDES) += ax45mp_c8_ae350.dtb
1818
dtb-$(CONFIG_ARCH_ANDES) += ax45mpv_c1_d_hvm_ae350.dtb
1919
dtb-$(CONFIG_ARCH_ANDES) += ax45mpv_c2_d_dsp_hvm_ae350.dtb
20+
dtb-$(CONFIG_ARCH_ANDES) += ax46mpv_c1_d_hvm_ae350.dtb
2021

2122
# FPGA : VU19P
22-
dtb-$(CONFIG_ARCH_ANDES) += ax65mp_c2_d_dsp_ae350.dtb
23+
dtb-$(CONFIG_ARCH_ANDES) += ax65_c2_d_ae350.dtb
24+
dtb-$(CONFIG_ARCH_ANDES) += ax66_c1_d_ae350.dtb
25+
dtb-$(CONFIG_ARCH_ANDES) += ax66_c2_d_ae350.dtb
2326

2427
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

‎arch/riscv/boot/dts/andes/ax46mpv_c1_d_hvm_ae350.dts‎

Lines changed: 217 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,217 @@
1+
/dts-v1/;
2+
3+
/ {
4+
#address-cells = <2>;
5+
#size-cells = <2>;
6+
compatible = "andestech,ae350";
7+
model = "andestech,ax45";
8+
aliases {
9+
uart0 = &serial0;
10+
spi0 = &spi;
11+
};
12+
13+
chosen {
14+
bootargs = "console=ttyS0,115200n8 debug loglevel=7 earlycon=sbi";
15+
stdout-path = "uart0:115200n8";
16+
};
17+
cpus {
18+
#address-cells = <1>;
19+
#size-cells = <0>;
20+
timebase-frequency = <60000000>;
21+
CPU0: cpu@0 {
22+
device_type = "cpu";
23+
reg = <0>;
24+
status = "okay";
25+
compatible = "riscv";
26+
riscv,isa = "rv64imafdcv_sscofpmf_svpbmt_zicbom_xandes_xandespmu_xandesvmm";
27+
riscv,cbom-block-size = <64>;
28+
mmu-type = "riscv,sv48";
29+
clock-frequency = <60000000>;
30+
i-cache-size = <0x8000>;
31+
i-cache-sets = <256>;
32+
i-cache-line-size = <64>;
33+
i-cache-block-size = <64>;
34+
d-cache-size = <0x8000>;
35+
d-cache-sets = <128>;
36+
d-cache-line-size = <64>;
37+
d-cache-block-size = <64>;
38+
next-level-cache = <&L2>;
39+
CPU0_intc: interrupt-controller {
40+
#interrupt-cells = <1>;
41+
interrupt-controller;
42+
compatible = "andestech,cpu-intc", "riscv,cpu-intc";
43+
};
44+
};
45+
};
46+
L2: l2-cache@e0500000 {
47+
compatible = "cache";
48+
cache-level = <2>;
49+
cache-size = <0x200000>;
50+
reg = <0x00000000 0xe0500000 0x00000000 0x00010000>;
51+
andes,inst-prefetch = <3>;
52+
andes,data-prefetch = <3>;
53+
// The value format is <XRAMOCTL XRAMICTL>
54+
andes,tag-ram-ctl = <0 0>;
55+
andes,data-ram-ctl = <0 0>;
56+
};
57+
reserved-memory {
58+
#address-cells = <2>;
59+
#size-cells = <2>;
60+
ranges;
61+
62+
hvm0: andes_hvm@90000000 {
63+
compatible = "andestech,hvm";
64+
reg = <0x0 0x90000000 0x0 0x800000>;
65+
andes,hvm_bank = <0x02>;
66+
andes,hvm_subp = <0x01>;
67+
no-map;
68+
};
69+
andes_inject@100000 {
70+
compatible = "inject";
71+
reg = <0x00 0x100000 0x00 0x100000>;
72+
reusable;
73+
};
74+
};
75+
memory@0 {
76+
reg = <0x00000000 0x00000000 0x00000000 0x40000000>;
77+
device_type = "memory";
78+
};
79+
soc {
80+
#address-cells = <2>;
81+
#size-cells = <2>;
82+
compatible = "andestech,riscv-ae350-soc", "simple-bus";
83+
ranges;
84+
plic0: interrupt-controller@e4000000 {
85+
compatible = "riscv,plic0";
86+
reg = <0x00000000 0xe4000000 0x00000000 0x02000000>;
87+
interrupts-extended = < &CPU0_intc 11 &CPU0_intc 9>;
88+
interrupt-controller;
89+
#address-cells = <2>;
90+
#interrupt-cells = <2>;
91+
riscv,ndev = <71>;
92+
};
93+
plic1: interrupt-controller@e6400000 {
94+
compatible = "andestech,plicsw";
95+
reg = <0x00000000 0xe6400000 0x00000000 0x00400000>;
96+
interrupts-extended = < &CPU0_intc 3>;
97+
interrupt-controller;
98+
#address-cells = <2>;
99+
#interrupt-cells = <2>;
100+
riscv,ndev = <1>;
101+
};
102+
plmt0: plmt0@e6000000 {
103+
compatible = "andestech,plmt0";
104+
reg = <0x00000000 0xe6000000 0x00000000 0x00100000>;
105+
interrupts-extended = < &CPU0_intc 7>;
106+
};
107+
spiclk: virt_100mhz {
108+
compatible = "fixed-clock";
109+
#clock-cells = <0>;
110+
clock-frequency = <100000000>;
111+
};
112+
timer0: timer@f0400000 {
113+
compatible = "andestech,atcpit100";
114+
reg = <0x00000000 0xf0400000 0x00000000 0x00001000>;
115+
interrupts = <3 4>;
116+
interrupt-parent = <&plic0>;
117+
clock-frequency = <60000000>;
118+
};
119+
pwm: pwm@f0400000 {
120+
compatible = "andestech,atcpit100-pwm";
121+
reg = <0x00000000 0xf0400000 0x00000000 0x00001000>;
122+
interrupts = <3 4>;
123+
interrupt-parent = <&plic0>;
124+
clock-frequency = <60000000>;
125+
pwm-cells = <2>;
126+
};
127+
wdt: wdt@f0500000 {
128+
compatible = "andestech,atcwdt200";
129+
reg = <0x00000000 0xf0500000 0x00000000 0x00001000>;
130+
interrupts = <3 4>;
131+
interrupt-parent = <&plic0>;
132+
clock-frequency = <60000000>;
133+
};
134+
serial0: serial@f0300000 {
135+
compatible = "andestech,uart16550", "ns16550a";
136+
reg = <0x00000000 0xf0300000 0x00000000 0x00001000>;
137+
interrupts = <9 4>;
138+
interrupt-parent = <&plic0>;
139+
clock-frequency = <19660800>;
140+
current-speed = <115200>;
141+
reg-shift = <2>;
142+
reg-offset = <32>;
143+
reg-io-width = <4>;
144+
no-loopback-test = <1>;
145+
};
146+
rtc0: rtc@f0600000 {
147+
compatible = "andestech,atcrtc100";
148+
reg = <0x00000000 0xf0600000 0x00000000 0x00001000>;
149+
interrupts = <1 4 2 4>;
150+
interrupt-parent = <&plic0>;
151+
wakeup-source;
152+
};
153+
gpio: gpio@f0700000 {
154+
compatible = "andestech,atcgpio100";
155+
reg = <0x00000000 0xf0700000 0x00000000 0x00001000>;
156+
interrupts = <7 4>;
157+
interrupt-parent = <&plic0>;
158+
wakeup-source;
159+
};
160+
mac0: mac@e0100000 {
161+
compatible = "andestech,atmac100";
162+
reg = <0x00000000 0xe0100000 0x00000000 0x00001000>;
163+
interrupts = <19 4>;
164+
interrupt-parent = <&plic0>;
165+
dma-noncoherent;
166+
};
167+
smu: smu@f0100000 {
168+
compatible = "andestech,atcsmu";
169+
reg = <0x00000000 0xf0100000 0x00000000 0x00001000>;
170+
};
171+
mmc0: mmc@f0e00000 {
172+
compatible = "andestech,atfsdc010";
173+
reg = <0x00000000 0xf0e00000 0x00000000 0x00001000>;
174+
interrupts = <18 4>;
175+
interrupt-parent = <&plic0>;
176+
clock-freq-min-max = <400000 100000000>;
177+
max-frequency = <100000000>;
178+
fifo-depth = <16>;
179+
dmas = <&dma0 9>;
180+
dma-names = "rxtx";
181+
dma-noncoherent;
182+
};
183+
dma0: dma@f0c00000 {
184+
compatible = "andestech,atcdmac300";
185+
reg = <0x00000000 0xf0c00000 0x00000000 0x00001000>;
186+
interrupts = <10 4>;
187+
interrupt-parent = <&plic0>;
188+
dma-channels = <8>;
189+
#dma-cells = <1>;
190+
dma-noncoherent;
191+
};
192+
pmu: pmu {
193+
compatible = "riscv,pmu";
194+
device_type = "pmu";
195+
};
196+
spi: spi@f0b00000 {
197+
compatible = "andestech,atcspi200";
198+
reg = <0x00000000 0xf0b00000 0x00000000 0x00001000>;
199+
interrupts = <4 4>;
200+
interrupt-parent = <&plic0>;
201+
#address-cells = <1>;
202+
#size-cells = <0>;
203+
num-cs = <1>;
204+
clocks = <&spiclk>;
205+
dmas = <&dma0 0>, <&dma0 1>;
206+
dma-names = "spi_tx", "spi_rx";
207+
208+
flash@0 {
209+
compatible = "jedec,spi-nor";
210+
reg = <0x00000000>;
211+
spi-max-frequency = <50000000>;
212+
spi-cpol;
213+
spi-cpha;
214+
};
215+
};
216+
};
217+
};

‎arch/riscv/boot/dts/andes/ax65mp_c2_d_dsp_ae350.dts‎ renamed to ‎arch/riscv/boot/dts/andes/ax65_c2_d_ae350.dts‎

File renamed without changes.

‎arch/riscv/boot/dts/andes/ae350-aplic.dts‎ renamed to ‎arch/riscv/boot/dts/andes/ax66_c1_d_ae350.dts‎

Lines changed: 41 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -4,16 +4,15 @@
44
#address-cells = <2>;
55
#size-cells = <2>;
66
compatible = "andestech,ae350";
7-
model = "andestech,ax65";
8-
serial-number = "7066729052";
7+
model = "andestech,ax66";
98
aliases {
109
uart0 = &serial0;
1110
spi0 = &spi;
1211
};
1312

1413
chosen {
15-
bootargs = "console=ttyS0,38400n8 debug loglevel=8 earlycon=sbi initcall_debug";
16-
stdout-path = "uart0:38400n8";
14+
bootargs = "console=ttyS0,115200n8 debug loglevel=7 earlycon=sbi";
15+
stdout-path = "uart0:115200n8";
1716
};
1817
cpus {
1918
#address-cells = <1>;
@@ -24,7 +23,7 @@
2423
reg = <0>;
2524
status = "okay";
2625
compatible = "riscv";
27-
riscv,isa = "rv64imafdc_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zicbom_zkn_zknd_zkne_zknh_zks_zksed_zksh_zkt_smaia_smepmp_smstateen_ssaia_sscofpmf_svinval_svnapot_svpbmt_xandes";
26+
riscv,isa = "rv64imadcbh_zimop_zicond_zihintntl_zifencei_zicntr_zihpm_zicbom_zicbop_zicboz_zfa_zfh_zfbfmin_zawrs_zbc_zcb_zcmop_zbkb_zbkc_zbkx_zkn_zknd_zkne_zknh_zks_zksed_zksh_zkt_smepmp_svinval_svnapot_svpbmt_smstateen_sscofpmf_smaia_ssaia_smcsrind_sscsrind_sstc_ssnpm_smnpm_smmpm_xandes";
2827
riscv,priv-major = <1>;
2928
riscv,priv-minor = <10>;
3029
riscv,cbom-block-size = <64>;
@@ -58,6 +57,24 @@
5857
andes,tag-ram-ctl = <0 0>;
5958
andes,data-ram-ctl = <0 0>;
6059
};
60+
reserved-memory {
61+
#address-cells = <2>;
62+
#size-cells = <2>;
63+
ranges;
64+
65+
hvm0: andes_hvm@90000000 {
66+
compatible = "andestech,hvm";
67+
reg = <0x0 0x90000000 0x0 0x800000>;
68+
andes,hvm_bank = <0x02>;
69+
andes,hvm_subp = <0x01>;
70+
no-map;
71+
};
72+
andes_inject@100000 {
73+
compatible = "inject";
74+
reg = <0x00 0x100000 0x00 0x100000>;
75+
reusable;
76+
};
77+
};
6178
memory@0 {
6279
reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
6380
device_type = "memory";
@@ -67,57 +84,51 @@
6784
#size-cells = <2>;
6885
compatible = "andestech,riscv-ae350-soc", "simple-bus";
6986
ranges;
70-
71-
//APLIC domains forwarding interrupts as MSIs
7287
aplic_m: interrupt-controller@e4400000 {
73-
#address-cells = <2>;
7488
compatible = "riscv,aplic";
7589
msi-parent = <&imsic_mlevel>;
76-
reg = <0x0 0xe4400000 0x0 0x8000>;
90+
reg = <0x00000000 0xe4400000 0x00000000 0x00008000>;
7791
interrupt-controller;
92+
#address-cells = <2>;
7893
#interrupt-cells = <2>;
7994
riscv,num-sources = <31>;
8095
riscv,children = <&aplic_s>;
8196
riscv,delegation = <&aplic_s 1 31>;
8297
};
8398
aplic_s: interrupt-controller@e4408000 {
84-
#address-cells = <2>;
85-
compatible = "riscv,aplic";
99+
compatible = "riscv,aplic";
86100
msi-parent = <&imsic_slevel>;
87-
reg = <0x0 0xe4408000 0x0 0x8000>;
101+
reg = <0x00000000 0xe4408000 0x00000000 0x00008000>;
88102
interrupt-controller;
103+
#address-cells = <2>;
89104
#interrupt-cells = <2>;
90105
riscv,num-sources = <31>;
91106
};
92-
93-
// (Machine-level IMSIC files):
94107
imsic_mlevel: interrupt-controller@c4000000 {
95-
#address-cells = <2>;
96108
compatible = "riscv,imsics";
97-
interrupts-extended = <&CPU0_intc 11>;
98-
reg = <0x0 0xc4000000 0x0 0x100000>;
109+
msi-controller;
110+
reg = <0x00000000 0xc4000000 0x00000000 0x00100000>;
111+
interrupts-extended = < &CPU0_intc 11>;
99112
interrupt-controller;
113+
#address-cells = <2>;
100114
#interrupt-cells = <0>;
101-
msi-controller;
102-
#msi-cells = <0>;
103115
riscv,num-ids = <63>;
116+
#msi-cells = <0>;
104117
};
105-
106-
//(Supervisor-level IMSIC files)
107118
imsic_slevel: interrupt-controller@c4100000 {
108-
#address-cells = <2>;
109119
compatible = "riscv,imsics";
110-
interrupts-extended = <&CPU0_intc 9>;
111-
reg = <0x0 0xc4100000 0x0 0x100000>; /* Group IMSICs */
120+
msi-controller;
121+
reg = <0x00000000 0xc4100000 0x00000000 0x00100000>;
122+
interrupts-extended = < &CPU0_intc 9>;
112123
interrupt-controller;
124+
#address-cells = <2>;
113125
#interrupt-cells = <0>;
114-
msi-controller;
115-
#msi-cells = <0>;
116126
riscv,num-ids = <63>;
117-
riscv,guest-index-bits = <2>; /* GEILEN=3 */
127+
riscv,guest-index-bits = <2>;
128+
#msi-cells = <0>;
118129
};
119130
plmt0: plmt0@e6000000 {
120-
compatible = "riscv,plmt0";
131+
compatible = "andestech,plmt0";
121132
reg = <0x00000000 0xe6000000 0x00000000 0x00100000>;
122133
interrupts-extended = < &CPU0_intc 7>;
123134
};
@@ -186,7 +197,7 @@
186197
reg = <0x00000000 0xf0100000 0x00000000 0x00001000>;
187198
};
188199
mmc0: mmc@f0e00000 {
189-
compatible = "andestech,atfsdc010g";
200+
compatible = "andestech,atfsdc010";
190201
reg = <0x00000000 0xf0e00000 0x00000000 0x00001000>;
191202
interrupts = <18 4>;
192203
interrupt-parent = <&aplic_s>;
@@ -198,7 +209,7 @@
198209
dma-coherent;
199210
};
200211
dma0: dma@f0c00000 {
201-
compatible = "andestech,atcdmac300g";
212+
compatible = "andestech,atcdmac300";
202213
reg = <0x00000000 0xf0c00000 0x00000000 0x00001000>;
203214
interrupts = <10 4>;
204215
interrupt-parent = <&aplic_s>;

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