drivers/iio/adc/ad9361: Misc changes

Verify TX FIR may not work if the filter is disabled.
Preserve XO_BYPASS
For now leave TX CP LEVEL by reset default

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>

Author: mhennerich

drivers/iio/adc/ad9361.c

@@ -1898,7 +1898,9 @@ static int ad9361_txrx_synth_cp_calib(struct ad9361_rf_phy *phy,
 	dev_dbg(&phy->spi->dev, "%s : ref_clk_hz %lu : is_tx %d",
 		__func__, ref_clk_hz, tx);
 
-	ad9361_spi_write(phy->spi, REG_RX_CP_LEVEL_DETECT + offs, 0x17);
+	/* REVIST:
+	 * ad9361_spi_write(phy->spi, REG_RX_CP_LEVEL_DETECT + offs, 0x17);
+	 */
 	ad9361_spi_write(phy->spi, REG_RX_DSM_SETUP_1 + offs, 0x0);
 
 	ad9361_spi_write(phy->spi, REG_RX_LO_GEN_POWER_MODE + offs, 0x00);
@@ -3197,7 +3199,8 @@ static int ad9361_ensm_set_state(struct ad9361_rf_phy *phy, u8 ensm_state,
 		udelay(384000000UL / clk_get_rate(phy->clks[ADC_CLK]));
 		ad9361_spi_write(spi, REG_ENSM_CONFIG_1, 0); /* Move to Wait*/
 		udelay(1); /* Wait for ENSM settle */
-		ad9361_spi_write(spi, REG_CLOCK_ENABLE, 0); /* Turn off all clocks */
+		ad9361_spi_write(spi, REG_CLOCK_ENABLE,
+				 (phy->pdata->use_extclk ? XO_BYPASS : 0)); /* Turn off all clocks */
 		phy->curr_ensm_state = ensm_state;
 		return 0;
 
@@ -3851,6 +3854,7 @@ static int ad9361_setup(struct ad9361_rf_phy *phy)
 			DIGITAL_POWER_UP | CLOCK_ENABLE_DFLT | BBPLL_ENABLE |
 			(pd->use_extclk ? XO_BYPASS : 0)); /* Enable Clocks */
 
+
 	ret = clk_set_rate(phy->clks[BB_REFCLK], ref_freq);
 	if (ret < 0) {
 		dev_err(dev, "Failed to set BB ref clock rate (%d)\n",
@@ -4130,6 +4134,9 @@ static int ad9361_verify_fir_filter_coef(struct ad9361_rf_phy *phy,
 	u32 val, offs = 0, gain = 0, conf, sel, cnt;
 	int ret = 0;
 
+#ifndef DEBUG
+	return 0;
+#endif
 	dev_dbg(&phy->spi->dev, "%s: TAPS %d, dest %d",
 		__func__, ntaps, dest);