Merge branch 'sycl' into global_constructors_wrapper

* sycl:
  [SYCL] Fix test failure due to size discrepancy in 32 and 64 bit environment (intel#2594)
  [BuildBot] Linux GPU driver uplift to 20.39.17972 (intel#2600)
  [SYCL][NFC] Remove cyclic dependency in headers (intel#2601)
  [SYCL][Doc] Fix Sphinx docs index (intel#2599)
  [SYCL][PI][L0] Add an assert to piEnqueueKernelLaunch() when the GlobalWorkOffset!=0 (intel#2593)
  [SYCL][Driver] Turn on -spirv-allow-extra-diexpressions option (intel#2578)
  [SYCL] Serialize queue related PI API in the Level-Zero plugin (intel#2588)
  Added missing math APIs for devicelib. (intel#2558)
  [SYCL][DOC] Fix path to FPGA device selector (intel#2563)
  [SYCL][CUDA] Add basic sub-group functionality (intel#2587)
  [SYCL] Add specialization constant feature design doc. (intel#2572)
  [SYCL] Expand release lit test to CPU and ACC (intel#2589)
  [SYCL] Add clang support for FPGA kernel attribute scheduler_target_fmax_mhz (intel#2511)
  [SYCL][ESIMD] Fixed compiler crash in LowerESIMDVecArg pass (intel#2556)

Author: Alexander Batashev

buildbot/dependency.conf

@@ -4,8 +4,8 @@ ocl_cpu_rt_ver=2020.11.8.0.27
 # https://github.com/intel/llvm/releases/download/2020-WW36/win-oclcpuexp-2020.11.8.0.27_rel.zip
 ocl_cpu_rt_ver_win=2020.11.8.0.27
 # Same GPU driver supports Level Zero and OpenCL:
-# https://github.com/intel/compute-runtime/releases/tag/20.37.17906
-ocl_gpu_rt_ver=20.37.17906
+# https://github.com/intel/compute-runtime/releases/tag/20.39.17972
+ocl_gpu_rt_ver=20.39.17972
 # Same GPU driver supports Level Zero and OpenCL:
 # https://downloadmirror.intel.com/29879/a08/igfx_win10_100.8778.zip
 ocl_gpu_rt_ver_win=27.20.100.8778
@@ -24,7 +24,7 @@ fpga_ver_win=20200811_000006
 [DRIVER VERSIONS]
 cpu_driver_lin=2020.11.8.0.27
 cpu_driver_win=2020.11.8.0.27
-gpu_driver_lin=20.37.17906
+gpu_driver_lin=20.39.17972
 gpu_driver_win=27.20.100.8778
 fpga_driver_lin=2020.11.8.0.27
 fpga_driver_win=2020.11.8.0.27

clang/include/clang/Basic/Attr.td

@@ -1225,6 +1225,24 @@ def SYCLIntelNumSimdWorkItems : InheritableAttr {
   let PragmaAttributeSupport = 0;
 }
 
+def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
+  let Spellings = [CXX11<"intelfpga","scheduler_target_fmax_mhz">];
+  let Args = [ExprArgument<"Value">];
+  let LangOpts = [SYCLIsDevice, SYCLIsHost];
+  let Subjects = SubjectList<[Function], ErrorDiag>;
+  let Documentation = [SYCLIntelSchedulerTargetFmaxMhzAttrDocs];
+  let PragmaAttributeSupport = 0;
+  let AdditionalMembers = [{
+    static unsigned getMinValue() {
+      return 0;
+    }
+    static unsigned getMaxValue() {
+      return 1048576;
+    }
+  }];
+
+}
+
 def SYCLIntelMaxWorkGroupSize : InheritableAttr {
   let Spellings = [CXX11<"intelfpga","max_work_group_size">];
   let Args = [UnsignedArgument<"XDim">,

clang/include/clang/Basic/AttrDocs.td

@@ -2223,6 +2223,28 @@ device kernel, the attribute is ignored and it is not propagated to a kernel.
   }];
 }
 
+def SYCLIntelSchedulerTargetFmaxMhzAttrDocs : Documentation {
+  let Category = DocCatFunction;
+  let Heading = "scheduler_target_fmax_mhz (IntelFPGA)";
+  let Content = [{
+Applies to a device function/lambda function. Indicates that the kernel should
+be pipelined so as to achieve the specified target clock frequency (Fmax) of N
+MHz. The argument N may be a template parameter. This attribute should be
+ignored for the FPGA emulator device.
+
+``[[intelfpga::scheduler_target_fmax_mhz(N)]]``
+Valid values of N are integers in the range [0, 1048576]. The upper limit,
+although too high to be a realistic value for frequency, is chosen to be future
+proof. The FPGA backend emits a diagnostic message if the passed value is
+unachievable by the device.
+
+This attribute enables communication of the desired maximum frequency of the
+device operation, guiding the FPGA backend to insert the appropriate number of
+registers to break-up the combinational logic circuit, and thereby controlling
+the length of the longest combinational path.
+  }];
+}
+
 def SYCLIntelNoGlobalWorkOffsetAttrDocs : Documentation {
   let Category = DocCatFunction;
   let Heading = "no_global_work_offset (IntelFPGA)";

clang/include/clang/Basic/AttributeCommonInfo.h

@@ -162,6 +162,7 @@ class AttributeCommonInfo {
         (ParsedAttr == AT_ReqdWorkGroupSize && isCXX11Attribute()) ||
         (ParsedAttr == AT_IntelReqdSubGroupSize && isCXX11Attribute()) ||
         ParsedAttr == AT_SYCLIntelNumSimdWorkItems ||
+        ParsedAttr == AT_SYCLIntelSchedulerTargetFmaxMhz ||
         ParsedAttr == AT_SYCLIntelMaxWorkGroupSize ||
         ParsedAttr == AT_SYCLIntelMaxGlobalWorkDim ||
         ParsedAttr == AT_SYCLIntelNoGlobalWorkOffset)

clang/include/clang/Sema/Sema.h

@@ -10060,6 +10060,11 @@ class Sema final {
   bool checkAllowedSYCLInitializer(VarDecl *VD,
                                    bool CheckValueDependent = false);
 
+  // Adds a scheduler_target_fmax_mhz attribute to a particular declaration.
+  void addSYCLIntelSchedulerTargetFmaxMhzAttr(Decl *D,
+                                              const AttributeCommonInfo &CI,
+                                              Expr *E);
+
   //===--------------------------------------------------------------------===//
   // C++ Coroutines TS
   //

clang/lib/CodeGen/CodeGenFunction.cpp

@@ -641,6 +641,17 @@ void CodeGenFunction::EmitOpenCLKernelMetadata(const FunctionDecl *FD,
                     llvm::MDNode::get(Context, AttrMDArgs));
   }
 
+  if (const SYCLIntelSchedulerTargetFmaxMhzAttr *A =
+          FD->getAttr<SYCLIntelSchedulerTargetFmaxMhzAttr>()) {
+    Optional<llvm::APSInt> ArgVal =
+        A->getValue()->getIntegerConstantExpr(FD->getASTContext());
+    assert(ArgVal.hasValue() && "Not an integer constant expression");
+    llvm::Metadata *AttrMDArgs[] = {llvm::ConstantAsMetadata::get(
+        Builder.getInt32(ArgVal->getSExtValue()))};
+    Fn->setMetadata("scheduler_target_fmax_mhz",
+                    llvm::MDNode::get(Context, AttrMDArgs));
+  }
+
   if (const SYCLIntelMaxWorkGroupSizeAttr *A =
       FD->getAttr<SYCLIntelMaxWorkGroupSizeAttr>()) {
     llvm::Metadata *AttrMDArgs[] = {

clang/lib/Driver/ToolChains/Clang.cpp

@@ -7826,6 +7826,9 @@ void SPIRVTranslator::ConstructJob(Compilation &C, const JobAction &JA,
   if (getToolChain().getTriple().isSYCLDeviceEnvironment()) {
     TranslatorArgs.push_back("-spirv-max-version=1.1");
     TranslatorArgs.push_back("-spirv-debug-info-version=legacy");
+    // Prevent crash in the translator if input IR contains DIExpression
+    // operations which don't have mapping to OpenCL.DebugInfo.100 spec.
+    TranslatorArgs.push_back("-spirv-allow-extra-diexpressions");
     if (C.getArgs().hasArg(options::OPT_fsycl_esimd))
       TranslatorArgs.push_back("-spirv-allow-unknown-intrinsics");
 

clang/lib/Driver/ToolChains/SYCL.cpp

@@ -43,6 +43,7 @@ const char *SYCL::Linker::constructLLVMSpirvCommand(Compilation &C,
     CmdArgs.push_back("-spirv-max-version=1.1");
     CmdArgs.push_back("-spirv-ext=+all");
     CmdArgs.push_back("-spirv-debug-info-version=legacy");
+    CmdArgs.push_back("-spirv-allow-extra-diexpressions");
     if (C.getArgs().hasArg(options::OPT_fsycl_esimd))
       CmdArgs.push_back("-spirv-allow-unknown-intrinsics");
     CmdArgs.push_back("-o");

clang/lib/Sema/SemaDeclAttr.cpp

@@ -3006,6 +3006,38 @@ static void handleNumSimdWorkItemsAttr(Sema &S, Decl *D,
                                                                      E);
 }
 
+// Add scheduler_target_fmax_mhz
+void Sema::addSYCLIntelSchedulerTargetFmaxMhzAttr(
+    Decl *D, const AttributeCommonInfo &Attr, Expr *E) {
+  assert(E && "Attribute must have an argument.");
+
+  SYCLIntelSchedulerTargetFmaxMhzAttr TmpAttr(Context, Attr, E);
+  if (!E->isValueDependent()) {
+    ExprResult ResultExpr;
+    if (checkRangedIntegralArgument<SYCLIntelSchedulerTargetFmaxMhzAttr>(
+            E, &TmpAttr, ResultExpr))
+      return;
+    E = ResultExpr.get();
+  }
+
+  D->addAttr(::new (Context)
+                 SYCLIntelSchedulerTargetFmaxMhzAttr(Context, Attr, E));
+}
+
+// Handle scheduler_target_fmax_mhz
+static void handleSchedulerTargetFmaxMhzAttr(Sema &S, Decl *D,
+                                             const ParsedAttr &AL) {
+  if (D->isInvalidDecl())
+    return;
+
+  Expr *E = AL.getArgAsExpr(0);
+
+  if (D->getAttr<SYCLIntelSchedulerTargetFmaxMhzAttr>())
+    S.Diag(AL.getLoc(), diag::warn_duplicate_attribute) << AL;
+
+  S.addSYCLIntelSchedulerTargetFmaxMhzAttr(D, AL, E);
+}
+
 // Handles max_global_work_dim.
 static void handleMaxGlobalWorkDimAttr(Sema &S, Decl *D,
                                        const ParsedAttr &Attr) {
@@ -8225,6 +8257,9 @@ static void ProcessDeclAttribute(Sema &S, Scope *scope, Decl *D,
   case ParsedAttr::AT_SYCLIntelNumSimdWorkItems:
     handleNumSimdWorkItemsAttr(S, D, AL);
     break;
+  case ParsedAttr::AT_SYCLIntelSchedulerTargetFmaxMhz:
+    handleSchedulerTargetFmaxMhzAttr(S, D, AL);
+    break;
   case ParsedAttr::AT_SYCLIntelMaxGlobalWorkDim:
     handleMaxGlobalWorkDimAttr(S, D, AL);
     break;

clang/lib/Sema/SemaSYCL.cpp

@@ -531,6 +531,9 @@ class MarkDeviceFunction : public RecursiveASTVisitor<MarkDeviceFunction> {
       if (auto *A = FD->getAttr<SYCLIntelNumSimdWorkItemsAttr>())
         Attrs.insert(A);
 
+      if (auto *A = FD->getAttr<SYCLIntelSchedulerTargetFmaxMhzAttr>())
+        Attrs.insert(A);
+
       if (auto *A = FD->getAttr<SYCLIntelMaxWorkGroupSizeAttr>())
         Attrs.insert(A);
 
@@ -3166,6 +3169,7 @@ void Sema::MarkDevice(void) {
         }
         case attr::Kind::SYCLIntelKernelArgsRestrict:
         case attr::Kind::SYCLIntelNumSimdWorkItems:
+        case attr::Kind::SYCLIntelSchedulerTargetFmaxMhz:
         case attr::Kind::SYCLIntelMaxGlobalWorkDim:
         case attr::Kind::SYCLIntelNoGlobalWorkOffset:
         case attr::Kind::SYCLSimd: {