Correct cleanup of debug code

[pat-pgt]

Hi all,

Is it safe to have some info code for debug in the (VHDL) code?

I define an input signal debug_in and an output signal debug_out. I implement a process containing something like;
wait until debug_in = '1';
report "blabla" severity note;
debug_out <= '1';

The debugs are connected in chain for all the instantiated modules.

• I can have a proper report for simulation. The first debug_in is connected to a signal detecting the end of the simulation.
• For the synthesis, the top level (or under) connects the first debug_in to '0'. Recursively, since each debug_in never reaches '1', all the processes SHOULD be cleaned-up.

Perhaps this discussion shouldn't be here but on the GHDL project. Correct me if I am wrong, Yosys search to fit the design, using the modules described in the selected plug-in (for instance ice40) and generates a net-list. For instance, if a RAM is detected, it uses the one in the plug-in if available. If I write the TTL or 74HC circuits plug-in, it is going to build with gates (and NEXTPNR builds the list for the extravagant PCB)

Regards

[KrystalDelusion]

I'm not sure how Yosys handles the wait until keyword(s); my guess is that either it gives an error about being unsynthesizable, or it might just give a warning and drop the included logic.

[pat-pgt]

I am sorry for the disturbance. This is now closed for me as I can now pass the VHDL 2008 option. This version allows null length arrays. By this way, I can pass a generic/configure/signal that contains the test items list. It is implemented such as "test_instanc : for ind in test_array'range generate ... end generate test_instanc". Then, in production mode, the array is empty and the content of the generate is (I HOPE) discarded.