How to extract an AST tree？

[lijiale6224]

I want the verilog designed AST parsing tree, not the RTLIL that I get directly

[keithpenney]

Yes, I second that. I would also like to extract the AST (even in plain text) rather than the RTLIL. I need vector widths, indices, and slices to be retained in their original form (i.e. expressions involving constants, operators, localparams/parameters, etc). The AST (lexed, parsed, not processed) representation described in the docs sounds perfect, but it looks like it's purely internal and I would need to write a plugin to access this structure.

The output of write_rtlil resolves expressions/parameters/localparams into constant bit widths/indices, and so doesn't meet my needs. Is there any external (serializable) AST representation available at this level?