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Implement sequential placer pass, set up placement pass infrastructure.
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‎include/aie/Dialect/AIE/Transforms/AIEPasses.h‎

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@@ -23,6 +23,7 @@ namespace xilinx::AIE {
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#define GEN_PASS_CLASSES
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#include "aie/Dialect/AIE/Transforms/AIEPasses.h.inc"
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std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIEPlaceTilesPass();
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std::unique_ptr<mlir::OperationPass<DeviceOp>>
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createAIEAssignBufferAddressesPass();
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std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIEAssignLockIDsPass();

‎include/aie/Dialect/AIE/Transforms/AIEPasses.td‎

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include "mlir/Pass/PassBase.td"
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def AIEPlaceTiles : Pass<"aie-place-tiles", "DeviceOp"> {
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let summary = "Place logical tiles onto physical AIE tiles";
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let description = [{
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Sequential placer algorithm places core tiles in a
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column-major order and places fifo-connected Shim/Mem tiles
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near its core tiles. One or more aie.logical_tile operation is mapped
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to one aie.tile.
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}];
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let constructor = "xilinx::AIE::createAIEPlaceTilesPass()";
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let dependentDialects = ["xilinx::AIE::AIEDialect"];
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let options = [
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Option<"clPlacerName", "placer", "std::string",
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/*default=*/"\"sequential_placer\"",
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"Placement algorithm to use (currently only 'sequential_placer')">
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];
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}
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def AIEAssignBufferAddresses : Pass<"aie-assign-buffer-addresses", "DeviceOp"> {
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let summary = "Assign memory locations for buffers in each tile";
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let description = [{

‎include/aie/Dialect/AIE/Transforms/AIEPlacer.h‎

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//===- AIEPlacer.h ----------------------------------------------*- C++ -*-===//
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//
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// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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// (c) Copyright 2024-2026 Advanced Micro Devices, Inc.
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//
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//===----------------------------------------------------------------------===//
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// This file contains the interface for tile placement algorithms.
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// Placers assign physical tile coordinates to logical tiles.
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//===----------------------------------------------------------------------===//
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#ifndef AIE_PLACER_H
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#define AIE_PLACER_H
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#include "aie/Dialect/AIE/IR/AIEDialect.h"
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#include "aie/Dialect/AIE/IR/AIETargetModel.h"
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namespace xilinx::AIE {
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// maps logical tile operations to physical coordinates
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using PlacementResult = llvm::DenseMap<mlir::Operation *, TileID>;
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// Track available tiles and resource usage
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struct TileAvailability {
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std::vector<TileID> compTiles;
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std::vector<TileID> nonCompTiles; // Memory and shim tiles
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llvm::DenseMap<TileID, int> inputChannelsUsed;
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llvm::DenseMap<TileID, int> outputChannelsUsed;
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void removeTile(TileID tile, AIETileType type);
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};
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// Abstract placer interface
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class Placer {
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public:
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Placer() = default;
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virtual ~Placer() = default;
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virtual void initialize(DeviceOp device,
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const AIETargetModel &targetModel) = 0;
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virtual mlir::LogicalResult
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place(llvm::ArrayRef<mlir::Operation *> logicalTiles,
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llvm::ArrayRef<mlir::Operation *> objectFifos,
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llvm::ArrayRef<mlir::Operation *> cores, PlacementResult &result) = 0;
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virtual llvm::StringRef getName() const = 0;
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};
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// Sequential placement algorithm
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//
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// Places logical tiles to physical tiles using a simple strategy:
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// - Compute tiles: Sequential row-major placement
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// - Memory/shim tiles: Channel capacity placement near common column
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//
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// Core-to-core connections are NOT validated because SequentialPlacer
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// doesn't account for shared memory optimization.
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//
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// Shim/Mem tiles with identical placement constraints and sufficient
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// DMA capacity are merged to the same physical tile.
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class SequentialPlacer : public Placer {
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public:
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SequentialPlacer(std::optional<int> coresPerCol = std::nullopt)
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: coresPerCol(coresPerCol) {}
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void initialize(DeviceOp device, const AIETargetModel &targetModel) override;
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mlir::LogicalResult place(llvm::ArrayRef<mlir::Operation *> logicalTiles,
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llvm::ArrayRef<mlir::Operation *> objectFifos,
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llvm::ArrayRef<mlir::Operation *> cores,
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PlacementResult &result) override;
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llvm::StringRef getName() const override { return "sequential_placer"; }
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private:
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std::optional<int> coresPerCol;
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TileAvailability availability;
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const AIETargetModel *targetModel;
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DeviceOp device;
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int getCommonColumn(const PlacementResult &result);
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std::optional<TileID> findTileWithCapacity(int targetCol,
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std::vector<TileID> &tiles,
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int requiredInputChannels,
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int requiredOutputChannels);
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void updateChannelUsage(TileID tile, bool isOutput, int numChannels);
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bool hasAvailableChannels(TileID tile, int inputChannels, int outputChannels);
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mlir::LogicalResult validateAndUpdateChannelUsage(
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LogicalTileOp logicalTile, TileID tile,
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const llvm::DenseMap<mlir::Operation *, std::pair<int, int>>
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&channelRequirements,
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bool isConstrained);
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};
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// PlacementAnalysis integrates the Pathfinder class into the MLIR
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// environment.
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class PlacementAnalysis {
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public:
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PlacementAnalysis() : placer(std::make_shared<SequentialPlacer>()) {}
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explicit PlacementAnalysis(std::shared_ptr<Placer> p)
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: placer(std::move(p)) {}
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mlir::LogicalResult runAnalysis(DeviceOp &device);
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std::optional<TileID> getPlacement(mlir::Operation *logicalTile) const;
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Placer &getPlacer() { return *placer; }
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private:
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std::shared_ptr<Placer> placer;
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PlacementResult result;
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};
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} // namespace xilinx::AIE
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#endif // AIE_PLACER_H

‎lib/Dialect/AIE/Transforms/AIEPlaceTiles.cpp‎

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//===- AIEPlaceTiles.cpp ----------------------------------------*- C++ -*-===//
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//
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// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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// (c) Copyright 2024-2026 Advanced Micro Devices, Inc.
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//
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//===----------------------------------------------------------------------===//
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#include "aie/Dialect/AIE/IR/AIEDialect.h"
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#include "aie/Dialect/AIE/Transforms/AIEPasses.h"
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#include "aie/Dialect/AIE/Transforms/AIEPlacer.h"
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#include "mlir/IR/PatternMatch.h"
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#include "mlir/Transforms/DialectConversion.h"
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#define DEBUG_TYPE "aie-place-tiles"
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using namespace mlir;
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using namespace xilinx;
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using namespace xilinx::AIE;
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namespace {
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struct ConvertLogicalTileToTile : OpConversionPattern<LogicalTileOp> {
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ConvertLogicalTileToTile(MLIRContext *context, DeviceOp &d,
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PlacementAnalysis &a, PatternBenefit benefit = 1)
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: OpConversionPattern(context, benefit), device(d), analyzer(a) {}
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LogicalResult
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matchAndRewrite(LogicalTileOp logicalTile, OpAdaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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// Get pre-computed placement from analysis
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auto placement = analyzer.getPlacement(logicalTile);
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if (!placement) {
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return logicalTile.emitError("no placement found for logical tile");
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}
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// handle merging multiple logical tiles to same physical tile
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TileOp tileOp =
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TileOp::getOrCreate(rewriter, device, placement->col, placement->row);
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// Copy allocation_scheme if present
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if (auto scheme = logicalTile.getAllocationScheme())
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tileOp.setAllocationScheme(scheme);
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// Replace all uses and erase logical tile
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rewriter.replaceOp(logicalTile, tileOp.getResult());
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return success();
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}
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private:
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DeviceOp device;
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PlacementAnalysis &analyzer;
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};
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} // namespace
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struct AIEPlaceTilesPass : AIEPlaceTilesBase<AIEPlaceTilesPass> {
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void runOnOperation() override {
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DeviceOp device = getOperation();
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// Create placer
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std::shared_ptr<Placer> placer;
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if (clPlacerName == "sequential_placer") {
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placer = std::make_shared<SequentialPlacer>();
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} else {
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device.emitError() << "Unknown placer: " << clPlacerName;
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return signalPassFailure();
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}
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// Run placement analysis
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PlacementAnalysis analyzer(placer);
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if (failed(analyzer.runAnalysis(device)))
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return signalPassFailure();
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// Apply placement using conversion pattern
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ConversionTarget target(getContext());
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target.addLegalOp<TileOp>();
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target.addIllegalOp<LogicalTileOp>();
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RewritePatternSet patterns(&getContext());
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patterns.add<ConvertLogicalTileToTile>(device.getContext(), device,
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analyzer);
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if (failed(applyPartialConversion(device, target, std::move(patterns))))
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return signalPassFailure();
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}
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};
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std::unique_ptr<OperationPass<DeviceOp>> AIE::createAIEPlaceTilesPass() {
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return std::make_unique<AIEPlaceTilesPass>();
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}

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