Add tile type filtering to sequential placer to ensure mem/shim tiles are placed correctly.

Co-Authored-By: Claude Opus 4.6 <[email protected]>

Author: yenjames

include/aie/Dialect/AIE/Transforms/AIEPlacer.h

@@ -86,7 +86,8 @@ class SequentialPlacer : public Placer {
   std::optional<TileID> findTileWithCapacity(int targetCol,
                                              std::vector<TileID> &tiles,
                                              int requiredInputChannels,
-                                             int requiredOutputChannels);
+                                             int requiredOutputChannels,
+                                             AIETileType requestedType);
 
   void updateChannelUsage(TileID tile, bool isOutput, int numChannels);
 

lib/Dialect/AIE/Transforms/AIEPlaceTiles.cpp

@@ -80,6 +80,10 @@ struct AIEPlaceTilesPass : AIEPlaceTilesBase<AIEPlaceTilesPass> {
     target.addLegalOp<TileOp>();
     target.addIllegalOp<LogicalTileOp>();
 
+    // Mark all other AIE dialect operations as legal
+    // They will have their operands automatically updated when LogicalTileOp -> TileOp
+    target.addLegalDialect<AIEDialect>();
+
     RewritePatternSet patterns(&getContext());
     patterns.add<ConvertLogicalTileToTile>(device.getContext(), device,
                                            analyzer);

lib/Dialect/AIE/Transforms/AIEPlacer.cpp

@@ -189,8 +189,10 @@ LogicalResult SequentialPlacer::place(ArrayRef<Operation *> logicalTiles,
     }
 
     // Find tile with capacity near common column
+    // Pass tile type to ensure we only search for matching tile types
     auto maybeTile = findTileWithCapacity(commonCol, availability.nonCompTiles,
-                                          numInputChannels, numOutputChannels);
+                                          numInputChannels, numOutputChannels,
+                                          logicalTile.getTileType());
     if (!maybeTile)
       return logicalTile.emitError("no tile with sufficient DMA capacity");
 
@@ -300,12 +302,14 @@ PlacementAnalysis::getPlacement(Operation *logicalTile) const {
 // Find tile with available DMA capacity near target column
 // This function checks capacity for BOTH input and output channels
 // simultaneously. For unidirectional tiles, pass 0 for the unused direction:
-//   - Input-only:  findTileWithCapacity(..., numInputChannels, 0)
-//   - Output-only: findTileWithCapacity(..., 0, numOutputChannels)
-//   - Both: findTileWithCapacity(..., numInputChannels, numOutputChannels)
+//   - Input-only:  findTileWithCapacity(..., numInputChannels, 0, type)
+//   - Output-only: findTileWithCapacity(..., 0, numOutputChannels, type)
+//   - Both: findTileWithCapacity(..., numInputChannels, numOutputChannels, type)
+// The requestedType parameter filters tiles to only consider matching types
+// (e.g., only MemTiles for MemTile logical tiles, only ShimNOCTiles for shims).
 std::optional<TileID> SequentialPlacer::findTileWithCapacity(
     int targetCol, std::vector<TileID> &tiles, int requiredInputChannels,
-    int requiredOutputChannels) {
+    int requiredOutputChannels, AIETileType requestedType) {
   // Search starting from target column, expanding outward
   int maxCol = targetModel->columns();
 
@@ -315,6 +319,11 @@ std::optional<TileID> SequentialPlacer::findTileWithCapacity(
       continue;
 
     for (auto &tile : tiles) {
+      // Filter by tile type - only consider tiles of the requested type
+      AIETileType tileType = targetModel->getTileType(tile.col, tile.row);
+      if (tileType != requestedType)
+        continue;
+
       if (tile.col == searchCol) {
         // Check if tile has capacity for both input and output channels
         if (hasAvailableChannels(tile, requiredInputChannels,

test/place-tiles/sequential_placer/place_tiles_constrained.mlir

@@ -37,11 +37,11 @@ module @mixed_constraints {
     // CHECK-DAG: %[[C1:.*]] = aie.tile(1, 2)
     %c1 = aie.logical_tile<CoreTile>(1, 2)
 
-    // First available should be (0, 2)
+    // First available should be (0, 2) - sequential placement starts at column 0
     // CHECK-DAG: %[[C2:.*]] = aie.tile(0, 2)
     %c2 = aie.logical_tile<CoreTile>(?, ?)
-    // Second available should be (2, 2) (skipping already used (1, 2))
-    // CHECK-DAG: %[[C3:.*]] = aie.tile(2, 2)
+    // Second available should be (0, 3) - column-major sequential (fill column 0 first)
+    // CHECK-DAG: %[[C3:.*]] = aie.tile(0, 3)
     %c3 = aie.logical_tile<CoreTile>(?, ?)
 
     // CHECK: aie.core(%[[C1]])
@@ -61,7 +61,7 @@ module @mixed_constraints {
 // CHECK-LABEL: @constrained_memtile_shimtile
 module @constrained_memtile_shimtile {
   aie.device(npu1) {
-    // CHECK-DAG: %[[CORE:.*]] = aie.tile(1, 2)
+    // CHECK-DAG: %[[CORE:.*]] = aie.tile(0, 2)
     %core = aie.logical_tile<CoreTile>(?, ?)
 
     // MemTile fully constrained to (1, 1)

test/place-tiles/sequential_placer/place_tiles_objectfifo.mlir

@@ -66,7 +66,7 @@ module @multi_consumer {
     %shim = aie.logical_tile<ShimNOCTile>(?, ?)
     // CHECK-DAG: %[[CORE1:.*]] = aie.tile(0, 2)
     %core1 = aie.logical_tile<CoreTile>(?, ?)
-    // CHECK-DAG: %[[CORE2:.*]] = aie.tile(1, 2)
+    // CHECK-DAG: %[[CORE2:.*]] = aie.tile(0, 3)
     %core2 = aie.logical_tile<CoreTile>(?, ?)
 
     // One producer, multiple consumers (needs 2 output channels from shim)