From 3cf190594609183aeb02477d74aa3920374b27a7 Mon Sep 17 00:00:00 2001 From: Devendar Gali Date: Fri, 3 Jan 2025 12:15:44 +0530 Subject: [PATCH 1/8] QDMA Linux reference driver for v2024.1.0 release Signed-off-by: Devendar Gali Signed-off-by: Bharat Kumar Gogada Signed-off-by: Devendar Gali --- QDMA/linux-kernel/LICENSE | 1 + QDMA/linux-kernel/Makefile | 2 +- QDMA/linux-kernel/RELEASE | 22 +- QDMA/linux-kernel/apps/Makefile | 2 +- QDMA/linux-kernel/apps/dma-ctl/Makefile | 2 +- QDMA/linux-kernel/apps/dma-ctl/cmd_parse.c | 10 +- QDMA/linux-kernel/apps/dma-ctl/cmd_parse.h | 2 +- QDMA/linux-kernel/apps/dma-ctl/main.c | 2 +- QDMA/linux-kernel/apps/dma-ctl/version.h | 6 +- .../apps/dma-from-device/dma_from_device.c | 2 +- .../apps/dma-from-device/version.h | 6 +- QDMA/linux-kernel/apps/dma-latency/Makefile | 2 +- QDMA/linux-kernel/apps/dma-latency/Readme.txt | 2 +- QDMA/linux-kernel/apps/dma-latency/dmalat.c | 2 +- .../dma-latency/sample_dma_latency_config.txt | 2 +- QDMA/linux-kernel/apps/dma-latency/version.h | 6 +- QDMA/linux-kernel/apps/dma-perf/Makefile | 2 +- QDMA/linux-kernel/apps/dma-perf/dmaperf.c | 20 +- QDMA/linux-kernel/apps/dma-perf/version.h | 6 +- QDMA/linux-kernel/apps/dma-to-device/Makefile | 2 +- .../apps/dma-to-device/dma_to_device.c | 2 +- .../linux-kernel/apps/dma-to-device/version.h | 6 +- QDMA/linux-kernel/apps/dma-utils/Makefile | 2 +- .../apps/dma-utils/dma_xfer_utils.c | 2 +- QDMA/linux-kernel/apps/dma-utils/dmactl.c | 2 +- .../apps/dma-utils/dmactl_internal.h | 1 + QDMA/linux-kernel/apps/dma-utils/dmactl_reg.c | 5 +- QDMA/linux-kernel/apps/dma-utils/dmautils.c | 1 + QDMA/linux-kernel/apps/dma-utils/dmautils.h | 1 + QDMA/linux-kernel/apps/dma-utils/dmaxfer.c | 2 +- QDMA/linux-kernel/apps/dma-utils/dmaxfer.h | 1 + QDMA/linux-kernel/apps/dma-utils/version.h | 6 +- QDMA/linux-kernel/apps/dma-xfer/Makefile | 2 +- QDMA/linux-kernel/apps/dma-xfer/dmaxfer.c | 2 +- .../apps/dma-xfer/sample_qdma_xfer_config.txt | 2 +- QDMA/linux-kernel/apps/dma-xfer/version.h | 6 +- QDMA/linux-kernel/apps/include/qdma_nl.h | 2 +- .../apps/include/qdma_user_reg_dump.h | 2 +- QDMA/linux-kernel/apps/include/xdev_regs.h | 2 +- QDMA/linux-kernel/bsd_license.txt | 2 +- QDMA/linux-kernel/docs/README | 2 +- QDMA/linux-kernel/driver/Makefile | 2 +- QDMA/linux-kernel/driver/include/qdma_nl.h | 2 +- .../driver/include/qdma_user_reg_dump.h | 2 +- QDMA/linux-kernel/driver/include/xdev_regs.h | 2 +- QDMA/linux-kernel/driver/libqdma/Makefile | 2 +- .../driver/libqdma/libqdma_config.c | 2 +- .../driver/libqdma/libqdma_config.h | 6 +- .../driver/libqdma/libqdma_export.c | 2 +- .../driver/libqdma/libqdma_export.h | 2 +- .../eqdma_cpm5_access/eqdma_cpm5_access.c | 207 +++++++++++------- .../eqdma_cpm5_access/eqdma_cpm5_access.h | 10 +- .../eqdma_cpm5_access/eqdma_cpm5_reg.h | 4 +- .../eqdma_cpm5_access/eqdma_cpm5_reg_dump.c | 3 +- .../eqdma_soft_access/eqdma_soft_access.c | 196 ++++++++++------- .../eqdma_soft_access/eqdma_soft_access.h | 10 +- .../eqdma_soft_access/eqdma_soft_reg.h | 4 +- .../eqdma_soft_access/eqdma_soft_reg_dump.c | 3 +- .../libqdma/qdma_access/qdma_access_common.c | 33 ++- .../libqdma/qdma_access/qdma_access_common.h | 118 +++++----- .../libqdma/qdma_access/qdma_access_errors.h | 2 +- .../libqdma/qdma_access/qdma_access_export.h | 2 +- .../libqdma/qdma_access/qdma_access_version.h | 8 +- .../qdma_cpm4_access/qdma_cpm4_access.c | 142 +++++++----- .../qdma_cpm4_access/qdma_cpm4_access.h | 9 +- .../qdma_cpm4_access/qdma_cpm4_reg.h | 4 +- .../qdma_cpm4_access/qdma_cpm4_reg_dump.c | 3 +- .../driver/libqdma/qdma_access/qdma_list.c | 2 +- .../driver/libqdma/qdma_access/qdma_list.h | 2 +- .../libqdma/qdma_access/qdma_mbox_protocol.c | 39 ++-- .../libqdma/qdma_access/qdma_mbox_protocol.h | 2 +- .../libqdma/qdma_access/qdma_platform.h | 2 +- .../libqdma/qdma_access/qdma_reg_dump.h | 2 +- .../libqdma/qdma_access/qdma_resource_mgmt.c | 2 +- .../libqdma/qdma_access/qdma_resource_mgmt.h | 2 +- .../qdma_soft_access/qdma_soft_access.c | 139 +++++++----- .../qdma_soft_access/qdma_soft_access.h | 2 +- .../qdma_soft_access/qdma_soft_reg.h | 2 +- .../linux-kernel/driver/libqdma/qdma_compat.h | 2 +- .../driver/libqdma/qdma_context.c | 35 +-- .../driver/libqdma/qdma_context.h | 2 +- .../driver/libqdma/qdma_debugfs.c | 2 +- .../driver/libqdma/qdma_debugfs.h | 2 +- .../driver/libqdma/qdma_debugfs_dev.c | 2 +- .../driver/libqdma/qdma_debugfs_dev.h | 2 +- .../driver/libqdma/qdma_debugfs_queue.c | 2 +- .../driver/libqdma/qdma_debugfs_queue.h | 2 +- QDMA/linux-kernel/driver/libqdma/qdma_descq.c | 34 ++- QDMA/linux-kernel/driver/libqdma/qdma_descq.h | 2 +- .../linux-kernel/driver/libqdma/qdma_device.c | 2 +- .../linux-kernel/driver/libqdma/qdma_device.h | 2 +- QDMA/linux-kernel/driver/libqdma/qdma_intr.c | 18 +- QDMA/linux-kernel/driver/libqdma/qdma_intr.h | 2 +- .../driver/libqdma/qdma_license.h | 2 +- QDMA/linux-kernel/driver/libqdma/qdma_mbox.c | 8 +- QDMA/linux-kernel/driver/libqdma/qdma_mbox.h | 4 +- .../driver/libqdma/qdma_platform.c | 2 +- .../driver/libqdma/qdma_platform_env.h | 2 +- QDMA/linux-kernel/driver/libqdma/qdma_regs.c | 2 +- QDMA/linux-kernel/driver/libqdma/qdma_regs.h | 2 +- QDMA/linux-kernel/driver/libqdma/qdma_sriov.c | 2 +- .../linux-kernel/driver/libqdma/qdma_st_c2h.c | 2 +- .../linux-kernel/driver/libqdma/qdma_st_c2h.h | 2 +- .../linux-kernel/driver/libqdma/qdma_thread.c | 2 +- .../linux-kernel/driver/libqdma/qdma_thread.h | 2 +- .../linux-kernel/driver/libqdma/qdma_ul_ext.h | 2 +- QDMA/linux-kernel/driver/libqdma/thread.c | 2 +- QDMA/linux-kernel/driver/libqdma/thread.h | 2 +- QDMA/linux-kernel/driver/libqdma/version.h | 6 +- QDMA/linux-kernel/driver/libqdma/xdev.c | 33 ++- QDMA/linux-kernel/driver/libqdma/xdev.h | 14 +- .../driver/make_rules/common_flags.mk | 2 +- .../driver/make_rules/distro_check.mk | 6 +- .../driver/make_rules/kernel_check.mk | 2 +- QDMA/linux-kernel/driver/src/Makefile | 2 +- QDMA/linux-kernel/driver/src/cdev.c | 58 ++++- QDMA/linux-kernel/driver/src/cdev.h | 4 +- QDMA/linux-kernel/driver/src/nl.c | 25 ++- QDMA/linux-kernel/driver/src/nl.h | 2 +- QDMA/linux-kernel/driver/src/pci_ids.h | 2 +- QDMA/linux-kernel/driver/src/qdma_mod.c | 6 +- QDMA/linux-kernel/driver/src/qdma_mod.h | 2 +- QDMA/linux-kernel/driver/src/version.h | 8 +- .../license-for-datafile_16bit_pattern.txt | 3 +- .../scripts/qdma_generate_conf_file.sh | 2 +- .../scripts/qdma_run_test_mm_vf.sh | 2 +- QDMA/linux-kernel/scripts/qdma_run_test_pf.sh | 2 +- .../scripts/qdma_run_test_st_vf.sh | 2 +- QDMA/linux-kernel/scripts/qdma_vf_auto_tst.sh | 2 +- 129 files changed, 889 insertions(+), 575 deletions(-) diff --git a/QDMA/linux-kernel/LICENSE b/QDMA/linux-kernel/LICENSE index 94e1237b..8df76ac0 100755 --- a/QDMA/linux-kernel/LICENSE +++ b/QDMA/linux-kernel/LICENSE @@ -3,6 +3,7 @@ BSD License For Xilinx DMA IP software Copyright (c) 2016-2022 Xilinx, Inc. All rights reserved. +Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/QDMA/linux-kernel/Makefile b/QDMA/linux-kernel/Makefile index 53b933d7..08340f69 100755 --- a/QDMA/linux-kernel/Makefile +++ b/QDMA/linux-kernel/Makefile @@ -2,7 +2,7 @@ # * This file is part of the Xilinx DMA IP Core driver for Linux # * # * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is free software; you can redistribute it and/or modify it # * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/RELEASE b/QDMA/linux-kernel/RELEASE index 39807d72..d1222b9b 100755 --- a/QDMA/linux-kernel/RELEASE +++ b/QDMA/linux-kernel/RELEASE @@ -1,3 +1,11 @@ +RELEASE: 2024.1.0 +================= + +This release is validated + - On VCU118 for QDMA5.0 2022.1 example design + - On XCVP1202 for CPM5 2022.1 example design + - On XCVC1902 for CPM4 2022.1 example design + RELEASE: 2023.2.1 ================= @@ -153,6 +161,14 @@ CPM5 ---------------- - Added driver support to enable 10 bit tag for CPM5 design. +2024.1.0 Updates +---------------- +- Added support for kernel version 6.4.x. +- Added support for Fedora40 & Centos-Stream9 distros. +- Added support for AlmaLinux 9.4 +- Reduced descriptor data transfer length to 32KB for EQDMA Soft 5.0 design. +- Fixed bugs in driver. + KNOWN ISSUES: ============= - CPM4 Only @@ -180,8 +196,8 @@ DRIVER LIMITATIONS: - For optimal QDMA streaming performance, packet buffers of the descriptor ring should be aligned to at least 256 bytes. - FLR is not supported in the Driver for CentOS because linux kernels provided in CentOS versions does not support the driver call back registration for FLR functionality -- XRT Only - - QDMA: Bypass user BAR check for XRT application +- EQDMA Soft IP 5.0 + - QDMA: Fix user BAR check issue - The existing driver code assmues the presence of the user BAR as indicated in the functional example design. If this user BAR is not detected during the driver probing process, it results in a failure. However, this check is specific to example design and some customer designs might not contain user BAR. So bypassing the user BAR check to prevent driver returning error and proceed further. @@ -192,7 +208,7 @@ DRIVER LIMITATIONS: * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/apps/Makefile b/QDMA/linux-kernel/apps/Makefile index 9b7e9875..b9a4fbc7 100755 --- a/QDMA/linux-kernel/apps/Makefile +++ b/QDMA/linux-kernel/apps/Makefile @@ -4,7 +4,7 @@ # * to enable the user to execute the QDMA functionality # * # * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is licensed under BSD-style license (found in the # * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-ctl/Makefile b/QDMA/linux-kernel/apps/dma-ctl/Makefile index ef55091f..970f94c7 100755 --- a/QDMA/linux-kernel/apps/dma-ctl/Makefile +++ b/QDMA/linux-kernel/apps/dma-ctl/Makefile @@ -4,7 +4,7 @@ # * to enable the user to execute the QDMA functionality # * # * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is licensed under BSD-style license (found in the # * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.c b/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.c index 18ecd7b6..d427112f 100755 --- a/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.c +++ b/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.c @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) @@ -29,6 +29,12 @@ static int read_range(int argc, char *argv[], int i, unsigned int *v1, static const char *progname; #define DESC_SIZE_64B 3 +#ifdef CONFIG_PCI_DOMAINS_GENERIC +#define BUS_DEVICE_FUNC_MAX_LEN 15 +#else +#define BUS_DEVICE_FUNC_MAX_LEN 11 +#endif + #define Q_ADD_ATTR_IGNORE_MASK ~((1 << QPARM_IDX) | \ (1 << QPARM_MODE) | \ (1 << QPARM_DIR)) @@ -271,7 +277,7 @@ static int parse_ifname(char *name, struct xcmd_info *xcmd) char *p; /* qdmaN of qdmavfN*/ - if (len > 11) { + if (len > BUS_DEVICE_FUNC_MAX_LEN) { warnx("interface name %s too long, expect qdma.\n", name); return -EINVAL; } diff --git a/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.h b/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.h index ecd9224d..632aa20b 100755 --- a/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.h +++ b/QDMA/linux-kernel/apps/dma-ctl/cmd_parse.h @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-ctl/main.c b/QDMA/linux-kernel/apps/dma-ctl/main.c index 2a80961e..d6ddfe27 100755 --- a/QDMA/linux-kernel/apps/dma-ctl/main.c +++ b/QDMA/linux-kernel/apps/dma-ctl/main.c @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-ctl/version.h b/QDMA/linux-kernel/apps/dma-ctl/version.h index e01b78a8..cb18694a 100755 --- a/QDMA/linux-kernel/apps/dma-ctl/version.h +++ b/QDMA/linux-kernel/apps/dma-ctl/version.h @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) @@ -13,7 +13,7 @@ #define __DMA_CTL_VERSION_H #define PROGNAME "dma-ctl" -#define VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." +#define VERSION "2024.1.0" +#define COPYRIGHT "Copyright (c) 2022-2024 Advanced Micro Devices Inc." #endif diff --git a/QDMA/linux-kernel/apps/dma-from-device/dma_from_device.c b/QDMA/linux-kernel/apps/dma-from-device/dma_from_device.c index fe347575..c4fc53fe 100755 --- a/QDMA/linux-kernel/apps/dma-from-device/dma_from_device.c +++ b/QDMA/linux-kernel/apps/dma-from-device/dma_from_device.c @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-from-device/version.h b/QDMA/linux-kernel/apps/dma-from-device/version.h index 9eeb7848..fc7bd993 100755 --- a/QDMA/linux-kernel/apps/dma-from-device/version.h +++ b/QDMA/linux-kernel/apps/dma-from-device/version.h @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) @@ -13,7 +13,7 @@ #define __DMA_FROM_DEVICE_VERSION_H #define PROGNAME "dma-from-device" -#define VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." +#define VERSION "2024.1.0" +#define COPYRIGHT "Copyright (c) 2022-2024 Advanced Micro Devices Inc." #endif diff --git a/QDMA/linux-kernel/apps/dma-latency/Makefile b/QDMA/linux-kernel/apps/dma-latency/Makefile index 56549730..7366be3a 100755 --- a/QDMA/linux-kernel/apps/dma-latency/Makefile +++ b/QDMA/linux-kernel/apps/dma-latency/Makefile @@ -4,7 +4,7 @@ # * to enable the user to execute the QDMA functionality # * # * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is licensed under BSD-style license (found in the # * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-latency/Readme.txt b/QDMA/linux-kernel/apps/dma-latency/Readme.txt index 9c07c2c8..56e66d4e 100755 --- a/QDMA/linux-kernel/apps/dma-latency/Readme.txt +++ b/QDMA/linux-kernel/apps/dma-latency/Readme.txt @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under both the BSD-style license (found in the * LICENSE file in the root directory of this source tree) and the GPLv2 (found diff --git a/QDMA/linux-kernel/apps/dma-latency/dmalat.c b/QDMA/linux-kernel/apps/dma-latency/dmalat.c index 98c157ba..b98ab3a1 100755 --- a/QDMA/linux-kernel/apps/dma-latency/dmalat.c +++ b/QDMA/linux-kernel/apps/dma-latency/dmalat.c @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-latency/sample_dma_latency_config.txt b/QDMA/linux-kernel/apps/dma-latency/sample_dma_latency_config.txt index f7108450..0bf0fa27 100755 --- a/QDMA/linux-kernel/apps/dma-latency/sample_dma_latency_config.txt +++ b/QDMA/linux-kernel/apps/dma-latency/sample_dma_latency_config.txt @@ -4,7 +4,7 @@ # * to enable the user to execute the QDMA functionality # * # * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is licensed under BSD-style license (found in the # * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-latency/version.h b/QDMA/linux-kernel/apps/dma-latency/version.h index 650deb97..2a694ee4 100755 --- a/QDMA/linux-kernel/apps/dma-latency/version.h +++ b/QDMA/linux-kernel/apps/dma-latency/version.h @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) @@ -13,7 +13,7 @@ #define __DMA_LATENCY_VERSION_H #define PROGNAME "dma-latency" -#define VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." +#define VERSION "2024.1.0" +#define COPYRIGHT "Copyright (c) 2022-2024 Advanced Micro Devices Inc." #endif diff --git a/QDMA/linux-kernel/apps/dma-perf/Makefile b/QDMA/linux-kernel/apps/dma-perf/Makefile index 34ba4846..094d393a 100755 --- a/QDMA/linux-kernel/apps/dma-perf/Makefile +++ b/QDMA/linux-kernel/apps/dma-perf/Makefile @@ -4,7 +4,7 @@ # * to enable the user to execute the QDMA functionality # * # * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is licensed under BSD-style license (found in the # * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-perf/dmaperf.c b/QDMA/linux-kernel/apps/dma-perf/dmaperf.c index 1d9638e0..17196c4f 100755 --- a/QDMA/linux-kernel/apps/dma-perf/dmaperf.c +++ b/QDMA/linux-kernel/apps/dma-perf/dmaperf.c @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) @@ -319,8 +319,8 @@ static int arg_read_int_array(char *s, unsigned int *v, unsigned int max_arr_siz char *elem; int cnt = 0; - memset(str, '\0', slen + 1); - strncpy(str, s + 1, slen - trail_blanks - 2); + memset(str, '\0', slen - trail_blanks + 1); + strncpy(str, s + 1, slen - trail_blanks - 1); str[slen] = '\0'; elem = strtok(str, " ,");/* space or comma separated */ @@ -781,6 +781,7 @@ static void parse_config_file(const char *cfg_fname) char rng_sz[100] = {'\0'}; char rng_sz_path[200] = {'\0'}; int rng_sz_fd, ret = 0; + struct stat st; fp = fopen(cfg_fname, "r"); if (fp == NULL) @@ -804,7 +805,7 @@ static void parse_config_file(const char *cfg_fname) else if(!strncmp(value, "st", 2)) mode = Q_MODE_ST; else { - printf("Error: Unkown mode"); + printf("Error: Unknown mode\n"); goto prase_cleanup; } } else if (!strncmp(config, "dir", 3)) { @@ -815,7 +816,7 @@ static void parse_config_file(const char *cfg_fname) else if(!strncmp(value, "bi", 2)) dir = Q_DIR_BI; else { - printf("Error: Unkown dir"); + printf("Error: Unknown dir\n"); goto prase_cleanup; } } else if (!strncmp(config, "name", 3)) { @@ -1089,6 +1090,12 @@ static void parse_config_file(const char *cfg_fname) system(rng_sz_path); snprintf(rng_sz_path, 200, "glbl_rng_sz"); + stat(rng_sz_path, &st); + if (st.st_size == 0) { + printf("Error: Global csr get failed\n"); + exit(1); + } + rng_sz_fd = open(rng_sz_path, O_RDONLY); if (rng_sz_fd < 0) { printf("Could not open %s\n", rng_sz_path); @@ -1123,6 +1130,7 @@ static void parse_config_file(const char *cfg_fname) prase_cleanup: fclose(fp); + exit(1); } #define MAX_AIO_EVENTS 65536 @@ -1738,7 +1746,7 @@ static void io_proc_cleanup(struct io_info *_info) { unsigned int i; unsigned int q_offset; - unsigned int dir_factor = (dir == Q_DIR_BI) ? 1 : 2; + unsigned int dir_factor = (dir == Q_DIR_BI) ? 2 : 1; unsigned int q_lst_idx_base; unsigned char is_q_stop = (_info->q_ctrl && _info->q_started); int reg_value = 0; diff --git a/QDMA/linux-kernel/apps/dma-perf/version.h b/QDMA/linux-kernel/apps/dma-perf/version.h index 53a766a5..4a226478 100755 --- a/QDMA/linux-kernel/apps/dma-perf/version.h +++ b/QDMA/linux-kernel/apps/dma-perf/version.h @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) @@ -13,7 +13,7 @@ #define __DMA_PERF_VERSION_H #define PROGNAME "dma-perf" -#define VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." +#define VERSION "2024.1.0" +#define COPYRIGHT "Copyright (c) 2022-2024 Advanced Micro Devices Inc." #endif diff --git a/QDMA/linux-kernel/apps/dma-to-device/Makefile b/QDMA/linux-kernel/apps/dma-to-device/Makefile index bccb8346..800ffa8f 100755 --- a/QDMA/linux-kernel/apps/dma-to-device/Makefile +++ b/QDMA/linux-kernel/apps/dma-to-device/Makefile @@ -4,7 +4,7 @@ # * to enable the user to execute the QDMA functionality # * # * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is licensed under BSD-style license (found in the # * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-to-device/dma_to_device.c b/QDMA/linux-kernel/apps/dma-to-device/dma_to_device.c index 49d53b0c..8b70a0ed 100755 --- a/QDMA/linux-kernel/apps/dma-to-device/dma_to_device.c +++ b/QDMA/linux-kernel/apps/dma-to-device/dma_to_device.c @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-to-device/version.h b/QDMA/linux-kernel/apps/dma-to-device/version.h index b14cefc1..14a8dd9f 100755 --- a/QDMA/linux-kernel/apps/dma-to-device/version.h +++ b/QDMA/linux-kernel/apps/dma-to-device/version.h @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) @@ -13,7 +13,7 @@ #define __DMA_TO_DEVICE_VERSION_H #define PROGNAME "dma-to-device" -#define VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." +#define VERSION "2024.1.0" +#define COPYRIGHT "Copyright (c) 2022-2024 Advanced Micro Devices Inc." #endif diff --git a/QDMA/linux-kernel/apps/dma-utils/Makefile b/QDMA/linux-kernel/apps/dma-utils/Makefile index f6d9ecd1..9534b840 100755 --- a/QDMA/linux-kernel/apps/dma-utils/Makefile +++ b/QDMA/linux-kernel/apps/dma-utils/Makefile @@ -4,7 +4,7 @@ # * to enable the user to execute the QDMA functionality # * # * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is licensed under BSD-style license (found in the # * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-utils/dma_xfer_utils.c b/QDMA/linux-kernel/apps/dma-utils/dma_xfer_utils.c index d3fefd26..3d051506 100755 --- a/QDMA/linux-kernel/apps/dma-utils/dma_xfer_utils.c +++ b/QDMA/linux-kernel/apps/dma-utils/dma_xfer_utils.c @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-utils/dmactl.c b/QDMA/linux-kernel/apps/dma-utils/dmactl.c index 988d482e..88efd220 100755 --- a/QDMA/linux-kernel/apps/dma-utils/dmactl.c +++ b/QDMA/linux-kernel/apps/dma-utils/dmactl.c @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-utils/dmactl_internal.h b/QDMA/linux-kernel/apps/dma-utils/dmactl_internal.h index 7283f7cc..7b419141 100755 --- a/QDMA/linux-kernel/apps/dma-utils/dmactl_internal.h +++ b/QDMA/linux-kernel/apps/dma-utils/dmactl_internal.h @@ -4,6 +4,7 @@ * * Copyright (c) 2019 - 2022, Xilinx, Inc. * All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-utils/dmactl_reg.c b/QDMA/linux-kernel/apps/dma-utils/dmactl_reg.c index 549d67af..a696dade 100755 --- a/QDMA/linux-kernel/apps/dma-utils/dmactl_reg.c +++ b/QDMA/linux-kernel/apps/dma-utils/dmactl_reg.c @@ -4,6 +4,7 @@ * * Copyright (c) 2019 - 2022, Xilinx, Inc. * All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) @@ -204,8 +205,8 @@ static void print_repeated_reg(uint32_t *bar, struct xreg_info *xreg, for (i = start; i < end; i++) { uint32_t addr = xreg->addr + (i * step); - char name[40]; - snprintf(name, 40, "%s_%d", + char name[45]; + snprintf(name, 45, "%s_%d", xreg->name, i); if (xcmd == NULL) { diff --git a/QDMA/linux-kernel/apps/dma-utils/dmautils.c b/QDMA/linux-kernel/apps/dma-utils/dmautils.c index 358530bc..27e01e07 100755 --- a/QDMA/linux-kernel/apps/dma-utils/dmautils.c +++ b/QDMA/linux-kernel/apps/dma-utils/dmautils.c @@ -4,6 +4,7 @@ * * Copyright (c) 2019 - 2022, Xilinx, Inc. * All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-utils/dmautils.h b/QDMA/linux-kernel/apps/dma-utils/dmautils.h index 2df9416a..de661fd8 100755 --- a/QDMA/linux-kernel/apps/dma-utils/dmautils.h +++ b/QDMA/linux-kernel/apps/dma-utils/dmautils.h @@ -4,6 +4,7 @@ * * Copyright (c) 2019 - 2020, Xilinx, Inc. * All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-utils/dmaxfer.c b/QDMA/linux-kernel/apps/dma-utils/dmaxfer.c index b0c9b8ea..b476e151 100755 --- a/QDMA/linux-kernel/apps/dma-utils/dmaxfer.c +++ b/QDMA/linux-kernel/apps/dma-utils/dmaxfer.c @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-utils/dmaxfer.h b/QDMA/linux-kernel/apps/dma-utils/dmaxfer.h index 0dda0d1d..e35d22d1 100755 --- a/QDMA/linux-kernel/apps/dma-utils/dmaxfer.h +++ b/QDMA/linux-kernel/apps/dma-utils/dmaxfer.h @@ -4,6 +4,7 @@ * * Copyright (c) 2019 - 2022, Xilinx, Inc. * All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-utils/version.h b/QDMA/linux-kernel/apps/dma-utils/version.h index 7e540efc..1547701e 100755 --- a/QDMA/linux-kernel/apps/dma-utils/version.h +++ b/QDMA/linux-kernel/apps/dma-utils/version.h @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) @@ -13,7 +13,7 @@ #define __DMA_UTILS_VERSION_H #define LIBNAME "dma-utils" -#define QDMATUILS_VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." +#define QDMATUILS_VERSION "2024.1.0" +#define COPYRIGHT "Copyright (c) 2022-2024 Advanced Micro Devices Inc." #endif diff --git a/QDMA/linux-kernel/apps/dma-xfer/Makefile b/QDMA/linux-kernel/apps/dma-xfer/Makefile index f30478ae..acb97f75 100755 --- a/QDMA/linux-kernel/apps/dma-xfer/Makefile +++ b/QDMA/linux-kernel/apps/dma-xfer/Makefile @@ -4,7 +4,7 @@ # * to enable the user to execute the QDMA functionality # * # * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is licensed under BSD-style license (found in the # * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-xfer/dmaxfer.c b/QDMA/linux-kernel/apps/dma-xfer/dmaxfer.c index 23945bd3..41457277 100755 --- a/QDMA/linux-kernel/apps/dma-xfer/dmaxfer.c +++ b/QDMA/linux-kernel/apps/dma-xfer/dmaxfer.c @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-xfer/sample_qdma_xfer_config.txt b/QDMA/linux-kernel/apps/dma-xfer/sample_qdma_xfer_config.txt index d4a2c828..90f8ce98 100755 --- a/QDMA/linux-kernel/apps/dma-xfer/sample_qdma_xfer_config.txt +++ b/QDMA/linux-kernel/apps/dma-xfer/sample_qdma_xfer_config.txt @@ -4,7 +4,7 @@ # * to enable the user to execute the QDMA functionality # * # * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is licensed under BSD-style license (found in the # * LICENSE file in the root directory of this source tree) diff --git a/QDMA/linux-kernel/apps/dma-xfer/version.h b/QDMA/linux-kernel/apps/dma-xfer/version.h index 31e86544..030757b1 100755 --- a/QDMA/linux-kernel/apps/dma-xfer/version.h +++ b/QDMA/linux-kernel/apps/dma-xfer/version.h @@ -3,7 +3,7 @@ * to enable the user to execute the QDMA functionality * * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under BSD-style license (found in the * LICENSE file in the root directory of this source tree) @@ -12,7 +12,7 @@ #define __DMA_XFER_VERSION_H #define PROGNAME "dma-xfer" -#define VERSION "2023.2.0" -#define COPYRIGHT "Copyright (c) 2022-2023 Advanced Micro Devices Inc." +#define VERSION "2024.1.0" +#define COPYRIGHT "Copyright (c) 2022-2024 Advanced Micro Devices Inc." #endif diff --git a/QDMA/linux-kernel/apps/include/qdma_nl.h b/QDMA/linux-kernel/apps/include/qdma_nl.h index fd8b43cd..cb12294e 100755 --- a/QDMA/linux-kernel/apps/include/qdma_nl.h +++ b/QDMA/linux-kernel/apps/include/qdma_nl.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under both the BSD-style license (found in the * LICENSE file in the root directory of this source tree) and the GPLv2 (found diff --git a/QDMA/linux-kernel/apps/include/qdma_user_reg_dump.h b/QDMA/linux-kernel/apps/include/qdma_user_reg_dump.h index 4e833732..b0a197f9 100755 --- a/QDMA/linux-kernel/apps/include/qdma_user_reg_dump.h +++ b/QDMA/linux-kernel/apps/include/qdma_user_reg_dump.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under both the BSD-style license (found in the * LICENSE file in the root directory of this source tree) and the GPLv2 (found diff --git a/QDMA/linux-kernel/apps/include/xdev_regs.h b/QDMA/linux-kernel/apps/include/xdev_regs.h index 1434dce3..fcfceaf9 100755 --- a/QDMA/linux-kernel/apps/include/xdev_regs.h +++ b/QDMA/linux-kernel/apps/include/xdev_regs.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under both the BSD-style license (found in the * LICENSE file in the root directory of this source tree) and the GPLv2 (found diff --git a/QDMA/linux-kernel/bsd_license.txt b/QDMA/linux-kernel/bsd_license.txt index 20693b4e..ebf291e6 100755 --- a/QDMA/linux-kernel/bsd_license.txt +++ b/QDMA/linux-kernel/bsd_license.txt @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is licensed under both the BSD-style license (found in the * LICENSE file in the root directory of this source tree) and the GPLv2 (found diff --git a/QDMA/linux-kernel/docs/README b/QDMA/linux-kernel/docs/README index bc04f890..bac99177 100755 --- a/QDMA/linux-kernel/docs/README +++ b/QDMA/linux-kernel/docs/README @@ -303,7 +303,7 @@ _____________________________________________________________________________ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/Makefile b/QDMA/linux-kernel/driver/Makefile index 7d1377a5..1d073f4f 100755 --- a/QDMA/linux-kernel/driver/Makefile +++ b/QDMA/linux-kernel/driver/Makefile @@ -2,7 +2,7 @@ # * This file is part of the Xilinx DMA IP Core driver for Linux # * # * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is free software; you can redistribute it and/or modify it # * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/include/qdma_nl.h b/QDMA/linux-kernel/driver/include/qdma_nl.h index e0801c9e..c9bb02da 100755 --- a/QDMA/linux-kernel/driver/include/qdma_nl.h +++ b/QDMA/linux-kernel/driver/include/qdma_nl.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/include/qdma_user_reg_dump.h b/QDMA/linux-kernel/driver/include/qdma_user_reg_dump.h index 80906cee..4bcd4ca5 100755 --- a/QDMA/linux-kernel/driver/include/qdma_user_reg_dump.h +++ b/QDMA/linux-kernel/driver/include/qdma_user_reg_dump.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/include/xdev_regs.h b/QDMA/linux-kernel/driver/include/xdev_regs.h index c1c198df..0d4e5272 100755 --- a/QDMA/linux-kernel/driver/include/xdev_regs.h +++ b/QDMA/linux-kernel/driver/include/xdev_regs.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/Makefile b/QDMA/linux-kernel/driver/libqdma/Makefile index 3184572c..83b07ffc 100755 --- a/QDMA/linux-kernel/driver/libqdma/Makefile +++ b/QDMA/linux-kernel/driver/libqdma/Makefile @@ -2,7 +2,7 @@ # * This file is part of the Xilinx DMA IP Core driver for Linux # * # * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is free software; you can redistribute it and/or modify it # * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/libqdma_config.c b/QDMA/linux-kernel/driver/libqdma/libqdma_config.c index 69fbf63e..1ee9aef9 100755 --- a/QDMA/linux-kernel/driver/libqdma/libqdma_config.c +++ b/QDMA/linux-kernel/driver/libqdma/libqdma_config.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/libqdma_config.h b/QDMA/linux-kernel/driver/libqdma/libqdma_config.h index 99ae2613..93720be2 100755 --- a/QDMA/linux-kernel/driver/libqdma/libqdma_config.h +++ b/QDMA/linux-kernel/driver/libqdma/libqdma_config.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -44,6 +44,10 @@ */ #define MAX_DMA_DEV 32 +#ifdef CONFIG_PCI_DOMAINS_GENERIC +#define PCI_SHIFT_DOMAIN 20 +#endif + /** * Shift for bus 'B' in B:D:F */ diff --git a/QDMA/linux-kernel/driver/libqdma/libqdma_export.c b/QDMA/linux-kernel/driver/libqdma/libqdma_export.c index 30398b7f..f0524d89 100755 --- a/QDMA/linux-kernel/driver/libqdma/libqdma_export.c +++ b/QDMA/linux-kernel/driver/libqdma/libqdma_export.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/libqdma_export.h b/QDMA/linux-kernel/driver/libqdma/libqdma_export.h index fd604466..baeb78e5 100755 --- a/QDMA/linux-kernel/driver/libqdma/libqdma_export.h +++ b/QDMA/linux-kernel/driver/libqdma/libqdma_export.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c index 9bb152fe..41a47f1b 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -2248,35 +2248,56 @@ static void eqdma_cpm5_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt { int i = 0; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_stat_desc; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_int; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->trig_mode; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->fnc_id; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->counter_idx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_idx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->in_st; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->color; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ringsz_idx; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.en_stat_desc; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.en_int; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.trig_mode; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.fnc_id; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.counter_idx; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.timer_idx; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.in_st; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.color; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.ringsz_idx; eqdma_cpm5_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_L_MASK, cmpt_ctxt->bs_addr); eqdma_cpm5_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_H_MASK, cmpt_ctxt->bs_addr); - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->desc_sz; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.desc_sz; eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->pidx; eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->cidx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->valid; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->err; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->user_trig_pend; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_running; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->full_upd; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ovf_chk_dis; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->at; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->vec; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->int_aggr; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dis_intr_on_vf; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dir_c2h; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.valid; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.err; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.user_trig_pend; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.timer_running; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.full_upd; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.ovf_chk_dis; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.at; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.vec; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.int_aggr; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.dis_intr_on_vf; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.dir_c2h; eqdma_cpm5_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( EQDMA_CPM5_COMPL_CTXT_BADDR_LOW_MASK, cmpt_ctxt->bs_addr); @@ -3695,10 +3716,11 @@ static int eqdma_cpm5_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, return -QDMA_ERR_INV_PARAM; } - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { + if (ctxt->lower_dword.bit.trig_mode > + QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", __func__, - ctxt->trig_mode, + ctxt->lower_dword.bit.trig_mode, QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, -QDMA_ERR_INV_PARAM); return -QDMA_ERR_INV_PARAM; @@ -3726,47 +3748,63 @@ static int eqdma_cpm5_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | + ctxt->lower_dword.bit.en_stat_desc) | + FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, + ctxt->lower_dword.bit.en_int) | + FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, + ctxt->lower_dword.bit.trig_mode) | + FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, + ctxt->lower_dword.bit.fnc_id) | FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - ctxt->counter_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, ctxt->timer_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, ctxt->ringsz_idx); + ctxt->lower_dword.bit.counter_idx) | + FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, + ctxt->lower_dword.bit.timer_idx) | + FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, + ctxt->lower_dword.bit.in_st) | + FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, + ctxt->lower_dword.bit.color) | + FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, + ctxt->lower_dword.bit.ringsz_idx); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, baddr4_high_l); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, baddr4_high_h) | - FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, ctxt->desc_sz) | + FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, + ctxt->higher_dword.bit.desc_sz) | FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, pidx_l); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, pidx_h) | FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | + FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, + ctxt->higher_dword.bit.valid) | + FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, + ctxt->higher_dword.bit.err) | FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend); + ctxt->higher_dword.bit.user_trig_pend); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, - ctxt->timer_running) | - FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, ctxt->full_upd) | + ctxt->higher_dword.bit.timer_running) | + FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, + ctxt->higher_dword.bit.full_upd) | FIELD_SET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, ctxt->at) | - FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->int_aggr) | + ctxt->higher_dword.bit.ovf_chk_dis) | + FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, + ctxt->higher_dword.bit.at) | + FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, + ctxt->higher_dword.bit.vec) | + FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, + ctxt->higher_dword.bit.int_aggr) | FIELD_SET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | + ctxt->higher_dword.bit.dis_intr_on_vf) | FIELD_SET(CMPL_CTXT_DATA_W4_VIO_MASK, ctxt->vio) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, ctxt->dir_c2h) | - FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | + FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, + ctxt->higher_dword.bit.dir_c2h) | + FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, + ctxt->higher_dword.bit.host_id) | FIELD_SET(CMPL_CTXT_DATA_W4_PASID_L_MASK, pasid_l); cmpt_ctxt[num_words_count++] = @@ -3812,25 +3850,28 @@ static int eqdma_cpm5_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, if (rv < 0) return rv; - ctxt->en_stat_desc = - FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = + ctxt->lower_dword.bit.en_stat_desc = + FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, + cmpt_ctxt[0]); + ctxt->lower_dword.bit.en_int = + FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); + ctxt->lower_dword.bit.trig_mode = FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, cmpt_ctxt[0]); - ctxt->counter_idx = + ctxt->lower_dword.bit.fnc_id = + FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, cmpt_ctxt[0]); + ctxt->lower_dword.bit.counter_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, cmpt_ctxt[0])); - ctxt->timer_idx = + ctxt->lower_dword.bit.timer_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, cmpt_ctxt[0])); - ctxt->in_st = + ctxt->lower_dword.bit.in_st = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, cmpt_ctxt[0])); - ctxt->color = + ctxt->lower_dword.bit.color = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, cmpt_ctxt[0])); - ctxt->ringsz_idx = + ctxt->lower_dword.bit.ringsz_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, cmpt_ctxt[0])); @@ -3839,7 +3880,7 @@ static int eqdma_cpm5_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, baddr4_high_h = FIELD_GET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, cmpt_ctxt[2]); - ctxt->desc_sz = + ctxt->higher_dword.bit.desc_sz = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, cmpt_ctxt[2])); pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, cmpt_ctxt[2]); @@ -3848,34 +3889,42 @@ static int eqdma_cpm5_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, ctxt->cidx = (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, cmpt_ctxt[3])); - ctxt->valid = + ctxt->higher_dword.bit.valid = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, cmpt_ctxt[3])); - ctxt->err = + ctxt->higher_dword.bit.err = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) + ctxt->higher_dword.bit.user_trig_pend = (uint8_t) (FIELD_GET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, cmpt_ctxt[3])); - ctxt->timer_running = - FIELD_GET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, cmpt_ctxt[4]); - ctxt->full_upd = - FIELD_GET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = - FIELD_GET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) - (FIELD_GET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, cmpt_ctxt[4])); - ctxt->dis_intr_on_vf = (uint8_t) - FIELD_GET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - cmpt_ctxt[4]); + ctxt->higher_dword.bit.timer_running = + FIELD_GET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, + cmpt_ctxt[4]); + ctxt->higher_dword.bit.full_upd = + FIELD_GET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, + cmpt_ctxt[4]); + ctxt->higher_dword.bit.ovf_chk_dis = + FIELD_GET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, + cmpt_ctxt[4]); + ctxt->higher_dword.bit.at = + FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); + ctxt->higher_dword.bit.vec = + FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); + ctxt->higher_dword.bit.int_aggr = (uint8_t) + (FIELD_GET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, + cmpt_ctxt[4])); + ctxt->higher_dword.bit.dis_intr_on_vf = (uint8_t) + FIELD_GET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, + cmpt_ctxt[4]); ctxt->vio = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_VIO_MASK, cmpt_ctxt[4]); - ctxt->dir_c2h = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, + ctxt->higher_dword.bit.dir_c2h = + (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, cmpt_ctxt[4]); - ctxt->host_id = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, + ctxt->higher_dword.bit.host_id = + (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, cmpt_ctxt[4]); pasid_l = FIELD_GET(CMPL_CTXT_DATA_W4_PASID_L_MASK, cmpt_ctxt[4]); @@ -5231,7 +5280,7 @@ static void eqdma_cpm5_hw_err_dump_ctxt_info(void *dev_hndl, eqdma_cpm5_cmpt_ctxt_entries[13].value, eqdma_cpm5_cmpt_ctxt_entries[13].value); - if (cmpt_ctxt.err != 0) { + if (cmpt_ctxt.higher_dword.bit.err != 0) { /*** CMPT Context: ERR ***/ qdma_log_info("%-47s %#-10x %u\n", eqdma_cpm5_cmpt_ctxt_entries[15].name, @@ -6759,7 +6808,7 @@ int eqdma_cpm5_dump_reg_info(void *dev_hndl, uint32_t reg_addr, if (buf) { rv = QDMA_SNPRINTF_S(buf, buflen, DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", + "\n%-40s 0x%-7x %-#10x %u\n", config_regs[j].name, config_regs[j].addr, reg_val, reg_val); @@ -6773,7 +6822,7 @@ int eqdma_cpm5_dump_reg_info(void *dev_hndl, uint32_t reg_addr, data_len += rv; buflen -= rv; } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", + qdma_log_info("%-40s 0x%-7x %-#10x %u\n", config_regs[j].name, config_regs[j].addr, reg_val, reg_val); @@ -6791,7 +6840,7 @@ int eqdma_cpm5_dump_reg_info(void *dev_hndl, uint32_t reg_addr, bitfield = config_regs[j].bitfields[k].field_mask; bitfield_name = - config_regs[i].bitfields[k].field_name; + config_regs[j].bitfields[k].field_name; lsb = 0; msb = 31; diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h index 93662d22..3308640f 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -24,6 +24,8 @@ extern "C" { #include "qdma_platform.h" +#define DEBGFS_REG_LINE_SZ (74) + /** * enum eqdma_cpm5_error_idx - qdma errors */ @@ -337,6 +339,12 @@ uint32_t eqdma_cpm5_get_config_num_regs(void); struct xreg_info *eqdma_cpm5_get_config_regs(void); +uint32_t eqdma_cpm5_config_num_regs_get(void); + +struct xreg_info *eqdma_cpm5_config_regs_get(void); + +int qdma_reginfo_dump_buf_len(int *n_regs, struct xreg_info *config_regs); + #ifdef __cplusplus } #endif diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h index 40274843..c1b406f2 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -72,8 +72,6 @@ extern "C" { sizeof(arr[0])) -uint32_t eqdma_cpm5_config_num_regs_get(void); -struct xreg_info *eqdma_cpm5_config_regs_get(void); #define EQDMA_CPM5_CFG_BLK_IDENTIFIER_ADDR 0x00 #define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) #define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c index 2c71d016..93374f1c 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,6 +16,7 @@ */ #include "eqdma_cpm5_reg.h" +#include "eqdma_cpm5_access.h" #include "qdma_reg_dump.h" #ifdef ENABLE_WPP_TRACING diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c index 0a65fbac..77ec2780 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -2285,35 +2285,56 @@ static void eqdma_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) { int i = 0; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_stat_desc; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_int; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->trig_mode; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->fnc_id; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->counter_idx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_idx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->in_st; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->color; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ringsz_idx; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.en_stat_desc; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.en_int; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.trig_mode; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.fnc_id; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.counter_idx; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.timer_idx; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.in_st; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.color; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.ringsz_idx; eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK, cmpt_ctxt->bs_addr); eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK, cmpt_ctxt->bs_addr); - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->desc_sz; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.desc_sz; eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->pidx; eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->cidx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->valid; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->err; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->user_trig_pend; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_running; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->full_upd; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ovf_chk_dis; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->at; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->vec; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->int_aggr; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dis_intr_on_vf; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dir_c2h; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.valid; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.err; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.user_trig_pend; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.timer_running; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.full_upd; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.ovf_chk_dis; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.at; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.vec; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.int_aggr; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.dis_intr_on_vf; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.dir_c2h; eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( EQDMA_COMPL_CTXT_BADDR_LOW_MASK, cmpt_ctxt->bs_addr); @@ -3765,10 +3786,11 @@ static int eqdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, return -QDMA_ERR_INV_PARAM; } - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { + if (ctxt->lower_dword.bit.trig_mode > + QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", __func__, - ctxt->trig_mode, + ctxt->lower_dword.bit.trig_mode, QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, -QDMA_ERR_INV_PARAM); return -QDMA_ERR_INV_PARAM; @@ -3791,47 +3813,64 @@ static int eqdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | + ctxt->lower_dword.bit.en_stat_desc) | + FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, + ctxt->lower_dword.bit.en_int) | + FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, + ctxt->lower_dword.bit.trig_mode) | + FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, + ctxt->lower_dword.bit.fnc_id) | FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - ctxt->counter_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, ctxt->timer_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, ctxt->ringsz_idx); + ctxt->lower_dword.bit.counter_idx) | + FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, + ctxt->lower_dword.bit.timer_idx) | + FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, + ctxt->lower_dword.bit.in_st) | + FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, + ctxt->lower_dword.bit.color) | + FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, + ctxt->lower_dword.bit.ringsz_idx); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, baddr4_high_l); cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, baddr4_high_h) | - FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, ctxt->desc_sz) | + FIELD_SET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, + baddr4_high_h) | + FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, + ctxt->higher_dword.bit.desc_sz) | FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, pidx_l); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, pidx_h) | FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | + FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, + ctxt->higher_dword.bit.valid) | + FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, + ctxt->higher_dword.bit.err) | FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend); + ctxt->higher_dword.bit.user_trig_pend); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, - ctxt->timer_running) | - FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, ctxt->full_upd) | + ctxt->higher_dword.bit.timer_running) | + FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, + ctxt->higher_dword.bit.full_upd) | FIELD_SET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, ctxt->at) | - FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->int_aggr) | + ctxt->higher_dword.bit.ovf_chk_dis) | + FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, + ctxt->higher_dword.bit.at) | + FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, + ctxt->higher_dword.bit.vec) | + FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, + ctxt->higher_dword.bit.int_aggr) | FIELD_SET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | + ctxt->higher_dword.bit.dis_intr_on_vf) | FIELD_SET(CMPL_CTXT_DATA_W4_VIO_MASK, ctxt->vio) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, ctxt->dir_c2h) | - FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | + FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, + ctxt->higher_dword.bit.dir_c2h) | + FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, + ctxt->higher_dword.bit.host_id) | FIELD_SET(CMPL_CTXT_DATA_W4_PASID_L_MASK, pasid_l); cmpt_ctxt[num_words_count++] = @@ -3877,27 +3916,28 @@ static int eqdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, if (rv < 0) return rv; - ctxt->en_stat_desc = + ctxt->lower_dword.bit.en_stat_desc = FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = + ctxt->lower_dword.bit.en_int = + FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); + ctxt->lower_dword.bit.trig_mode = FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = + ctxt->lower_dword.bit.fnc_id = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, cmpt_ctxt[0])); - ctxt->counter_idx = + ctxt->lower_dword.bit.counter_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, cmpt_ctxt[0])); - ctxt->timer_idx = + ctxt->lower_dword.bit.timer_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, cmpt_ctxt[0])); - ctxt->in_st = + ctxt->lower_dword.bit.in_st = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, cmpt_ctxt[0])); - ctxt->color = + ctxt->lower_dword.bit.color = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, cmpt_ctxt[0])); - ctxt->ringsz_idx = + ctxt->lower_dword.bit.ringsz_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, cmpt_ctxt[0])); @@ -3906,7 +3946,7 @@ static int eqdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, baddr4_high_h = FIELD_GET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, cmpt_ctxt[2]); - ctxt->desc_sz = + ctxt->higher_dword.bit.desc_sz = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, cmpt_ctxt[2])); pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, cmpt_ctxt[2]); @@ -3915,34 +3955,38 @@ static int eqdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, ctxt->cidx = (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, cmpt_ctxt[3])); - ctxt->valid = + ctxt->higher_dword.bit.valid = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, cmpt_ctxt[3])); - ctxt->err = + ctxt->higher_dword.bit.err = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) + ctxt->higher_dword.bit.user_trig_pend = (uint8_t) (FIELD_GET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, cmpt_ctxt[3])); - ctxt->timer_running = + ctxt->higher_dword.bit.timer_running = FIELD_GET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, cmpt_ctxt[4]); - ctxt->full_upd = + ctxt->higher_dword.bit.full_upd = FIELD_GET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = + ctxt->higher_dword.bit.ovf_chk_dis = FIELD_GET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) + ctxt->higher_dword.bit.at = + FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); + ctxt->higher_dword.bit.vec = + FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); + ctxt->higher_dword.bit.int_aggr = (uint8_t) (FIELD_GET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, cmpt_ctxt[4])); - ctxt->dis_intr_on_vf = (uint8_t) + ctxt->higher_dword.bit.dis_intr_on_vf = (uint8_t) FIELD_GET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, cmpt_ctxt[4]); ctxt->vio = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_VIO_MASK, cmpt_ctxt[4]); - ctxt->dir_c2h = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, + ctxt->higher_dword.bit.dir_c2h = (uint8_t) + FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, cmpt_ctxt[4]); - ctxt->host_id = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, + ctxt->higher_dword.bit.host_id = (uint8_t) + FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, cmpt_ctxt[4]); pasid_l = FIELD_GET(CMPL_CTXT_DATA_W4_PASID_L_MASK, cmpt_ctxt[4]); @@ -5111,10 +5155,8 @@ int eqdma_get_user_bar(void *dev_hndl, uint8_t is_vf, } if (bar_found == 0) { *user_bar = 0; - qdma_log_error("%s: Bar not found, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BAR_NOT_FOUND); - return -QDMA_ERR_HWACC_BAR_NOT_FOUND; + qdma_log_info("%s: AXI Master Lite User Bar not found %d\n", + __func__, -QDMA_ERR_HWACC_BAR_NOT_FOUND); } return QDMA_SUCCESS; @@ -5295,7 +5337,7 @@ static void eqdma_hw_err_dump_ctxt_info(void *dev_hndl, eqdma_cmpt_ctxt_entries[13].value, eqdma_cmpt_ctxt_entries[13].value); - if (cmpt_ctxt.err != 0) { + if (cmpt_ctxt.higher_dword.bit.err != 0) { /*** CMPT Context: ERR ***/ qdma_log_info("%-47s %#-10x %u\n", eqdma_cmpt_ctxt_entries[15].name, @@ -6714,7 +6756,7 @@ int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, if (buf) { rv = QDMA_SNPRINTF_S(buf, buflen, DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", + "\n%-40s 0x%-7x %-#10x %u\n", config_regs[j].name, config_regs[j].addr, reg_val, reg_val); @@ -6728,7 +6770,7 @@ int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, data_len += rv; buflen -= rv; } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", + qdma_log_info("%-40s 0x%-7x %-#10x %u\n", config_regs[j].name, config_regs[j].addr, reg_val, reg_val); @@ -6746,7 +6788,7 @@ int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, bitfield = config_regs[j].bitfields[k].field_mask; bitfield_name = - config_regs[i].bitfields[k].field_name; + config_regs[j].bitfields[k].field_name; lsb = 0; msb = 31; diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h index 4cc8ca96..8ff644d0 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -24,6 +24,8 @@ extern "C" { #include "qdma_platform.h" +#define DEBGFS_REG_LINE_SZ (74) + /** * enum qdma_error_idx - qdma errors */ @@ -338,6 +340,12 @@ uint32_t eqdma_get_config_num_regs(void); struct xreg_info *eqdma_get_config_regs(void); +uint32_t eqdma_config_num_regs_get(void); + +struct xreg_info *eqdma_config_regs_get(void); + +int qdma_reginfo_dump_buf_len(int *n_regs, struct xreg_info *config_regs); + #ifdef __cplusplus } #endif diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h index 0905d509..d67e0e12 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -72,8 +72,6 @@ extern "C" { sizeof(arr[0])) -uint32_t eqdma_config_num_regs_get(void); -struct xreg_info *eqdma_config_regs_get(void); #define EQDMA_CFG_BLK_IDENTIFIER_ADDR 0x00 #define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) #define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c index 8754fb7c..00662fc6 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,6 +16,7 @@ */ #include "eqdma_soft_reg.h" +#include "eqdma_soft_access.h" #include "qdma_reg_dump.h" #ifdef ENABLE_WPP_TRACING diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.c index 6b468d57..e1c3363f 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -665,11 +665,24 @@ int qdma_acc_reg_dump_buf_len(void *dev_hndl, enum qdma_ip_type ip_type, return rv; } +int qdma_reginfo_dump_buf_len(int *n_regs, struct xreg_info *config_regs) +{ + int i = 0, bitfield_val = 0; + uint32_t len = 0; + + for (i = 0; i < *n_regs; i++) + bitfield_val += config_regs[i].num_bitfields; + len = (((*n_regs + 1) * DEBGFS_REG_LINE_SZ) + + ((bitfield_val + 1) * DEBGFS_LINE_SZ)); + return len; +} + int qdma_acc_reg_info_len(void *dev_hndl, enum qdma_ip_type ip_type, enum qdma_device_type device_type, int *buflen, int *num_regs) { uint32_t len = 0; int rv = 0; + struct xreg_info *config_regs = NULL; if (!dev_hndl) { qdma_log_error("%s: dev_handle is NULL, err:%d\n", @@ -701,11 +714,13 @@ int qdma_acc_reg_info_len(void *dev_hndl, enum qdma_ip_type ip_type, break; case QDMA_VERSAL_HARD_IP: if (device_type == QDMA_DEVICE_VERSAL_CPM4) { - len = qdma_cpm4_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); + *num_regs = (int)qdma_cpm4_config_num_regs_get(); + config_regs = qdma_cpm4_config_regs_get(); + len = qdma_reginfo_dump_buf_len(num_regs, config_regs); } else if (device_type == QDMA_DEVICE_VERSAL_CPM5) { - len = eqdma_cpm5_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); + *num_regs = (int)eqdma_cpm5_config_num_regs_get(); + config_regs = eqdma_cpm5_config_regs_get(); + len = qdma_reginfo_dump_buf_len(num_regs, config_regs); } else { qdma_log_error("%s: Invalid device type, err = %d", __func__, -QDMA_ERR_INV_PARAM); @@ -713,8 +728,9 @@ int qdma_acc_reg_info_len(void *dev_hndl, enum qdma_ip_type ip_type, } break; case EQDMA_SOFT_IP: - len = eqdma_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); + *num_regs = (int)eqdma_config_num_regs_get(); + config_regs = eqdma_config_regs_get(); + len = qdma_reginfo_dump_buf_len(num_regs, config_regs); break; default: qdma_log_error("%s: Invalid version number, err = %d", @@ -1367,9 +1383,6 @@ int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf, qdma_log_info("IP Type: %s\n", qdma_get_ip_type(dev_hndl, is_vf, version_info.ip_type)); - qdma_log_info("Vivado Release: %s\n", - qdma_get_vivado_release_id(version_info.vivado_release)); - if (version_info.ip_type == QDMA_VERSAL_HARD_IP && version_info.device_type == QDMA_DEVICE_VERSAL_CPM4) { hw_access->qdma_init_ctxt_memory = diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.h index f88c015d..03371e75 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_common.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -348,63 +348,81 @@ struct qdma_descq_prefetch_ctxt { * struct qdma_descq_cmpt_ctxt - descq completion context config data structure */ struct qdma_descq_cmpt_ctxt { + union __lower_dword__ { + uint32_t reg; + struct { + /** @en_stat_desc - Enable Completion Status writes */ + uint8_t en_stat_desc :1; + /** @en_int - Enable Completion interrupts */ + uint8_t en_int :1; + /** @trig_mode - Interrupt and Completion + * Status Write Trigger Mode + */ + uint8_t trig_mode :3; + /** @fnc_id - Function ID */ + uint8_t fnc_id :8; + /** @counter_idx - Index to counter register */ + uint8_t counter_idx :4; + /** @timer_idx - Index to timer register */ + uint8_t timer_idx :4; + /** @in_st - Interrupt State */ + uint8_t in_st :2; + /** @color - initial color bit to be used on + * Completion + */ + uint8_t color :1; + /** @ringsz_idx - Completion ring size index to + * ring size registers + */ + uint8_t ringsz_idx :4; + } bit; + } lower_dword; /** @bs_addr - completion ring base address */ uint64_t bs_addr; - /** @vec - Interrupt Vector */ - uint16_t vec; /** @pidx_l - producer index low */ uint16_t pidx; /** @cidx - consumer index */ uint16_t cidx; - /** @en_stat_desc - Enable Completion Status writes */ - uint8_t en_stat_desc; - /** @en_int - Enable Completion interrupts */ - uint8_t en_int; - /** @trig_mode - Interrupt and Completion Status Write Trigger Mode */ - uint8_t trig_mode; - /** @fnc_id - Function ID */ - uint8_t fnc_id; - /** @counter_idx - Index to counter register */ - uint8_t counter_idx; - /** @timer_idx - Index to timer register */ - uint8_t timer_idx; - /** @in_st - Interrupt State */ - uint8_t in_st; - /** @color - initial color bit to be used on Completion */ - uint8_t color; - /** @ringsz_idx - Completion ring size index to ring size registers */ - uint8_t ringsz_idx; - /** @desc_sz -descriptor size */ - uint8_t desc_sz; - /** @valid - context valid */ - uint8_t valid; - /** @err - error status */ - uint8_t err; - /** - * @user_trig_pend - user logic initiated interrupt is - * pending to be generate - */ - uint8_t user_trig_pend; - /** @timer_running - timer is running on this queue */ - uint8_t timer_running; - /** @full_upd - Full update */ - uint8_t full_upd; - /** @ovf_chk_dis - Completion Ring Overflow Check Disable */ - uint8_t ovf_chk_dis; - /** @at -Address Translation */ - uint8_t at; - /** @int_aggr -Interrupt Aggregation */ - uint8_t int_aggr; - /** @dis_intr_on_vf - Disbale interrupt with VF */ - uint8_t dis_intr_on_vf; - /** @vio - queue is in VirtIO mode */ - uint8_t vio; - /** @dir_c2h - DMA direction is C2H */ - uint8_t dir_c2h; - /** @host_id - Host ID */ - uint8_t host_id; + union __higher_dword__ { + uint32_t reg; + struct { + /** @desc_sz -descriptor size */ + uint8_t desc_sz :2; + /** @valid - context valid */ + uint8_t valid :1; + /** @err - error status */ + uint8_t err :2; + /** + * @user_trig_pend - user logic initiated interrupt is + * pending to be generate + */ + uint8_t user_trig_pend :1; + /** @timer_running - timer is running on this queue */ + uint8_t timer_running :1; + /** @full_upd - Full update */ + uint8_t full_upd :1; + /** @ovf_chk_dis - Completion Ring Overflow + * Check Disable + */ + uint8_t ovf_chk_dis :1; + /** @at -Address Translation */ + uint8_t at : 1; + /** @vec - Interrupt Vector */ + uint16_t vec: 11; + /** @int_aggr -Interrupt Aggregation */ + uint8_t int_aggr :1; + /** @dis_intr_on_vf - Disbale interrupt with VF */ + uint8_t dis_intr_on_vf :1; + /** @dir_c2h - DMA direction is C2H */ + uint8_t dir_c2h :1; + /** @host_id - Host ID */ + uint8_t host_id :3; + } bit; + } higher_dword; /** @pasid - PASID */ uint32_t pasid; + /** @vio - queue is in VirtIO mode */ + uint8_t vio; /** @pasid_en - PASID Enable */ uint8_t pasid_en; /** @vio_eop - Virtio End-of-packet */ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_errors.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_errors.h index c8b28c9f..f3d1ac3d 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_errors.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_errors.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_export.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_export.h index 66eaa322..26c94ca8 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_export.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_export.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_version.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_version.h index f6559181..11e06d21 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_version.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_access_version.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,9 +19,9 @@ #define __QDMA_ACCESS_VERSION_H_ -#define QDMA_VERSION_MAJOR 2023 -#define QDMA_VERSION_MINOR 2 -#define QDMA_VERSION_PATCH 1 +#define QDMA_VERSION_MAJOR 2024 +#define QDMA_VERSION_MINOR 1 +#define QDMA_VERSION_PATCH 0 #define QDMA_VERSION_STR \ __stringify(QDMA_VERSION_MAJOR) "." \ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c index 33c45ff6..87fa6d1a 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1298,27 +1298,42 @@ static void qdma_cpm4_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) */ static void qdma_cpm4_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) { - qdma_cpm4_cmpt_ctxt_entries[0].value = cmpt_ctxt->en_stat_desc; - qdma_cpm4_cmpt_ctxt_entries[1].value = cmpt_ctxt->en_int; - qdma_cpm4_cmpt_ctxt_entries[2].value = cmpt_ctxt->trig_mode; - qdma_cpm4_cmpt_ctxt_entries[3].value = cmpt_ctxt->fnc_id; - qdma_cpm4_cmpt_ctxt_entries[4].value = cmpt_ctxt->counter_idx; - qdma_cpm4_cmpt_ctxt_entries[5].value = cmpt_ctxt->timer_idx; - qdma_cpm4_cmpt_ctxt_entries[6].value = cmpt_ctxt->in_st; - qdma_cpm4_cmpt_ctxt_entries[7].value = cmpt_ctxt->color; - qdma_cpm4_cmpt_ctxt_entries[8].value = cmpt_ctxt->ringsz_idx; + qdma_cpm4_cmpt_ctxt_entries[0].value = + cmpt_ctxt->lower_dword.bit.en_stat_desc; + qdma_cpm4_cmpt_ctxt_entries[1].value = + cmpt_ctxt->lower_dword.bit.en_int; + qdma_cpm4_cmpt_ctxt_entries[2].value = + cmpt_ctxt->lower_dword.bit.trig_mode; + qdma_cpm4_cmpt_ctxt_entries[3].value = + cmpt_ctxt->lower_dword.bit.fnc_id; + qdma_cpm4_cmpt_ctxt_entries[4].value = + cmpt_ctxt->lower_dword.bit.counter_idx; + qdma_cpm4_cmpt_ctxt_entries[5].value = + cmpt_ctxt->lower_dword.bit.timer_idx; + qdma_cpm4_cmpt_ctxt_entries[6].value = + cmpt_ctxt->lower_dword.bit.in_st; + qdma_cpm4_cmpt_ctxt_entries[7].value = + cmpt_ctxt->lower_dword.bit.color; + qdma_cpm4_cmpt_ctxt_entries[8].value = + cmpt_ctxt->lower_dword.bit.ringsz_idx; qdma_cpm4_cmpt_ctxt_entries[9].value = cmpt_ctxt->bs_addr & 0xFFFFFFFF; qdma_cpm4_cmpt_ctxt_entries[10].value = (cmpt_ctxt->bs_addr >> 32) & 0xFFFFFFFF; - qdma_cpm4_cmpt_ctxt_entries[11].value = cmpt_ctxt->desc_sz; + qdma_cpm4_cmpt_ctxt_entries[11].value = + cmpt_ctxt->higher_dword.bit.desc_sz; qdma_cpm4_cmpt_ctxt_entries[12].value = cmpt_ctxt->pidx; qdma_cpm4_cmpt_ctxt_entries[13].value = cmpt_ctxt->cidx; - qdma_cpm4_cmpt_ctxt_entries[14].value = cmpt_ctxt->valid; - qdma_cpm4_cmpt_ctxt_entries[15].value = cmpt_ctxt->err; - qdma_cpm4_cmpt_ctxt_entries[16].value = cmpt_ctxt->user_trig_pend; - qdma_cpm4_cmpt_ctxt_entries[17].value = cmpt_ctxt->timer_running; - qdma_cpm4_cmpt_ctxt_entries[18].value = cmpt_ctxt->full_upd; + qdma_cpm4_cmpt_ctxt_entries[14].value = + cmpt_ctxt->higher_dword.bit.valid; + qdma_cpm4_cmpt_ctxt_entries[15].value = + cmpt_ctxt->higher_dword.bit.err; + qdma_cpm4_cmpt_ctxt_entries[16].value = + cmpt_ctxt->higher_dword.bit.user_trig_pend; + qdma_cpm4_cmpt_ctxt_entries[17].value = + cmpt_ctxt->higher_dword.bit.timer_running; + qdma_cpm4_cmpt_ctxt_entries[18].value = + cmpt_ctxt->higher_dword.bit.full_upd; } @@ -3017,19 +3032,23 @@ static int qdma_cpm4_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, return -QDMA_ERR_INV_PARAM; } - if ((ctxt->desc_sz > QDMA_DESC_SIZE_32B) || - (ctxt->ringsz_idx >= QDMA_NUM_RING_SIZES) || - (ctxt->counter_idx >= QDMA_NUM_C2H_COUNTERS) || - (ctxt->timer_idx >= QDMA_NUM_C2H_TIMERS) || - (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR)) { + if ((ctxt->higher_dword.bit.desc_sz > QDMA_DESC_SIZE_32B) || + (FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK, + ctxt->lower_dword.bit.ringsz_idx) >= QDMA_NUM_RING_SIZES) || + (FIELD_GET(CMPL_CTXT_DATA_W0_CNTER_IDX_MASK, + ctxt->lower_dword.bit.counter_idx) >= QDMA_NUM_C2H_COUNTERS) || + (FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK, + ctxt->lower_dword.bit.timer_idx) >= QDMA_NUM_C2H_TIMERS) || + (ctxt->lower_dword.bit.trig_mode > + QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR)) { qdma_log_error ("%s Inv dsz(%d)/ridx(%d)/cntr(%d)/tmr(%d)/tm(%d), err:%d\n", __func__, - ctxt->desc_sz, - ctxt->ringsz_idx, - ctxt->counter_idx, - ctxt->timer_idx, - ctxt->trig_mode, + ctxt->higher_dword.bit.desc_sz, + ctxt->lower_dword.bit.ringsz_idx, + ctxt->lower_dword.bit.counter_idx, + ctxt->lower_dword.bit.timer_idx, + ctxt->lower_dword.bit.trig_mode, -QDMA_ERR_INV_PARAM); return -QDMA_ERR_INV_PARAM; } @@ -3051,20 +3070,23 @@ static int qdma_cpm4_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | + ctxt->lower_dword.bit.en_stat_desc) | + FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, + ctxt->lower_dword.bit.en_int) | + FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, + ctxt->lower_dword.bit.trig_mode) | + FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, + ctxt->lower_dword.bit.fnc_id) | FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IDX_MASK, - ctxt->counter_idx) | + ctxt->lower_dword.bit.counter_idx) | FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK, - ctxt->timer_idx) | + ctxt->lower_dword.bit.timer_idx) | FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - ctxt->in_st) | + ctxt->lower_dword.bit.in_st) | FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, - ctxt->color) | + ctxt->lower_dword.bit.color) | FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK, - ctxt->ringsz_idx) | + ctxt->lower_dword.bit.ringsz_idx) | FIELD_SET(CMPL_CTXT_DATA_W0_BADDR_64_L_MASK, baddr_l); @@ -3076,7 +3098,7 @@ static int qdma_cpm4_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, FIELD_SET(CMPL_CTXT_DATA_W2_BADDR_64_H_MASK, baddr_h) | FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - ctxt->desc_sz) | + ctxt->higher_dword.bit.desc_sz) | FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, pidx_l); @@ -3084,14 +3106,16 @@ static int qdma_cpm4_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, pidx_h) | FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | + FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, + ctxt->higher_dword.bit.valid) | + FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, + ctxt->higher_dword.bit.err) | FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend) | + ctxt->higher_dword.bit.user_trig_pend) | FIELD_SET(CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK, - ctxt->timer_running) | + ctxt->higher_dword.bit.timer_running) | FIELD_SET(CMPL_CTXT_DATA_W3_FULL_UPD_MASK, - ctxt->full_upd); + ctxt->higher_dword.bit.full_upd); return qdma_cpm4_indirect_reg_write(dev_hndl, sel, hw_qid, cmpt_ctxt, num_words_count); @@ -3129,29 +3153,29 @@ static int qdma_cpm4_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, if (rv < 0) return rv; - ctxt->en_stat_desc = + ctxt->lower_dword.bit.en_stat_desc = FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, + ctxt->lower_dword.bit.en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = + ctxt->lower_dword.bit.trig_mode = FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = + ctxt->lower_dword.bit.fnc_id = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, cmpt_ctxt[0])); - ctxt->counter_idx = + ctxt->lower_dword.bit.counter_idx = (uint8_t)(FIELD_GET( CMPL_CTXT_DATA_W0_CNTER_IDX_MASK, cmpt_ctxt[0])); - ctxt->timer_idx = + ctxt->lower_dword.bit.timer_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK, cmpt_ctxt[0])); - ctxt->in_st = + ctxt->lower_dword.bit.in_st = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, cmpt_ctxt[0])); - ctxt->color = + ctxt->lower_dword.bit.color = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, cmpt_ctxt[0])); - ctxt->ringsz_idx = + ctxt->lower_dword.bit.ringsz_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK, cmpt_ctxt[0])); @@ -3165,7 +3189,7 @@ static int qdma_cpm4_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, FIELD_GET(CMPL_CTXT_DATA_W2_BADDR_64_H_MASK, cmpt_ctxt[2]); - ctxt->desc_sz = + ctxt->higher_dword.bit.desc_sz = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, cmpt_ctxt[2])); pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, @@ -3176,20 +3200,20 @@ static int qdma_cpm4_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, ctxt->cidx = (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, cmpt_ctxt[3])); - ctxt->valid = + ctxt->higher_dword.bit.valid = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, cmpt_ctxt[3])); - ctxt->err = + ctxt->higher_dword.bit.err = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, cmpt_ctxt[3])); - ctxt->user_trig_pend = + ctxt->higher_dword.bit.user_trig_pend = (uint8_t)(FIELD_GET( CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, cmpt_ctxt[3])); - ctxt->timer_running = + ctxt->higher_dword.bit.timer_running = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK, cmpt_ctxt[3])); - ctxt->full_upd = + ctxt->higher_dword.bit.full_upd = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_FULL_UPD_MASK, cmpt_ctxt[3])); @@ -5957,7 +5981,7 @@ int qdma_cpm4_dump_reg_info(void *dev_hndl, uint32_t reg_addr, if (buf) { rv = QDMA_SNPRINTF_S(buf, buflen, DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", + "\n%-40s 0x%-7x %-#10x %u\n", config_regs[j].name, config_regs[j].addr, reg_val, reg_val); @@ -5971,7 +5995,7 @@ int qdma_cpm4_dump_reg_info(void *dev_hndl, uint32_t reg_addr, data_len += rv; buflen -= rv; } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", + qdma_log_info("%-40s 0x%-7x %-#10x %u\n", config_regs[j].name, config_regs[j].addr, reg_val, reg_val); @@ -5983,7 +6007,7 @@ int qdma_cpm4_dump_reg_info(void *dev_hndl, uint32_t reg_addr, bitfield = config_regs[j].bitfields[k].field_mask; bitfield_name = - config_regs[i].bitfields[k].field_name; + config_regs[j].bitfields[k].field_name; lsb = 0; msb = 31; diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h index cecb0d73..8127ddcc 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -24,6 +24,8 @@ extern "C" { #include "qdma_platform.h" +#define DEBGFS_REG_LINE_SZ (74) + /** * enum qdma_error_idx - qdma errors */ @@ -277,6 +279,11 @@ uint32_t qdma_cpm4_get_config_num_regs(void); struct xreg_info *qdma_cpm4_get_config_regs(void); +uint32_t qdma_cpm4_config_num_regs_get(void); +struct xreg_info *qdma_cpm4_config_regs_get(void); + +int qdma_reginfo_dump_buf_len(int *n_regs, struct xreg_info *config_regs); + #ifdef __cplusplus } #endif diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h index dee28b4d..68f7b13c 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -72,8 +72,6 @@ extern "C" { sizeof(arr[0])) -uint32_t qdma_cpm4_config_num_regs_get(void); -struct xreg_info *qdma_cpm4_config_regs_get(void); #define QDMA_CPM4_CFG_BLK_IDENTIFIER_ADDR 0x00 #define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) #define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c index dcfb94f4..b4385b8a 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,6 +16,7 @@ */ #include "qdma_cpm4_reg.h" +#include "qdma_cpm4_access.h" #include "qdma_reg_dump.h" #ifdef ENABLE_WPP_TRACING diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.c index b7fabf75..5e1717bb 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.h index dd5f7d4b..dab922cb 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_list.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.c index 67e7268c..447f43a5 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -610,22 +610,27 @@ static int mbox_compose_cmpt_context(void *dev_hndl, /* writeback context */ cmpt_ctxt->bs_addr = qctxt->descq_conf.cmpt_ring_bs_addr; - cmpt_ctxt->en_stat_desc = qctxt->descq_conf.cmpl_stat_en; - cmpt_ctxt->en_int = qctxt->descq_conf.cmpt_int_en; - cmpt_ctxt->trig_mode = qctxt->descq_conf.triggermode; - cmpt_ctxt->fnc_id = qctxt->descq_conf.func_id; - cmpt_ctxt->timer_idx = tmr_idx; - cmpt_ctxt->counter_idx = cntr_idx; - cmpt_ctxt->color = 1; - cmpt_ctxt->ringsz_idx = rng_idx; - - cmpt_ctxt->desc_sz = qctxt->descq_conf.cmpt_desc_sz; - - cmpt_ctxt->valid = 1; - - cmpt_ctxt->ovf_chk_dis = qctxt->descq_conf.dis_overflow_check; - cmpt_ctxt->vec = qctxt->descq_conf.intr_id; - cmpt_ctxt->int_aggr = qctxt->descq_conf.intr_aggr; + cmpt_ctxt->lower_dword.bit.en_stat_desc = + qctxt->descq_conf.cmpl_stat_en; + cmpt_ctxt->lower_dword.bit.en_int = qctxt->descq_conf.cmpt_int_en; + cmpt_ctxt->lower_dword.bit.trig_mode = qctxt->descq_conf.triggermode; + cmpt_ctxt->lower_dword.bit.fnc_id = qctxt->descq_conf.func_id; + cmpt_ctxt->lower_dword.bit.timer_idx = tmr_idx; + cmpt_ctxt->lower_dword.bit.counter_idx = cntr_idx; + cmpt_ctxt->lower_dword.bit.color = 1; + cmpt_ctxt->lower_dword.bit.ringsz_idx = rng_idx; + + cmpt_ctxt->higher_dword.bit.desc_sz = qctxt->descq_conf.cmpt_desc_sz; + + cmpt_ctxt->higher_dword.bit.valid = 1; + + if ((qctxt->st) && (qctxt->c2h)) + cmpt_ctxt->higher_dword.bit.dir_c2h = 1; + + cmpt_ctxt->higher_dword.bit.ovf_chk_dis = + qctxt->descq_conf.dis_overflow_check; + cmpt_ctxt->higher_dword.bit.vec = qctxt->descq_conf.intr_id; + cmpt_ctxt->higher_dword.bit.int_aggr = qctxt->descq_conf.intr_aggr; return QDMA_SUCCESS; } diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.h index b29a8c0b..5dfb30bb 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_mbox_protocol.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_platform.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_platform.h index 996b8916..042d8d60 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_platform.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_platform.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_reg_dump.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_reg_dump.h index f774bf65..3a2583bd 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_reg_dump.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_reg_dump.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.c index 1875ac4d..b812d5a3 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.h index 5c53c476..1679dff9 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_resource_mgmt.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.c b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.c index b23a4df5..15a154ad 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1737,30 +1737,31 @@ static void qdma_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) */ static void qdma_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) { - cmpt_ctxt_entries[0].value = cmpt_ctxt->en_stat_desc; - cmpt_ctxt_entries[1].value = cmpt_ctxt->en_int; - cmpt_ctxt_entries[2].value = cmpt_ctxt->trig_mode; - cmpt_ctxt_entries[3].value = cmpt_ctxt->fnc_id; - cmpt_ctxt_entries[4].value = cmpt_ctxt->counter_idx; - cmpt_ctxt_entries[5].value = cmpt_ctxt->timer_idx; - cmpt_ctxt_entries[6].value = cmpt_ctxt->in_st; - cmpt_ctxt_entries[7].value = cmpt_ctxt->color; - cmpt_ctxt_entries[8].value = cmpt_ctxt->ringsz_idx; + cmpt_ctxt_entries[0].value = cmpt_ctxt->lower_dword.bit.en_stat_desc; + cmpt_ctxt_entries[1].value = cmpt_ctxt->lower_dword.bit.en_int; + cmpt_ctxt_entries[2].value = cmpt_ctxt->lower_dword.bit.trig_mode; + cmpt_ctxt_entries[3].value = cmpt_ctxt->lower_dword.bit.fnc_id; + cmpt_ctxt_entries[4].value = cmpt_ctxt->lower_dword.bit.counter_idx; + cmpt_ctxt_entries[5].value = cmpt_ctxt->lower_dword.bit.timer_idx; + cmpt_ctxt_entries[6].value = cmpt_ctxt->lower_dword.bit.in_st; + cmpt_ctxt_entries[7].value = cmpt_ctxt->lower_dword.bit.color; + cmpt_ctxt_entries[8].value = cmpt_ctxt->lower_dword.bit.ringsz_idx; cmpt_ctxt_entries[9].value = cmpt_ctxt->bs_addr & 0xFFFFFFFF; cmpt_ctxt_entries[10].value = (cmpt_ctxt->bs_addr >> 32) & 0xFFFFFFFF; - cmpt_ctxt_entries[11].value = cmpt_ctxt->desc_sz; + cmpt_ctxt_entries[11].value = cmpt_ctxt->higher_dword.bit.desc_sz; cmpt_ctxt_entries[12].value = cmpt_ctxt->pidx; cmpt_ctxt_entries[13].value = cmpt_ctxt->cidx; - cmpt_ctxt_entries[14].value = cmpt_ctxt->valid; - cmpt_ctxt_entries[15].value = cmpt_ctxt->err; - cmpt_ctxt_entries[16].value = cmpt_ctxt->user_trig_pend; - cmpt_ctxt_entries[17].value = cmpt_ctxt->timer_running; - cmpt_ctxt_entries[18].value = cmpt_ctxt->full_upd; - cmpt_ctxt_entries[19].value = cmpt_ctxt->ovf_chk_dis; - cmpt_ctxt_entries[20].value = cmpt_ctxt->at; - cmpt_ctxt_entries[21].value = cmpt_ctxt->vec; - cmpt_ctxt_entries[22].value = cmpt_ctxt->int_aggr; + cmpt_ctxt_entries[14].value = cmpt_ctxt->higher_dword.bit.valid; + cmpt_ctxt_entries[15].value = cmpt_ctxt->higher_dword.bit.err; + cmpt_ctxt_entries[16].value = + cmpt_ctxt->higher_dword.bit.user_trig_pend; + cmpt_ctxt_entries[17].value = cmpt_ctxt->higher_dword.bit.timer_running; + cmpt_ctxt_entries[18].value = cmpt_ctxt->higher_dword.bit.full_upd; + cmpt_ctxt_entries[19].value = cmpt_ctxt->higher_dword.bit.ovf_chk_dis; + cmpt_ctxt_entries[20].value = cmpt_ctxt->higher_dword.bit.at; + cmpt_ctxt_entries[21].value = cmpt_ctxt->higher_dword.bit.vec; + cmpt_ctxt_entries[22].value = cmpt_ctxt->higher_dword.bit.int_aggr; } /* @@ -3140,10 +3141,11 @@ static int qdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, return -QDMA_ERR_INV_PARAM; } - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { + if (ctxt->lower_dword.bit.trig_mode > + QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", __func__, - ctxt->trig_mode, + ctxt->lower_dword.bit.trig_mode, QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, -QDMA_ERR_INV_PARAM); return -QDMA_ERR_INV_PARAM; @@ -3158,43 +3160,57 @@ static int qdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, cmpt_ctxt[num_words_count++] = FIELD_SET(QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(QDMA_COMPL_CTXT_W0_FNC_ID_MASK, ctxt->fnc_id) | + ctxt->lower_dword.bit.en_stat_desc) | + FIELD_SET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, + ctxt->lower_dword.bit.en_int) | + FIELD_SET(QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK, + ctxt->lower_dword.bit.trig_mode) | + FIELD_SET(QDMA_COMPL_CTXT_W0_FNC_ID_MASK, + ctxt->lower_dword.bit.fnc_id) | FIELD_SET(QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK, - ctxt->counter_idx) | - FIELD_SET(QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK, ctxt->timer_idx) | - FIELD_SET(QDMA_COMPL_CTXT_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(QDMA_COMPL_CTXT_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(QDMA_COMPL_CTXT_W0_RING_SZ_MASK, ctxt->ringsz_idx); + ctxt->lower_dword.bit.counter_idx) | + FIELD_SET(QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK, + ctxt->lower_dword.bit.timer_idx) | + FIELD_SET(QDMA_COMPL_CTXT_W0_INT_ST_MASK, + ctxt->lower_dword.bit.in_st) | + FIELD_SET(QDMA_COMPL_CTXT_W0_COLOR_MASK, + ctxt->lower_dword.bit.color) | + FIELD_SET(QDMA_COMPL_CTXT_W0_RING_SZ_MASK, + ctxt->lower_dword.bit.ringsz_idx); cmpt_ctxt[num_words_count++] = FIELD_SET(QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK, baddr_l); cmpt_ctxt[num_words_count++] = FIELD_SET(QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK, baddr_h) | - FIELD_SET(QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK, ctxt->desc_sz) | + FIELD_SET(QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK, + ctxt->higher_dword.bit.desc_sz) | FIELD_SET(QDMA_COMPL_CTXT_W2_PIDX_L_MASK, pidx_l); cmpt_ctxt[num_words_count++] = FIELD_SET(QDMA_COMPL_CTXT_W3_PIDX_H_MASK, pidx_h) | FIELD_SET(QDMA_COMPL_CTXT_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(QDMA_COMPL_CTXT_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(QDMA_COMPL_CTXT_W3_ERR_MASK, ctxt->err) | + FIELD_SET(QDMA_COMPL_CTXT_W3_VALID_MASK, + ctxt->higher_dword.bit.valid) | + FIELD_SET(QDMA_COMPL_CTXT_W3_ERR_MASK, + ctxt->higher_dword.bit.err) | FIELD_SET(QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK, - ctxt->user_trig_pend); + ctxt->higher_dword.bit.user_trig_pend); cmpt_ctxt[num_words_count++] = FIELD_SET(QDMA_COMPL_CTXT_W4_TMR_RUN_MASK, - ctxt->timer_running) | - FIELD_SET(QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK, ctxt->full_upd) | + ctxt->higher_dword.bit.timer_running) | + FIELD_SET(QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK, + ctxt->higher_dword.bit.full_upd) | FIELD_SET(QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(QDMA_COMPL_CTXT_W4_AT_MASK, ctxt->at) | - FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, ctxt->vec) | - FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK, ctxt->int_aggr); + ctxt->higher_dword.bit.ovf_chk_dis) | + FIELD_SET(QDMA_COMPL_CTXT_W4_AT_MASK, + ctxt->higher_dword.bit.at) | + FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, + ctxt->higher_dword.bit.vec) | + FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK, + ctxt->higher_dword.bit.int_aggr); return qdma_indirect_reg_write(dev_hndl, sel, hw_qid, cmpt_ctxt, num_words_count); @@ -3229,34 +3245,35 @@ static int qdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, if (rv < 0) return rv; - ctxt->en_stat_desc = + ctxt->lower_dword.bit.en_stat_desc = FIELD_GET(QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = + ctxt->lower_dword.bit.en_int = + FIELD_GET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, cmpt_ctxt[0]); + ctxt->lower_dword.bit.trig_mode = FIELD_GET(QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = + ctxt->lower_dword.bit.fnc_id = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_FNC_ID_MASK, cmpt_ctxt[0])); - ctxt->counter_idx = + ctxt->lower_dword.bit.counter_idx = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK, cmpt_ctxt[0])); - ctxt->timer_idx = + ctxt->lower_dword.bit.timer_idx = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK, cmpt_ctxt[0])); - ctxt->in_st = + ctxt->lower_dword.bit.in_st = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_INT_ST_MASK, cmpt_ctxt[0])); - ctxt->color = + ctxt->lower_dword.bit.color = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_COLOR_MASK, cmpt_ctxt[0])); - ctxt->ringsz_idx = + ctxt->lower_dword.bit.ringsz_idx = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_RING_SZ_MASK, cmpt_ctxt[0])); baddr_l = FIELD_GET(QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK, cmpt_ctxt[1]); baddr_h = FIELD_GET(QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK, cmpt_ctxt[2]); - ctxt->desc_sz = + ctxt->higher_dword.bit.desc_sz = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK, cmpt_ctxt[2])); pidx_l = FIELD_GET(QDMA_COMPL_CTXT_W2_PIDX_L_MASK, cmpt_ctxt[2]); @@ -3265,23 +3282,25 @@ static int qdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, ctxt->cidx = (uint16_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_CIDX_MASK, cmpt_ctxt[3])); - ctxt->valid = + ctxt->higher_dword.bit.valid = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_VALID_MASK, cmpt_ctxt[3])); - ctxt->err = + ctxt->higher_dword.bit.err = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_ERR_MASK, cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) + ctxt->higher_dword.bit.user_trig_pend = (uint8_t) (FIELD_GET(QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK, cmpt_ctxt[3])); - ctxt->timer_running = + ctxt->higher_dword.bit.timer_running = FIELD_GET(QDMA_COMPL_CTXT_W4_TMR_RUN_MASK, cmpt_ctxt[4]); - ctxt->full_upd = + ctxt->higher_dword.bit.full_upd = FIELD_GET(QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = + ctxt->higher_dword.bit.ovf_chk_dis = FIELD_GET(QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(QDMA_COMPL_CTXT_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) + ctxt->higher_dword.bit.at = + FIELD_GET(QDMA_COMPL_CTXT_W4_AT_MASK, cmpt_ctxt[4]); + ctxt->higher_dword.bit.vec = + FIELD_GET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, cmpt_ctxt[4]); + ctxt->higher_dword.bit.int_aggr = (uint8_t) (FIELD_GET(QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK, cmpt_ctxt[4])); ctxt->bs_addr = diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.h index 9cb5247f..3accd8cb 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_access.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_reg.h b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_reg.h index d3876c0c..cad26539 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_reg.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_access/qdma_soft_access/qdma_soft_reg.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_compat.h b/QDMA/linux-kernel/driver/libqdma/qdma_compat.h index ded71b58..e3549a56 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_compat.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_compat.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_context.c b/QDMA/linux-kernel/driver/libqdma/qdma_context.c index 246280b3..96b99489 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_context.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_context.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -198,29 +198,32 @@ static int make_cmpt_context(struct qdma_descq *descq, memset(cmpt_ctxt, 0, sizeof(struct qdma_descq_cmpt_ctxt)); - cmpt_ctxt->en_stat_desc = descq->conf.cmpl_stat_en; - cmpt_ctxt->en_int = descq->conf.cmpl_en_intr; - cmpt_ctxt->trig_mode = descq->conf.cmpl_trig_mode; - cmpt_ctxt->fnc_id = descq->xdev->func_id; - cmpt_ctxt->timer_idx = descq->conf.cmpl_timer_idx; - cmpt_ctxt->counter_idx = descq->conf.cmpl_cnt_th_idx; - cmpt_ctxt->color = 1; - cmpt_ctxt->ringsz_idx = descq->conf.cmpl_rng_sz_idx; + cmpt_ctxt->lower_dword.bit.en_stat_desc = descq->conf.cmpl_stat_en; + cmpt_ctxt->lower_dword.bit.en_int = descq->conf.cmpl_en_intr; + cmpt_ctxt->lower_dword.bit.trig_mode = descq->conf.cmpl_trig_mode; + cmpt_ctxt->lower_dword.bit.fnc_id = descq->xdev->func_id; + cmpt_ctxt->lower_dword.bit.timer_idx = descq->conf.cmpl_timer_idx; + cmpt_ctxt->lower_dword.bit.counter_idx = descq->conf.cmpl_cnt_th_idx; + cmpt_ctxt->lower_dword.bit.color = 1; + cmpt_ctxt->lower_dword.bit.ringsz_idx = descq->conf.cmpl_rng_sz_idx; cmpt_ctxt->bs_addr = descq->desc_cmpt_bus; - cmpt_ctxt->desc_sz = descq->conf.cmpl_desc_sz; - cmpt_ctxt->full_upd = descq->conf.adaptive_rx; + cmpt_ctxt->higher_dword.bit.desc_sz = descq->conf.cmpl_desc_sz; + cmpt_ctxt->higher_dword.bit.full_upd = descq->conf.adaptive_rx; - cmpt_ctxt->valid = 1; + cmpt_ctxt->higher_dword.bit.valid = 1; + if (descq->conf.st && descq->conf.q_type == Q_C2H) + cmpt_ctxt->higher_dword.bit.dir_c2h = 1; - cmpt_ctxt->ovf_chk_dis = descq->conf.cmpl_ovf_chk_dis; + cmpt_ctxt->higher_dword.bit.ovf_chk_dis = + descq->conf.cmpl_ovf_chk_dis; if ((descq->xdev->conf.qdma_drv_mode == INDIRECT_INTR_MODE) || (descq->xdev->conf.qdma_drv_mode == AUTO_MODE)) { ring_index = get_intr_ring_index(descq->xdev, descq->intr_id); - cmpt_ctxt->vec = ring_index; - cmpt_ctxt->int_aggr = 1; + cmpt_ctxt->higher_dword.bit.vec = ring_index; + cmpt_ctxt->higher_dword.bit.int_aggr = 1; } else { - cmpt_ctxt->vec = descq->intr_id; + cmpt_ctxt->higher_dword.bit.vec = descq->intr_id; } return 0; diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_context.h b/QDMA/linux-kernel/driver/libqdma/qdma_context.h index 9d21d484..6549f053 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_context.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_context.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.c b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.c index 0c61bad9..4cc84adb 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.h b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.h index 2b3600a3..ad4203de 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.c b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.c index 3daa36ac..80e02d49 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.h b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.h index 5a74c791..3776bb58 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_dev.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.c b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.c index c323c475..5874dd93 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.h b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.h index 37d62e7d..e2766c22 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_debugfs_queue.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_descq.c b/QDMA/linux-kernel/driver/libqdma/qdma_descq.c index 9cc4e49b..c2f19d1d 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_descq.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_descq.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -31,9 +31,7 @@ #include "qdma_context.h" #include "qdma_st_c2h.h" #include "qdma_access_common.h" -#ifdef __XRT__ #include "eqdma_soft_access.h" -#endif #include "thread.h" #include "qdma_ul_ext.h" #include "version.h" @@ -199,9 +197,9 @@ static ssize_t descq_mm_proc_request(struct qdma_descq *descq) qconf->aperture_size : QDMA_DESC_BLEN_MAX; u8 keyhole_en = qconf->aperture_size ? 1 : 0; u64 ep_addr_max = 0; -#ifdef __XRT__ + u32 ip_version = 0; + if (descq->xdev->version_info.ip_type == EQDMA_SOFT_IP) { - uint32_t ip_version; #ifndef __QDMA_VF__ uint8_t is_vf = 0; #else @@ -209,12 +207,12 @@ static ssize_t descq_mm_proc_request(struct qdma_descq *descq) #endif rv = eqdma_get_ip_version(descq->xdev, is_vf, &ip_version); if (ip_version == EQDMA_IP_VERSION_5) { - pr_info("EQDMA Soft IP 5.0 supports descriptor length < 64K.\n"); - aperture = qconf->aperture_size ? - qconf->aperture_size : SOFT_QDMA_DESC_BLEN_MAX; + if (qconf->aperture_size == 0) { + aperture = SOFT_EQDMA_DESC_BLEN_MAX; + pr_debug("aperture_size : %d\n", aperture); + } } } -#endif lock_descq(descq); /* process completion of submitted requests */ @@ -305,6 +303,21 @@ static ssize_t descq_mm_proc_request(struct qdma_descq *descq) dma_addr_t src_addr = sg->dma_addr; unsigned int pg_off = sg->offset; + if (descq->xdev->version_info.ip_type == + EQDMA_SOFT_IP) { + if (ip_version == EQDMA_IP_VERSION_5) { + if (qconf->aperture_size >= + SOFT_EQDMA_DESC_BLEN_MAX && + sg->len >= + SOFT_EQDMA_DESC_MAX_LEN) { + pr_debug("EQDMA Soft IP 5.0 supports descriptor data transfer length < 64K.\n"); + descq->proc_req_running = 0; + unlock_descq(descq); + return -EINVAL; + } + } + } + pr_debug("desc %u/%u, sgl %d, len %u,%u, offset %u.\n", desc_cnt, desc_max, i, len, tlen, sg_offset); @@ -1591,7 +1604,8 @@ int qdma_descq_dump_desc(struct qdma_descq *descq, int start, len += snprintf(buf + len, buflen - len, " fl pg 0x%p, 0x%llx.\n", fl->pg, fl->dma_addr); - fl++; + if (i != (descq->conf.rngsz - 1)) + fl++; } else buf[len++] = '\n'; } diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_descq.h b/QDMA/linux-kernel/driver/libqdma/qdma_descq.h index bb1ba361..cd9909cb 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_descq.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_descq.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_device.c b/QDMA/linux-kernel/driver/libqdma/qdma_device.c index fcf80581..afa17688 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_device.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_device.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_device.h b/QDMA/linux-kernel/driver/libqdma/qdma_device.h index c8604674..5f7f316d 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_device.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_device.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_intr.c b/QDMA/linux-kernel/driver/libqdma/qdma_intr.c index 1a90a42f..7446c1a5 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_intr.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_intr.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -35,7 +35,7 @@ #ifndef __QDMA_VF__ static LIST_HEAD(legacy_intr_q_list); static spinlock_t legacy_intr_lock; -static spinlock_t legacy_q_add_lock; +static struct mutex legacy_q_add_lock; static unsigned long legacy_intr_flags = IRQF_SHARED; #endif @@ -602,7 +602,7 @@ int intr_setup(struct xlnx_dma_dev *xdev) #ifndef MBOX_INTERRUPT_DISABLE /** Dedicate 1 vector for mailbox interrupts */ - if (qdma_mbox_is_irq_availabe(xdev)) + if (xdev->dev_cap.mailbox_en && qdma_mbox_is_irq_available(xdev)) num_vecs_req++; #endif @@ -658,7 +658,7 @@ int intr_setup(struct xlnx_dma_dev *xdev) i = 0; /* This is mandatory, do not delete */ #ifndef MBOX_INTERRUPT_DISABLE - if (qdma_mbox_is_irq_availabe(xdev)) { + if (xdev->dev_cap.mailbox_en && qdma_mbox_is_irq_available(xdev)) { /* Mail box interrupt */ rv = intr_vector_setup(xdev, i, INTR_TYPE_MBOX, mbox_intr_handler); @@ -783,7 +783,7 @@ int intr_legacy_setup(struct qdma_descq *descq) return -EINVAL; } - spin_lock(&legacy_q_add_lock); + mutex_lock(&legacy_q_add_lock); req_irq = list_empty(&legacy_intr_q_list); rv = req_irq ? 0 : 1; @@ -794,7 +794,7 @@ int intr_legacy_setup(struct qdma_descq *descq) if (descq->xdev->hw.qdma_legacy_intr_conf(descq->xdev, DISABLE)) { - spin_unlock(&legacy_q_add_lock); + mutex_unlock(&legacy_q_add_lock); return -EINVAL; } @@ -812,7 +812,7 @@ int intr_legacy_setup(struct qdma_descq *descq) } if (descq->xdev->hw.qdma_legacy_intr_conf(descq->xdev, ENABLE)) { - spin_unlock(&legacy_q_add_lock); + mutex_unlock(&legacy_q_add_lock); return -EINVAL; } } else @@ -820,7 +820,7 @@ int intr_legacy_setup(struct qdma_descq *descq) &legacy_intr_q_list); exit_intr_setup: - spin_unlock(&legacy_q_add_lock); + mutex_unlock(&legacy_q_add_lock); return rv; } #endif @@ -1019,6 +1019,6 @@ int get_intr_ring_index(struct xlnx_dma_dev *xdev, u32 vector_index) void intr_legacy_init(void) { #ifndef __QDMA_VF__ - spin_lock_init(&legacy_q_add_lock); + mutex_init(&legacy_q_add_lock); #endif } diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_intr.h b/QDMA/linux-kernel/driver/libqdma/qdma_intr.h index c26174e5..6060f46a 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_intr.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_intr.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_license.h b/QDMA/linux-kernel/driver/libqdma/qdma_license.h index 31750730..7be22bfc 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_license.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_license.h @@ -4,7 +4,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c b/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c index 0161d04d..a2dd527b 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -442,7 +442,7 @@ static void mbox_timer_handler(unsigned long arg) queue_work(mbox->workq, &mbox->tx_work); } -bool qdma_mbox_is_irq_availabe(struct xlnx_dma_dev *xdev) +bool qdma_mbox_is_irq_available(struct xlnx_dma_dev *xdev) { /*MBOX is available in all QDMA Soft Devices for vivado release > * 2019.1 @@ -489,7 +489,7 @@ void qdma_mbox_stop(struct xlnx_dma_dev *xdev) } while (retry_count != 0); mbox_timer_stop(&xdev->mbox); pr_debug("func_id=%d retry_count=%d\n", xdev->func_id, retry_count); - if (qdma_mbox_is_irq_availabe(xdev)) { + if (xdev->dev_cap.mailbox_en && qdma_mbox_is_irq_available(xdev)) { if (!xdev->mbox.rx_poll) qdma_mbox_disable_interrupts(xdev, QDMA_DEV); } @@ -574,7 +574,7 @@ int qdma_mbox_init(struct xlnx_dma_dev *xdev) #endif /* ack any received messages in the Q */ qdma_mbox_hw_init(xdev, QDMA_DEV); - if (qdma_mbox_is_irq_availabe(xdev)) { + if (xdev->dev_cap.mailbox_en && qdma_mbox_is_irq_available(xdev)) { if ((xdev->conf.qdma_drv_mode != POLL_MODE) && (xdev->conf.qdma_drv_mode != LEGACY_INTR_MODE)) { mbox->rx_poll = 0; diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_mbox.h b/QDMA/linux-kernel/driver/libqdma/qdma_mbox.h index e027edaa..9270f316 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_mbox.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_mbox.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -120,7 +120,7 @@ void qdma_mbox_cleanup(struct xlnx_dma_dev *xdev); void qdma_mbox_stop(struct xlnx_dma_dev *xdev); void qdma_mbox_start(struct xlnx_dma_dev *xdev); void qdma_mbox_poll_start(struct xlnx_dma_dev *xdev); -bool qdma_mbox_is_irq_availabe(struct xlnx_dma_dev *xdev); +bool qdma_mbox_is_irq_available(struct xlnx_dma_dev *xdev); /*****************************************************************************/ diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_platform.c b/QDMA/linux-kernel/driver/libqdma/qdma_platform.c index d008d92a..672b693f 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_platform.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_platform.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_platform_env.h b/QDMA/linux-kernel/driver/libqdma/qdma_platform_env.h index 6649bfc7..fa26c9af 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_platform_env.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_platform_env.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_regs.c b/QDMA/linux-kernel/driver/libqdma/qdma_regs.c index 920176cf..81e1e9ed 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_regs.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_regs.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_regs.h b/QDMA/linux-kernel/driver/libqdma/qdma_regs.h index 4e1d1bb1..884f4b33 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_regs.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_regs.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_sriov.c b/QDMA/linux-kernel/driver/libqdma/qdma_sriov.c index 4911bf81..5bbb5f77 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_sriov.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_sriov.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.c b/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.c index 80a8d739..57481850 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.h b/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.h index 1d6971f0..b415a65c 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_st_c2h.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_thread.c b/QDMA/linux-kernel/driver/libqdma/qdma_thread.c index cf96fd20..e8e2423a 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_thread.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_thread.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_thread.h b/QDMA/linux-kernel/driver/libqdma/qdma_thread.h index 48b26804..d2bfa4ec 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_thread.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_thread.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_ul_ext.h b/QDMA/linux-kernel/driver/libqdma/qdma_ul_ext.h index ae699386..19082b5a 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_ul_ext.h +++ b/QDMA/linux-kernel/driver/libqdma/qdma_ul_ext.h @@ -4,7 +4,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/thread.c b/QDMA/linux-kernel/driver/libqdma/thread.c index d0c09091..5a326c71 100755 --- a/QDMA/linux-kernel/driver/libqdma/thread.c +++ b/QDMA/linux-kernel/driver/libqdma/thread.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/thread.h b/QDMA/linux-kernel/driver/libqdma/thread.h index 56346ce6..2f573dd5 100755 --- a/QDMA/linux-kernel/driver/libqdma/thread.h +++ b/QDMA/linux-kernel/driver/libqdma/thread.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/libqdma/version.h b/QDMA/linux-kernel/driver/libqdma/version.h index 5b6e3324..8243fb42 100755 --- a/QDMA/linux-kernel/driver/libqdma/version.h +++ b/QDMA/linux-kernel/driver/libqdma/version.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,8 +23,8 @@ #define LIBQDMA_MODULE_NAME "libqdma" #define LIBQDMA_MODULE_DESC "Xilinx QDMA Library" -#define LIBQDMA_VERSION_MAJOR 2023 -#define LIBQDMA_VERSION_MINOR 2 +#define LIBQDMA_VERSION_MAJOR 2024 +#define LIBQDMA_VERSION_MINOR 1 #define LIBQDMA_VERSION_PATCH 0 #define LIBQDMA_VERSION_STR \ diff --git a/QDMA/linux-kernel/driver/libqdma/xdev.c b/QDMA/linux-kernel/driver/libqdma/xdev.c index 19880a51..36e53a59 100755 --- a/QDMA/linux-kernel/driver/libqdma/xdev.c +++ b/QDMA/linux-kernel/driver/libqdma/xdev.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -42,9 +42,6 @@ #ifdef DEBUGFS #include "qdma_debugfs_dev.h" #endif -#ifdef __XRT__ -#include "qdma_access_errors.h" -#endif #ifdef __LIST_NEXT_ENTRY__ #define list_next_entry(pos, member) \ @@ -308,7 +305,11 @@ int xdev_list_dump(char *buf, int buflen) mutex_lock(&xdev_mutex); list_for_each_entry_safe(xdev, tmp, &xdev_list, list_head) { len += snprintf(buf + len, buflen - len, +#ifdef CONFIG_PCI_DOMAINS_GENERIC + "qdma%09x\t%02x:%02x.%02x\n", +#else "qdma%05x\t%02x:%02x.%02x\n", +#endif xdev->conf.bdf, xdev->conf.pdev->bus->number, PCI_SLOT(xdev->conf.pdev->devfn), PCI_FUNC(xdev->conf.pdev->devfn)); @@ -337,9 +338,13 @@ static inline void xdev_list_add(struct xlnx_dma_dev *xdev) u32 last_dev = 0; mutex_lock(&xdev_mutex); - bdf = ((xdev->conf.pdev->bus->number << PCI_SHIFT_BUS) | - (PCI_SLOT(xdev->conf.pdev->devfn) << PCI_SHIFT_DEV) | - PCI_FUNC(xdev->conf.pdev->devfn)); + bdf = ( +#ifdef CONFIG_PCI_DOMAINS_GENERIC + (xdev->conf.pdev->bus->domain_nr << PCI_SHIFT_DOMAIN) | +#endif + (xdev->conf.pdev->bus->number << PCI_SHIFT_BUS) | + (PCI_SLOT(xdev->conf.pdev->devfn) << PCI_SHIFT_DEV) | + PCI_FUNC(xdev->conf.pdev->devfn)); xdev->conf.bdf = bdf; list_add_tail(&xdev->list_head, &xdev_list); @@ -578,14 +583,7 @@ static int xdev_identify_bars(struct xlnx_dma_dev *xdev, struct pci_dev *pdev) if (rv < 0) { pr_err("get AXI Master Lite bar failed with error = %d", rv); -#ifdef __XRT__ - /** This change is for XRT application, - * when there is no user BAR in desin - */ - rv = QDMA_ERR_HWACC_BAR_NOT_FOUND; -#else return xdev->hw.qdma_get_error_code(rv); -#endif } pr_info("AXI Master Lite BAR %d.\n", @@ -1062,7 +1060,11 @@ int qdma_device_open(const char *mod_name, struct qdma_dev_conf *conf, xdev_list_add(xdev); rv = snprintf(xdev->conf.name, QDMA_DEV_NAME_MAXLEN, +#ifdef CONFIG_PCI_DOMAINS_GENERIC + "qdma%09x-p%s", +#else "qdma%05x-p%s", +#endif xdev->conf.bdf, dev_name(&xdev->conf.pdev->dev)); xdev->conf.name[rv] = '\0'; @@ -1114,9 +1116,6 @@ int qdma_device_open(const char *mod_name, struct qdma_dev_conf *conf, goto unmap_bars; #endif - pr_info("Vivado version = %s\n", - xdev->version_info.qdma_vivado_release_id_str); - #ifndef __QDMA_VF__ rv = xdev->hw.qdma_get_function_number(xdev, &xdev->func_id); if (rv < 0) { diff --git a/QDMA/linux-kernel/driver/libqdma/xdev.h b/QDMA/linux-kernel/driver/libqdma/xdev.h index d79eb2b8..fd311282 100755 --- a/QDMA/linux-kernel/driver/libqdma/xdev.h +++ b/QDMA/linux-kernel/driver/libqdma/xdev.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -95,17 +95,17 @@ enum qdma_pf_devices { */ #define QDMA_DESC_BLEN_MAX ((1 << (QDMA_DESC_BLEN_BITS)) - 1) -#ifdef __XRT__ /** - * number of bits to describe the SOFT DMA transfer descriptor + * number of bits to describe the DMA transfer descriptor for EQDMA Soft 5.0 */ -#define SOFT_QDMA_DESC_BLEN_BITS 15 +#define SOFT_EQDMA_DESC_BLEN_BITS 15 /** - * maximum size of a single SOFT DMA transfer descriptor + * maximum size of a single DMA transfer descriptor for EQDMA Soft 5.0 */ -#define SOFT_QDMA_DESC_BLEN_MAX (1 << (SOFT_QDMA_DESC_BLEN_BITS)) -#endif +#define SOFT_EQDMA_DESC_BLEN_MAX (1 << (SOFT_EQDMA_DESC_BLEN_BITS)) + +#define SOFT_EQDMA_DESC_MAX_LEN (2 << (SOFT_EQDMA_DESC_BLEN_BITS)) /** * obtain the 32 most significant (high) bits of a 32-bit or 64-bit address diff --git a/QDMA/linux-kernel/driver/make_rules/common_flags.mk b/QDMA/linux-kernel/driver/make_rules/common_flags.mk index 69bebded..db114811 100755 --- a/QDMA/linux-kernel/driver/make_rules/common_flags.mk +++ b/QDMA/linux-kernel/driver/make_rules/common_flags.mk @@ -2,7 +2,7 @@ # * This file is part of the Xilinx DMA IP Core driver for Linux # * # * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is free software; you can redistribute it and/or modify it # * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/make_rules/distro_check.mk b/QDMA/linux-kernel/driver/make_rules/distro_check.mk index 4689147d..3a9d9bf4 100755 --- a/QDMA/linux-kernel/driver/make_rules/distro_check.mk +++ b/QDMA/linux-kernel/driver/make_rules/distro_check.mk @@ -2,7 +2,7 @@ # * This file is part of the Xilinx DMA IP Core driver for Linux # * # * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is free software; you can redistribute it and/or modify it # * under the terms and conditions of the GNU General Public License, @@ -96,6 +96,10 @@ ifeq ($(distro),) ifeq ($(kversion),6) distro := GIT endif + + ifeq ($(kversion),7) + distro := GIT + endif endif # assume kernel.org kernels ifeq ($(distro),) diff --git a/QDMA/linux-kernel/driver/make_rules/kernel_check.mk b/QDMA/linux-kernel/driver/make_rules/kernel_check.mk index ab2b3698..16ee0f9d 100755 --- a/QDMA/linux-kernel/driver/make_rules/kernel_check.mk +++ b/QDMA/linux-kernel/driver/make_rules/kernel_check.mk @@ -2,7 +2,7 @@ # * This file is part of the Xilinx DMA IP Core driver for Linux # * # * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is free software; you can redistribute it and/or modify it # * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/src/Makefile b/QDMA/linux-kernel/driver/src/Makefile index 1b5b9bd0..bb309d98 100755 --- a/QDMA/linux-kernel/driver/src/Makefile +++ b/QDMA/linux-kernel/driver/src/Makefile @@ -2,7 +2,7 @@ # * This file is part of the Xilinx DMA IP Core driver for Linux # * # * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is free software; you can redistribute it and/or modify it # * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/src/cdev.c b/QDMA/linux-kernel/driver/src/cdev.c index bd7d6812..b7ea4550 100755 --- a/QDMA/linux-kernel/driver/src/cdev.c +++ b/QDMA/linux-kernel/driver/src/cdev.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -51,6 +51,9 @@ struct xlnx_phy_dev { struct list_head list_head; /**< board list */ unsigned int major; /**< major number per board */ unsigned int device_bus; /**< PCIe device bus number per board */ +#ifdef CONFIG_PCI_DOMAINS_GENERIC + unsigned int device_bus_domain; /**< PCIe bus domain per board */ +#endif unsigned int dma_device_index; }; @@ -567,12 +570,40 @@ static ssize_t cdev_aio_read(struct kiocb *iocb, const struct iovec *io, #if KERNEL_VERSION(3, 16, 0) <= LINUX_VERSION_CODE static ssize_t cdev_write_iter(struct kiocb *iocb, struct iov_iter *io) { - return cdev_aio_write(iocb, io->iov, io->nr_segs, iocb->ki_pos); +#ifdef RHEL_RELEASE_VERSION + #if RHEL_RELEASE_VERSION(9, 4) > RHEL_RELEASE_CODE + return cdev_aio_write(iocb, io->iov, io->nr_segs, iocb->ki_pos); + #else + return cdev_aio_write(iocb, iter_iov(io), io->nr_segs, + iocb->ki_pos); + #endif +#else + #if KERNEL_VERSION(6, 4, 0) > LINUX_VERSION_CODE + return cdev_aio_write(iocb, io->iov, io->nr_segs, iocb->ki_pos); + #else + return cdev_aio_write(iocb, iter_iov(io), io->nr_segs, + iocb->ki_pos); + #endif +#endif } static ssize_t cdev_read_iter(struct kiocb *iocb, struct iov_iter *io) { - return cdev_aio_read(iocb, io->iov, io->nr_segs, iocb->ki_pos); +#ifdef RHEL_RELEASE_VERSION + #if RHEL_RELEASE_VERSION(9, 4) > RHEL_RELEASE_CODE + return cdev_aio_read(iocb, io->iov, io->nr_segs, iocb->ki_pos); + #else + return cdev_aio_read(iocb, iter_iov(io), io->nr_segs, + iocb->ki_pos); + #endif +#else + #if KERNEL_VERSION(6, 4, 0) > LINUX_VERSION_CODE + return cdev_aio_read(iocb, io->iov, io->nr_segs, iocb->ki_pos); + #else + return cdev_aio_read(iocb, iter_iov(io), io->nr_segs, + iocb->ki_pos); + #endif +#endif } #endif @@ -743,6 +774,10 @@ int qdma_cdev_device_init(struct qdma_cdev_cb *xcb) xdev = (struct xlnx_dma_dev *)xcb->xpdev->dev_hndl; list_for_each_entry_safe(phy_dev, tmp, &xlnx_phy_dev_list, list_head) { if (phy_dev->device_bus == xcb->xpdev->pdev->bus->number && +#ifdef CONFIG_PCI_DOMAINS_GENERIC + phy_dev->device_bus_domain == + xcb->xpdev->pdev->bus->domain_nr && +#endif phy_dev->dma_device_index == xdev->dma_device_index) { xcb->cdev_major = phy_dev->major; mutex_unlock(&xlnx_phy_dev_mutex); @@ -768,6 +803,9 @@ int qdma_cdev_device_init(struct qdma_cdev_cb *xcb) new_phy_dev->major = xcb->cdev_major; new_phy_dev->device_bus = xcb->xpdev->pdev->bus->number; +#ifdef CONFIG_PCI_DOMAINS_GENERIC + new_phy_dev->device_bus_domain = xcb->xpdev->pdev->bus->domain_nr; +#endif new_phy_dev->dma_device_index = xdev->dma_device_index; xlnx_phy_dev_list_add(new_phy_dev); @@ -780,7 +818,19 @@ int qdma_cdev_device_init(struct qdma_cdev_cb *xcb) int qdma_cdev_init(void) { - qdma_class = class_create(THIS_MODULE, QDMA_CDEV_CLASS_NAME); +#ifdef RHEL_RELEASE_VERSION + #if RHEL_RELEASE_VERSION(9, 4) > RHEL_RELEASE_CODE + qdma_class = class_create(THIS_MODULE, QDMA_CDEV_CLASS_NAME); + #else + qdma_class = class_create(QDMA_CDEV_CLASS_NAME); + #endif +#else + #if KERNEL_VERSION(6, 4, 0) > LINUX_VERSION_CODE + qdma_class = class_create(THIS_MODULE, QDMA_CDEV_CLASS_NAME); + #else + qdma_class = class_create(QDMA_CDEV_CLASS_NAME); + #endif +#endif if (IS_ERR(qdma_class)) { pr_err("%s: failed to create class 0x%lx.", QDMA_CDEV_CLASS_NAME, (unsigned long)qdma_class); diff --git a/QDMA/linux-kernel/driver/src/cdev.h b/QDMA/linux-kernel/driver/src/cdev.h index 371e5280..4239ab0d 100755 --- a/QDMA/linux-kernel/driver/src/cdev.h +++ b/QDMA/linux-kernel/driver/src/cdev.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -90,7 +90,7 @@ struct qdma_cdev { ssize_t (*fp_aiorw)(unsigned long dev_hndl, unsigned long qhndl, unsigned long count, struct qdma_request **reqv); /** name of the character device*/ - char name[0]; + char name[QDMA_QUEUE_NAME_MAXLEN]; }; /** diff --git a/QDMA/linux-kernel/driver/src/nl.c b/QDMA/linux-kernel/driver/src/nl.c index 5a3da367..45b7d8fe 100755 --- a/QDMA/linux-kernel/driver/src/nl.c +++ b/QDMA/linux-kernel/driver/src/nl.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -39,7 +39,7 @@ static int xnl_dev_list(struct sk_buff *skb2, struct genl_info *info); #ifdef RHEL_RELEASE_VERSION -#if RHEL_RELEASE_VERSION(8, 3) > RHEL_RELEASE_CODE +#if RHEL_RELEASE_VERSION(9, 99) >= RHEL_RELEASE_CODE static struct nla_policy xnl_policy[XNL_ATTR_MAX] = { [XNL_ATTR_GENMSG] = { .type = NLA_NUL_STRING }, @@ -70,6 +70,9 @@ static struct nla_policy xnl_policy[XNL_ATTR_MAX] = { [XNL_ATTR_REG_ADDR] = { .type = NLA_U32 }, [XNL_ATTR_REG_VAL] = { .type = NLA_U32 }, + [XNL_ATTR_CSR_INDEX] = { .type = NLA_U32 }, + [XNL_ATTR_CSR_COUNT] = { .type = NLA_U32 }, + [XNL_ATTR_QIDX] = { .type = NLA_U32 }, [XNL_ATTR_NUM_Q] = { .type = NLA_U32 }, [XNL_ATTR_QFLAG] = { .type = NLA_U32 }, @@ -86,6 +89,9 @@ static struct nla_policy xnl_policy[XNL_ATTR_MAX] = { [XNL_ATTR_RANGE_END] = { .type = NLA_U32 }, [XNL_ATTR_INTR_VECTOR_IDX] = { .type = NLA_U32 }, + [XNL_ATTR_INTR_VECTOR_START_IDX] = { .type = NLA_U32 }, + [XNL_ATTR_INTR_VECTOR_END_IDX] = { .type = NLA_U32 }, + [XNL_ATTR_RSP_BUF_LEN] = { .type = NLA_U32 }, [XNL_ATTR_PIPE_GL_MAX] = { .type = NLA_U32 }, [XNL_ATTR_PIPE_FLOW_ID] = { .type = NLA_U32 }, [XNL_ATTR_PIPE_SLR_ID] = { .type = NLA_U32 }, @@ -95,10 +101,18 @@ static struct nla_policy xnl_policy[XNL_ATTR_MAX] = { [XNL_ATTR_Q_STATE] = { .type = NLA_U32 }, [XNL_ATTR_ERROR] = { .type = NLA_U32 }, [XNL_ATTR_PING_PONG_EN] = { .type = NLA_U32 }, + [XNL_ATTR_APERTURE_SZ] = { .type = NLA_U32 }, + [XNL_ATTR_DEV_STAT_PING_PONG_LATMIN1] = { .type = NLA_U32 }, + [XNL_ATTR_DEV_STAT_PING_PONG_LATMIN2] = { .type = NLA_U32 }, + [XNL_ATTR_DEV_STAT_PING_PONG_LATMAX1] = { .type = NLA_U32 }, + [XNL_ATTR_DEV_STAT_PING_PONG_LATMAX2] = { .type = NLA_U32 }, + [XNL_ATTR_DEV_STAT_PING_PONG_LATAVG1] = { .type = NLA_U32 }, + [XNL_ATTR_DEV_STAT_PING_PONG_LATAVG2] = { .type = NLA_U32 }, [XNL_ATTR_DEV] = { .type = NLA_BINARY, .len = QDMA_DEV_ATTR_STRUCT_SIZE, }, [XNL_ATTR_GLOBAL_CSR] = { .type = NLA_BINARY, .len = QDMA_DEV_GLOBAL_CSR_STRUCT_SIZE, }, + [XNL_ATTR_NUM_REGS] = { .type = NLA_U32 }, #ifdef ERR_DEBUG [XNL_ATTR_QPARAM_ERR_INFO] = { .type = NLA_U32 }, #endif @@ -179,6 +193,7 @@ static struct nla_policy xnl_policy[XNL_ATTR_MAX] = { .len = QDMA_DEV_ATTR_STRUCT_SIZE, }, [XNL_ATTR_GLOBAL_CSR] = { .type = NLA_BINARY, .len = QDMA_DEV_GLOBAL_CSR_STRUCT_SIZE, }, + [XNL_ATTR_NUM_REGS] = { .type = NLA_U32 }, #ifdef ERR_DEBUG [XNL_ATTR_QPARAM_ERR_INFO] = { .type = NLA_U32 }, #endif @@ -222,7 +237,7 @@ static int xnl_err_induce(struct sk_buff *skb2, struct genl_info *info); #endif #ifdef RHEL_RELEASE_VERSION -#if RHEL_RELEASE_VERSION(8, 3) > RHEL_RELEASE_CODE +#if RHEL_RELEASE_VERSION(9, 99) >= RHEL_RELEASE_CODE #define GENL_OPS_POLICY #endif #else @@ -1075,10 +1090,6 @@ static int xnl_dev_version_capabilities(struct sk_buff *skb2, "=============Hardware Version============\n\n"); rv += snprintf(buf + rv, buflen - rv, "RTL Version : %s\n", ver_info.rtl_version_str); - rv += snprintf(buf + rv, - buflen - rv, - "Vivado ReleaseID : %s\n", - ver_info.vivado_release_str); rv += snprintf(buf + rv, buflen - rv, "QDMA Device Type : %s\n", diff --git a/QDMA/linux-kernel/driver/src/nl.h b/QDMA/linux-kernel/driver/src/nl.h index e1d40245..cfa3c23a 100755 --- a/QDMA/linux-kernel/driver/src/nl.h +++ b/QDMA/linux-kernel/driver/src/nl.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/src/pci_ids.h b/QDMA/linux-kernel/driver/src/pci_ids.h index 61a3da1e..a7bdb976 100755 --- a/QDMA/linux-kernel/driver/src/pci_ids.h +++ b/QDMA/linux-kernel/driver/src/pci_ids.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/src/qdma_mod.c b/QDMA/linux-kernel/driver/src/qdma_mod.c index 11791f97..4a94f57a 100755 --- a/QDMA/linux-kernel/driver/src/qdma_mod.c +++ b/QDMA/linux-kernel/driver/src/qdma_mod.c @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1339,8 +1339,10 @@ static int xpdev_qdata_realloc(struct xlnx_pci_dev *xpdev, unsigned int qmax) kfree(xpdev->qdata); xpdev->qdata = NULL; - if (!qmax) + if (!qmax) { + xpdev->qmax = qmax; return 0; + } xpdev->qdata = kzalloc(qmax * 3 * sizeof(struct xlnx_qdata), GFP_KERNEL); if (!xpdev->qdata) { diff --git a/QDMA/linux-kernel/driver/src/qdma_mod.h b/QDMA/linux-kernel/driver/src/qdma_mod.h index 3cd04a51..a6839096 100755 --- a/QDMA/linux-kernel/driver/src/qdma_mod.h +++ b/QDMA/linux-kernel/driver/src/qdma_mod.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/driver/src/version.h b/QDMA/linux-kernel/driver/src/version.h index 57274288..2218c922 100755 --- a/QDMA/linux-kernel/driver/src/version.h +++ b/QDMA/linux-kernel/driver/src/version.h @@ -2,7 +2,7 @@ * This file is part of the Xilinx DMA IP Core driver for Linux * * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * This source code is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -29,10 +29,10 @@ #define DRV_MODULE_NAME "qdma-pf" #define DRV_MODULE_DESC "Xilinx QDMA PF Reference Driver" #endif /* #ifdef __QDMA_VF__ */ -#define DRV_MODULE_RELDATE "Sept 2023" +#define DRV_MODULE_RELDATE "Dec 2024" -#define DRV_MOD_MAJOR 2023 -#define DRV_MOD_MINOR 2 +#define DRV_MOD_MAJOR 2024 +#define DRV_MOD_MINOR 1 #define DRV_MOD_PATCHLEVEL 0 #define DRV_MODULE_VERSION \ diff --git a/QDMA/linux-kernel/scripts/license-for-datafile_16bit_pattern.txt b/QDMA/linux-kernel/scripts/license-for-datafile_16bit_pattern.txt index 15469adb..7539381e 100755 --- a/QDMA/linux-kernel/scripts/license-for-datafile_16bit_pattern.txt +++ b/QDMA/linux-kernel/scripts/license-for-datafile_16bit_pattern.txt @@ -2,6 +2,7 @@ * THIS BINARY FILE IS GENERATED FROM XILINX TOOLS AND IS AVAILABLE EXCLUSIVELY IN BINARY FORMAT. * * Copyright © 2022 Xilinx, Inc. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in binary form only, without modification, is permitted provided that the following conditions are met: * @@ -16,4 +17,4 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - */ \ No newline at end of file + */ diff --git a/QDMA/linux-kernel/scripts/qdma_generate_conf_file.sh b/QDMA/linux-kernel/scripts/qdma_generate_conf_file.sh index c66cb1ad..adafd7f8 100755 --- a/QDMA/linux-kernel/scripts/qdma_generate_conf_file.sh +++ b/QDMA/linux-kernel/scripts/qdma_generate_conf_file.sh @@ -2,7 +2,7 @@ # * This file is part of the Xilinx DMA IP Core driver for Linux # * # * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is free software; you can redistribute it and/or modify it # * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/scripts/qdma_run_test_mm_vf.sh b/QDMA/linux-kernel/scripts/qdma_run_test_mm_vf.sh index 1692277c..0f93e534 100755 --- a/QDMA/linux-kernel/scripts/qdma_run_test_mm_vf.sh +++ b/QDMA/linux-kernel/scripts/qdma_run_test_mm_vf.sh @@ -2,7 +2,7 @@ # * This file is part of the Xilinx DMA IP Core driver for Linux # * # * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is free software; you can redistribute it and/or modify it # * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/scripts/qdma_run_test_pf.sh b/QDMA/linux-kernel/scripts/qdma_run_test_pf.sh index f49bead3..a611c4b4 100755 --- a/QDMA/linux-kernel/scripts/qdma_run_test_pf.sh +++ b/QDMA/linux-kernel/scripts/qdma_run_test_pf.sh @@ -2,7 +2,7 @@ # * This file is part of the Xilinx DMA IP Core driver for Linux # * # * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is free software; you can redistribute it and/or modify it # * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/scripts/qdma_run_test_st_vf.sh b/QDMA/linux-kernel/scripts/qdma_run_test_st_vf.sh index 754a4084..b1f9b103 100755 --- a/QDMA/linux-kernel/scripts/qdma_run_test_st_vf.sh +++ b/QDMA/linux-kernel/scripts/qdma_run_test_st_vf.sh @@ -2,7 +2,7 @@ # * This file is part of the Xilinx DMA IP Core driver for Linux # * # * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is free software; you can redistribute it and/or modify it # * under the terms and conditions of the GNU General Public License, diff --git a/QDMA/linux-kernel/scripts/qdma_vf_auto_tst.sh b/QDMA/linux-kernel/scripts/qdma_vf_auto_tst.sh index 4d7fed15..2b6984a6 100755 --- a/QDMA/linux-kernel/scripts/qdma_vf_auto_tst.sh +++ b/QDMA/linux-kernel/scripts/qdma_vf_auto_tst.sh @@ -2,7 +2,7 @@ # * This file is part of the Xilinx DMA IP Core driver for Linux # * # * Copyright (c) 2017-2022, Xilinx, Inc. All rights reserved. -# * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # * # * This source code is free software; you can redistribute it and/or modify it # * under the terms and conditions of the GNU General Public License, From 87c54f599685ef1b5d23fd99e9be06c7a80ea51d Mon Sep 17 00:00:00 2001 From: Bharat Kumar Gogada Date: Fri, 3 Jan 2025 12:40:45 +0530 Subject: [PATCH 2/8] QDMA DPDK reference driver for v2024.1.0 release Signed-off-by: Bharat Kumar Gogada --- QDMA/DPDK/RELEASE | 25 +- QDMA/DPDK/docs/README.txt | 19 +- QDMA/DPDK/drivers/net/qdma/meson.build | 7 +- QDMA/DPDK/drivers/net/qdma/qdma.h | 2 +- .../eqdma_cpm5_access/eqdma_cpm5_access.c | 207 +++++---- .../eqdma_cpm5_access/eqdma_cpm5_access.h | 9 +- .../eqdma_cpm5_access/eqdma_cpm5_reg.h | 4 +- .../eqdma_cpm5_access/eqdma_cpm5_reg_dump.c | 3 +- .../eqdma_soft_access/eqdma_soft_access.c | 196 ++++---- .../eqdma_soft_access/eqdma_soft_access.h | 9 +- .../eqdma_soft_access/eqdma_soft_reg.h | 4 +- .../eqdma_soft_access/eqdma_soft_reg_dump.c | 3 +- .../net/qdma/qdma_access/qdma_access_common.c | 33 +- .../net/qdma/qdma_access/qdma_access_common.h | 118 +++-- .../net/qdma/qdma_access/qdma_access_errors.h | 2 +- .../net/qdma/qdma_access/qdma_access_export.h | 2 +- .../qdma/qdma_access/qdma_access_version.h | 8 +- .../qdma_cpm4_access/qdma_cpm4_access.c | 142 +++--- .../qdma_cpm4_access/qdma_cpm4_access.h | 8 +- .../qdma_cpm4_access/qdma_cpm4_reg.h | 4 +- .../qdma_cpm4_access/qdma_cpm4_reg_dump.c | 3 +- .../drivers/net/qdma/qdma_access/qdma_list.c | 2 +- .../drivers/net/qdma/qdma_access/qdma_list.h | 2 +- .../net/qdma/qdma_access/qdma_mbox_protocol.c | 41 +- .../net/qdma/qdma_access/qdma_mbox_protocol.h | 2 +- .../net/qdma/qdma_access/qdma_platform.h | 2 +- .../net/qdma/qdma_access/qdma_reg_dump.h | 2 +- .../net/qdma/qdma_access/qdma_resource_mgmt.c | 2 +- .../net/qdma/qdma_access/qdma_resource_mgmt.h | 2 +- .../qdma_soft_access/qdma_soft_access.c | 139 +++--- .../qdma_soft_access/qdma_soft_access.h | 2 +- .../qdma_soft_access/qdma_soft_reg.h | 2 +- QDMA/DPDK/drivers/net/qdma/qdma_common.c | 6 +- QDMA/DPDK/drivers/net/qdma/qdma_devops.c | 26 +- QDMA/DPDK/drivers/net/qdma/qdma_devops.h | 2 +- QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.c | 40 +- QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.h | 36 +- QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c | 16 +- QDMA/DPDK/drivers/net/qdma/qdma_log.h | 2 +- QDMA/DPDK/drivers/net/qdma/qdma_mbox.c | 2 +- QDMA/DPDK/drivers/net/qdma/qdma_mbox.h | 2 +- QDMA/DPDK/drivers/net/qdma/qdma_platform.c | 2 +- .../DPDK/drivers/net/qdma/qdma_platform_env.h | 2 +- QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c | 2 +- QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h | 2 +- .../DPDK/drivers/net/qdma/qdma_rxtx_vec_sse.c | 2 +- QDMA/DPDK/drivers/net/qdma/qdma_user.c | 2 +- QDMA/DPDK/drivers/net/qdma/qdma_user.h | 2 +- QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c | 16 +- QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c | 14 +- QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c | 26 +- QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h | 2 +- QDMA/DPDK/drivers/net/qdma/version.h | 8 +- QDMA/DPDK/drivers/net/qdma/version.map | 139 +----- ...MA-xdebug-to-proc-info-of-dpdk-23.11.patch | 428 ++++++++++++++++++ ....1-Patch-to-add-Jumbo-packet-support.patch | 423 +++++++++++++++++ QDMA/DPDK/tools/README.txt | 4 +- 57 files changed, 1614 insertions(+), 598 deletions(-) create mode 100644 QDMA/DPDK/tools/0001-Add-QDMA-xdebug-to-proc-info-of-dpdk-23.11.patch create mode 100644 QDMA/DPDK/tools/0001-PKTGEN-24.03.1-Patch-to-add-Jumbo-packet-support.patch diff --git a/QDMA/DPDK/RELEASE b/QDMA/DPDK/RELEASE index 806779b5..da831e28 100755 --- a/QDMA/DPDK/RELEASE +++ b/QDMA/DPDK/RELEASE @@ -1,3 +1,22 @@ +RELEASE: 2024.1 +================= + +This release is based on DPDK v20.11, v21.11, v22.11 and v23.11 and +contains QDMA poll mode driver and QDMA test application. + +This release is validated for + - On VCU118 for QDMA5.0 2022.1 example design + - On XCVP1202 for CPM5 2022.1 example design + - On XCVC1902 for CPM4 2022.1 example design + +This release includes patch files for dpdk-pktgen v20.12.0, v22.04.1 and v24.03.1 that extends +dpdk-pktgen application to handle packets with packet sizes more than 1518 bytes +and it disables the packet size classification logic in dpdk-pktgen to remove +application overhead in performance measurement.This patch is used for +performance testing with dpdk-pktgen application. + +The driver is validated against dpdk-pktgen and testpmd applications for API compliance. + RELEASE: 2023.2.1 ================= @@ -136,6 +155,10 @@ CPM5 ---------------- - Added support for latency measurements in Tx and Rx data path for VF +2024.1 Updates +-------------- +- Migrated QDMA dpdk driver to Support DPDK framework v23.11 + KNOWN ISSUE: ============ - CPM4: @@ -165,7 +188,7 @@ DRIVER LIMITATIONS: * BSD LICENSE * * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/docs/README.txt b/QDMA/DPDK/docs/README.txt index a4ff05ee..9eb6de45 100755 --- a/QDMA/DPDK/docs/README.txt +++ b/QDMA/DPDK/docs/README.txt @@ -15,40 +15,39 @@ Contents _____________________________________________________________________________ -Note: This DPDK driver and applciation were tested on Ubuntu 18.04 machine. +Note: This DPDK driver and applciation were tested on Ubuntu 22.04.1 machine. 1.) Setup: Download and modifications -The reference driver code requires DPDK version 22.11. +The reference driver code requires DPDK version 23.11. Follow the steps below to download the proper version of DPDK and apply driver code and test application supplied in the GitHub. -Extract the DPDK driver software database from the Xilinx GitHub to the server where VCU1525 +Extract the DPDK driver software database from the Xilinx GitHub to the server where VCU118 is installed. Henceforth, this area is referred as . -Create a directory for the DPDK download on the server where the VCU1525 +Create a directory for the DPDK download on the server where the VCU118 is installed and move to this directory. $ mkdir / $ cd / $ git clone http://dpdk.org/git/dpdk-stable $ cd dpdk-stable - $ git checkout v22.11 + $ git checkout v23.11 $ git clone git://dpdk.org/dpdk-kmods $ cp -r /drivers/net/qdma ./drivers/net/ $ cp -r /examples/qdma_testapp ./examples/ - Additionally, make below changes to the DPDK 22.11 tree to build QDMA driver, + Additionally, make below changes to the DPDK 23.11 tree to build QDMA driver, support 4K queues and populate Xilinx devices for binding. i. Add QDMA driver a. To support 4K queues and 256 PCIe functions, update below configurations in ./config/rte_config.h - CONFIG_RTE_MAX_MEMZONE=40960 CONFIG_RTE_MAX_ETHPORTS=256 CONFIG_RTE_MAX_QUEUES_PER_PORT=4096 - b. Add below lines to ./config/meson.build in DPDK 22.11 tree + b. Add below lines to ./config/meson.build in DPDK 23.11 tree # Set maximum Ethernet ports to 256 dpdk_conf.set('RTE_MAX_ETHPORTS', 256) @@ -100,7 +99,7 @@ The following modifications must be made to the /boot/grub/grub.cfg on the host ninja ninja install ldconfig - + - The following should appear when ninja completes Linking target app/test/dpdk-test. @@ -526,7 +525,7 @@ Two ports: * BSD LICENSE * * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/meson.build b/QDMA/DPDK/drivers/net/qdma/meson.build index 0a04d4d9..1fade598 100755 --- a/QDMA/DPDK/drivers/net/qdma/meson.build +++ b/QDMA/DPDK/drivers/net/qdma/meson.build @@ -1,7 +1,7 @@ # BSD LICENSE # # Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved. -# Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. +# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions @@ -33,10 +33,11 @@ cflags += ['-DRTE_LIBRTE_QDMA_PMD'] cflags += ['-DDMA_BRAM_SIZE=524288'] cflags += ['-DTHROUGHPUT_MEASUREMENT'] +# Use QDMA_DPDK_23_11 compiler flag for DPDK v23.11 # Use QDMA_DPDK_22_11 compiler flag for DPDK v22.11 # Use QDMA_DPDK_21_11 compiler flag for DPDK v21.11 # Use QDMA_DPDK_20_11 compiler flag for DPDK v20.11 -cflags += ['-DQDMA_DPDK_22_11'] +cflags += ['-DQDMA_DPDK_23_11'] includes += include_directories('.') includes += include_directories('qdma_access') @@ -76,4 +77,4 @@ sources = files( if arch_subdir == 'x86' sources += files('qdma_rxtx_vec_sse.c') -endif \ No newline at end of file +endif diff --git a/QDMA/DPDK/drivers/net/qdma/qdma.h b/QDMA/DPDK/drivers/net/qdma/qdma.h index b6990696..66cc2bd6 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma.h @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c index 11f9cca1..ea4a70d0 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -2264,35 +2264,56 @@ static void eqdma_cpm5_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt { int i = 0; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_stat_desc; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_int; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->trig_mode; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->fnc_id; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->counter_idx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_idx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->in_st; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->color; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ringsz_idx; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.en_stat_desc; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.en_int; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.trig_mode; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.fnc_id; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.counter_idx; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.timer_idx; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.in_st; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.color; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.ringsz_idx; eqdma_cpm5_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_L_MASK, cmpt_ctxt->bs_addr); eqdma_cpm5_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( EQDMA_CPM5_COMPL_CTXT_BADDR_HIGH_H_MASK, cmpt_ctxt->bs_addr); - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->desc_sz; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.desc_sz; eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->pidx; eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->cidx; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->valid; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->err; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->user_trig_pend; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_running; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->full_upd; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ovf_chk_dis; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->at; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->vec; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->int_aggr; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dis_intr_on_vf; - eqdma_cpm5_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dir_c2h; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.valid; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.err; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.user_trig_pend; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.timer_running; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.full_upd; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.ovf_chk_dis; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.at; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.vec; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.int_aggr; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.dis_intr_on_vf; + eqdma_cpm5_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.dir_c2h; eqdma_cpm5_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( EQDMA_CPM5_COMPL_CTXT_BADDR_LOW_MASK, cmpt_ctxt->bs_addr); @@ -3711,10 +3732,11 @@ static int eqdma_cpm5_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, return -QDMA_ERR_INV_PARAM; } - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { + if (ctxt->lower_dword.bit.trig_mode > + QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", __func__, - ctxt->trig_mode, + ctxt->lower_dword.bit.trig_mode, QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, -QDMA_ERR_INV_PARAM); return -QDMA_ERR_INV_PARAM; @@ -3742,47 +3764,63 @@ static int eqdma_cpm5_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | + ctxt->lower_dword.bit.en_stat_desc) | + FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, + ctxt->lower_dword.bit.en_int) | + FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, + ctxt->lower_dword.bit.trig_mode) | + FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, + ctxt->lower_dword.bit.fnc_id) | FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - ctxt->counter_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, ctxt->timer_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, ctxt->ringsz_idx); + ctxt->lower_dword.bit.counter_idx) | + FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, + ctxt->lower_dword.bit.timer_idx) | + FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, + ctxt->lower_dword.bit.in_st) | + FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, + ctxt->lower_dword.bit.color) | + FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, + ctxt->lower_dword.bit.ringsz_idx); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, baddr4_high_l); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, baddr4_high_h) | - FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, ctxt->desc_sz) | + FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, + ctxt->higher_dword.bit.desc_sz) | FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, pidx_l); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, pidx_h) | FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | + FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, + ctxt->higher_dword.bit.valid) | + FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, + ctxt->higher_dword.bit.err) | FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend); + ctxt->higher_dword.bit.user_trig_pend); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, - ctxt->timer_running) | - FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, ctxt->full_upd) | + ctxt->higher_dword.bit.timer_running) | + FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, + ctxt->higher_dword.bit.full_upd) | FIELD_SET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, ctxt->at) | - FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->int_aggr) | + ctxt->higher_dword.bit.ovf_chk_dis) | + FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, + ctxt->higher_dword.bit.at) | + FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, + ctxt->higher_dword.bit.vec) | + FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, + ctxt->higher_dword.bit.int_aggr) | FIELD_SET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | + ctxt->higher_dword.bit.dis_intr_on_vf) | FIELD_SET(CMPL_CTXT_DATA_W4_VIO_MASK, ctxt->vio) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, ctxt->dir_c2h) | - FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | + FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, + ctxt->higher_dword.bit.dir_c2h) | + FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, + ctxt->higher_dword.bit.host_id) | FIELD_SET(CMPL_CTXT_DATA_W4_PASID_L_MASK, pasid_l); cmpt_ctxt[num_words_count++] = @@ -3828,25 +3866,28 @@ static int eqdma_cpm5_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, if (rv < 0) return rv; - ctxt->en_stat_desc = - FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = + ctxt->lower_dword.bit.en_stat_desc = + FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, + cmpt_ctxt[0]); + ctxt->lower_dword.bit.en_int = + FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); + ctxt->lower_dword.bit.trig_mode = FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, cmpt_ctxt[0]); - ctxt->counter_idx = + ctxt->lower_dword.bit.fnc_id = + FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, cmpt_ctxt[0]); + ctxt->lower_dword.bit.counter_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, cmpt_ctxt[0])); - ctxt->timer_idx = + ctxt->lower_dword.bit.timer_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, cmpt_ctxt[0])); - ctxt->in_st = + ctxt->lower_dword.bit.in_st = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, cmpt_ctxt[0])); - ctxt->color = + ctxt->lower_dword.bit.color = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, cmpt_ctxt[0])); - ctxt->ringsz_idx = + ctxt->lower_dword.bit.ringsz_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, cmpt_ctxt[0])); @@ -3855,7 +3896,7 @@ static int eqdma_cpm5_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, baddr4_high_h = FIELD_GET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, cmpt_ctxt[2]); - ctxt->desc_sz = + ctxt->higher_dword.bit.desc_sz = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, cmpt_ctxt[2])); pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, cmpt_ctxt[2]); @@ -3864,34 +3905,42 @@ static int eqdma_cpm5_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, ctxt->cidx = (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, cmpt_ctxt[3])); - ctxt->valid = + ctxt->higher_dword.bit.valid = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, cmpt_ctxt[3])); - ctxt->err = + ctxt->higher_dword.bit.err = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) + ctxt->higher_dword.bit.user_trig_pend = (uint8_t) (FIELD_GET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, cmpt_ctxt[3])); - ctxt->timer_running = - FIELD_GET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, cmpt_ctxt[4]); - ctxt->full_upd = - FIELD_GET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = - FIELD_GET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) - (FIELD_GET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, cmpt_ctxt[4])); - ctxt->dis_intr_on_vf = (uint8_t) - FIELD_GET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - cmpt_ctxt[4]); + ctxt->higher_dword.bit.timer_running = + FIELD_GET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, + cmpt_ctxt[4]); + ctxt->higher_dword.bit.full_upd = + FIELD_GET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, + cmpt_ctxt[4]); + ctxt->higher_dword.bit.ovf_chk_dis = + FIELD_GET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, + cmpt_ctxt[4]); + ctxt->higher_dword.bit.at = + FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); + ctxt->higher_dword.bit.vec = + FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); + ctxt->higher_dword.bit.int_aggr = (uint8_t) + (FIELD_GET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, + cmpt_ctxt[4])); + ctxt->higher_dword.bit.dis_intr_on_vf = (uint8_t) + FIELD_GET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, + cmpt_ctxt[4]); ctxt->vio = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_VIO_MASK, cmpt_ctxt[4]); - ctxt->dir_c2h = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, + ctxt->higher_dword.bit.dir_c2h = + (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, cmpt_ctxt[4]); - ctxt->host_id = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, + ctxt->higher_dword.bit.host_id = + (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, cmpt_ctxt[4]); pasid_l = FIELD_GET(CMPL_CTXT_DATA_W4_PASID_L_MASK, cmpt_ctxt[4]); @@ -5247,7 +5296,7 @@ static void eqdma_cpm5_hw_err_dump_ctxt_info(void *dev_hndl, eqdma_cpm5_cmpt_ctxt_entries[13].value, eqdma_cpm5_cmpt_ctxt_entries[13].value); - if (cmpt_ctxt.err != 0) { + if (cmpt_ctxt.higher_dword.bit.err != 0) { /*** CMPT Context: ERR ***/ qdma_log_info("%-47s %#-10x %u\n", eqdma_cpm5_cmpt_ctxt_entries[15].name, @@ -6775,7 +6824,7 @@ int eqdma_cpm5_dump_reg_info(void *dev_hndl, uint32_t reg_addr, if (buf) { rv = QDMA_SNPRINTF_S(buf, buflen, DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", + "\n%-40s 0x%-7x %-#10x %u\n", config_regs[j].name, config_regs[j].addr, reg_val, reg_val); @@ -6789,7 +6838,7 @@ int eqdma_cpm5_dump_reg_info(void *dev_hndl, uint32_t reg_addr, data_len += rv; buflen -= rv; } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", + qdma_log_info("%-40s 0x%-7x %-#10x %u\n", config_regs[j].name, config_regs[j].addr, reg_val, reg_val); @@ -6807,7 +6856,7 @@ int eqdma_cpm5_dump_reg_info(void *dev_hndl, uint32_t reg_addr, bitfield = config_regs[j].bitfields[k].field_mask; bitfield_name = - config_regs[i].bitfields[k].field_name; + config_regs[j].bitfields[k].field_name; lsb = 0; msb = 31; diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h index 8c14e040..f769f25c 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_access.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -40,6 +40,8 @@ extern "C" { #include "qdma_platform.h" +#define DEBGFS_REG_LINE_SZ (74) + /** * enum eqdma_cpm5_error_idx - qdma errors */ @@ -353,6 +355,11 @@ uint32_t eqdma_cpm5_get_config_num_regs(void); struct xreg_info *eqdma_cpm5_get_config_regs(void); +uint32_t eqdma_cpm5_config_num_regs_get(void); + +struct xreg_info *eqdma_cpm5_config_regs_get(void); + +int qdma_reginfo_dump_buf_len(int *n_regs, struct xreg_info *config_regs); #ifdef __cplusplus } #endif diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h index 1099ede2..8ee8540e 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -88,8 +88,6 @@ extern "C" { sizeof(arr[0])) -uint32_t eqdma_cpm5_config_num_regs_get(void); -struct xreg_info *eqdma_cpm5_config_regs_get(void); #define EQDMA_CPM5_CFG_BLK_IDENTIFIER_ADDR 0x00 #define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) #define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c index af9a175c..de27e6b3 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_cpm5_access/eqdma_cpm5_reg_dump.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -32,6 +32,7 @@ */ #include "eqdma_cpm5_reg.h" +#include "eqdma_cpm5_access.h" #include "qdma_reg_dump.h" #ifdef ENABLE_WPP_TRACING diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c index 03324799..0108f7cd 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -2301,35 +2301,56 @@ static void eqdma_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) { int i = 0; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_stat_desc; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->en_int; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->trig_mode; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->fnc_id; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->counter_idx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_idx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->in_st; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->color; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ringsz_idx; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.en_stat_desc; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.en_int; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.trig_mode; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.fnc_id; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.counter_idx; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.timer_idx; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.in_st; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.color; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->lower_dword.bit.ringsz_idx; eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( EQDMA_COMPL_CTXT_BADDR_HIGH_L_MASK, cmpt_ctxt->bs_addr); eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( EQDMA_COMPL_CTXT_BADDR_HIGH_H_MASK, cmpt_ctxt->bs_addr); - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->desc_sz; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.desc_sz; eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->pidx; eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->cidx; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->valid; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->err; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->user_trig_pend; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->timer_running; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->full_upd; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->ovf_chk_dis; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->at; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->vec; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->int_aggr; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dis_intr_on_vf; - eqdma_cmpt_ctxt_entries[i++].value = cmpt_ctxt->dir_c2h; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.valid; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.err; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.user_trig_pend; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.timer_running; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.full_upd; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.ovf_chk_dis; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.at; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.vec; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.int_aggr; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.dis_intr_on_vf; + eqdma_cmpt_ctxt_entries[i++].value = + cmpt_ctxt->higher_dword.bit.dir_c2h; eqdma_cmpt_ctxt_entries[i++].value = (uint32_t)FIELD_GET( EQDMA_COMPL_CTXT_BADDR_LOW_MASK, cmpt_ctxt->bs_addr); @@ -3781,10 +3802,11 @@ static int eqdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, return -QDMA_ERR_INV_PARAM; } - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { + if (ctxt->lower_dword.bit.trig_mode > + QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", __func__, - ctxt->trig_mode, + ctxt->lower_dword.bit.trig_mode, QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, -QDMA_ERR_INV_PARAM); return -QDMA_ERR_INV_PARAM; @@ -3807,47 +3829,64 @@ static int eqdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | + ctxt->lower_dword.bit.en_stat_desc) | + FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, + ctxt->lower_dword.bit.en_int) | + FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, + ctxt->lower_dword.bit.trig_mode) | + FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, + ctxt->lower_dword.bit.fnc_id) | FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, - ctxt->counter_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, ctxt->timer_idx) | - FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, ctxt->ringsz_idx); + ctxt->lower_dword.bit.counter_idx) | + FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, + ctxt->lower_dword.bit.timer_idx) | + FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, + ctxt->lower_dword.bit.in_st) | + FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, + ctxt->lower_dword.bit.color) | + FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, + ctxt->lower_dword.bit.ringsz_idx); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W1_BADDR4_HIGH_L_MASK, baddr4_high_l); cmpt_ctxt[num_words_count++] = - FIELD_SET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, baddr4_high_h) | - FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, ctxt->desc_sz) | + FIELD_SET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, + baddr4_high_h) | + FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, + ctxt->higher_dword.bit.desc_sz) | FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, pidx_l); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, pidx_h) | FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | + FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, + ctxt->higher_dword.bit.valid) | + FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, + ctxt->higher_dword.bit.err) | FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend); + ctxt->higher_dword.bit.user_trig_pend); cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, - ctxt->timer_running) | - FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, ctxt->full_upd) | + ctxt->higher_dword.bit.timer_running) | + FIELD_SET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, + ctxt->higher_dword.bit.full_upd) | FIELD_SET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, ctxt->at) | - FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, ctxt->vec) | - FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, ctxt->int_aggr) | + ctxt->higher_dword.bit.ovf_chk_dis) | + FIELD_SET(CMPL_CTXT_DATA_W4_AT_MASK, + ctxt->higher_dword.bit.at) | + FIELD_SET(CMPL_CTXT_DATA_W4_VEC_MASK, + ctxt->higher_dword.bit.vec) | + FIELD_SET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, + ctxt->higher_dword.bit.int_aggr) | FIELD_SET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, - ctxt->dis_intr_on_vf) | + ctxt->higher_dword.bit.dis_intr_on_vf) | FIELD_SET(CMPL_CTXT_DATA_W4_VIO_MASK, ctxt->vio) | - FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, ctxt->dir_c2h) | - FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, ctxt->host_id) | + FIELD_SET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, + ctxt->higher_dword.bit.dir_c2h) | + FIELD_SET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, + ctxt->higher_dword.bit.host_id) | FIELD_SET(CMPL_CTXT_DATA_W4_PASID_L_MASK, pasid_l); cmpt_ctxt[num_words_count++] = @@ -3893,27 +3932,28 @@ static int eqdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, if (rv < 0) return rv; - ctxt->en_stat_desc = + ctxt->lower_dword.bit.en_stat_desc = FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = + ctxt->lower_dword.bit.en_int = + FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); + ctxt->lower_dword.bit.trig_mode = FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = + ctxt->lower_dword.bit.fnc_id = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, cmpt_ctxt[0])); - ctxt->counter_idx = + ctxt->lower_dword.bit.counter_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_CNTER_IX_MASK, cmpt_ctxt[0])); - ctxt->timer_idx = + ctxt->lower_dword.bit.timer_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IX_MASK, cmpt_ctxt[0])); - ctxt->in_st = + ctxt->lower_dword.bit.in_st = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, cmpt_ctxt[0])); - ctxt->color = + ctxt->lower_dword.bit.color = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, cmpt_ctxt[0])); - ctxt->ringsz_idx = + ctxt->lower_dword.bit.ringsz_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IX_MASK, cmpt_ctxt[0])); @@ -3922,7 +3962,7 @@ static int eqdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, baddr4_high_h = FIELD_GET(CMPL_CTXT_DATA_W2_BADDR4_HIGH_H_MASK, cmpt_ctxt[2]); - ctxt->desc_sz = + ctxt->higher_dword.bit.desc_sz = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, cmpt_ctxt[2])); pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, cmpt_ctxt[2]); @@ -3931,34 +3971,38 @@ static int eqdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, ctxt->cidx = (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, cmpt_ctxt[3])); - ctxt->valid = + ctxt->higher_dword.bit.valid = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, cmpt_ctxt[3])); - ctxt->err = + ctxt->higher_dword.bit.err = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) + ctxt->higher_dword.bit.user_trig_pend = (uint8_t) (FIELD_GET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, cmpt_ctxt[3])); - ctxt->timer_running = + ctxt->higher_dword.bit.timer_running = FIELD_GET(CMPL_CTXT_DATA_W4_TIMER_RUNNING_MASK, cmpt_ctxt[4]); - ctxt->full_upd = + ctxt->higher_dword.bit.full_upd = FIELD_GET(CMPL_CTXT_DATA_W4_FULL_UPD_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = + ctxt->higher_dword.bit.ovf_chk_dis = FIELD_GET(CMPL_CTXT_DATA_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) + ctxt->higher_dword.bit.at = + FIELD_GET(CMPL_CTXT_DATA_W4_AT_MASK, cmpt_ctxt[4]); + ctxt->higher_dword.bit.vec = + FIELD_GET(CMPL_CTXT_DATA_W4_VEC_MASK, cmpt_ctxt[4]); + ctxt->higher_dword.bit.int_aggr = (uint8_t) (FIELD_GET(CMPL_CTXT_DATA_W4_INT_AGGR_MASK, cmpt_ctxt[4])); - ctxt->dis_intr_on_vf = (uint8_t) + ctxt->higher_dword.bit.dis_intr_on_vf = (uint8_t) FIELD_GET(CMPL_CTXT_DATA_W4_DIS_INTR_ON_VF_MASK, cmpt_ctxt[4]); ctxt->vio = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_VIO_MASK, cmpt_ctxt[4]); - ctxt->dir_c2h = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, + ctxt->higher_dword.bit.dir_c2h = (uint8_t) + FIELD_GET(CMPL_CTXT_DATA_W4_DIR_C2H_MASK, cmpt_ctxt[4]); - ctxt->host_id = (uint8_t)FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, + ctxt->higher_dword.bit.host_id = (uint8_t) + FIELD_GET(CMPL_CTXT_DATA_W4_HOST_ID_MASK, cmpt_ctxt[4]); pasid_l = FIELD_GET(CMPL_CTXT_DATA_W4_PASID_L_MASK, cmpt_ctxt[4]); @@ -5127,10 +5171,8 @@ int eqdma_get_user_bar(void *dev_hndl, uint8_t is_vf, } if (bar_found == 0) { *user_bar = 0; - qdma_log_error("%s: Bar not found, err:%d\n", - __func__, - -QDMA_ERR_HWACC_BAR_NOT_FOUND); - return -QDMA_ERR_HWACC_BAR_NOT_FOUND; + qdma_log_info("%s: AXI Master Lite User Bar not found %d\n", + __func__, -QDMA_ERR_HWACC_BAR_NOT_FOUND); } return QDMA_SUCCESS; @@ -5311,7 +5353,7 @@ static void eqdma_hw_err_dump_ctxt_info(void *dev_hndl, eqdma_cmpt_ctxt_entries[13].value, eqdma_cmpt_ctxt_entries[13].value); - if (cmpt_ctxt.err != 0) { + if (cmpt_ctxt.higher_dword.bit.err != 0) { /*** CMPT Context: ERR ***/ qdma_log_info("%-47s %#-10x %u\n", eqdma_cmpt_ctxt_entries[15].name, @@ -6730,7 +6772,7 @@ int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, if (buf) { rv = QDMA_SNPRINTF_S(buf, buflen, DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", + "\n%-40s 0x%-7x %-#10x %u\n", config_regs[j].name, config_regs[j].addr, reg_val, reg_val); @@ -6744,7 +6786,7 @@ int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, data_len += rv; buflen -= rv; } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", + qdma_log_info("%-40s 0x%-7x %-#10x %u\n", config_regs[j].name, config_regs[j].addr, reg_val, reg_val); @@ -6762,7 +6804,7 @@ int eqdma_dump_reg_info(void *dev_hndl, uint32_t reg_addr, bitfield = config_regs[j].bitfields[k].field_mask; bitfield_name = - config_regs[i].bitfields[k].field_name; + config_regs[j].bitfields[k].field_name; lsb = 0; msb = 31; diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h index b2df4fe1..f2832386 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_access.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -40,6 +40,8 @@ extern "C" { #include "qdma_platform.h" +#define DEBGFS_REG_LINE_SZ (74) + /** * enum qdma_error_idx - qdma errors */ @@ -354,6 +356,11 @@ uint32_t eqdma_get_config_num_regs(void); struct xreg_info *eqdma_get_config_regs(void); +uint32_t eqdma_config_num_regs_get(void); + +struct xreg_info *eqdma_config_regs_get(void); + +int qdma_reginfo_dump_buf_len(int *n_regs, struct xreg_info *config_regs); #ifdef __cplusplus } #endif diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h index 4f326ea0..c40d5fe3 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -88,8 +88,6 @@ extern "C" { sizeof(arr[0])) -uint32_t eqdma_config_num_regs_get(void); -struct xreg_info *eqdma_config_regs_get(void); #define EQDMA_CFG_BLK_IDENTIFIER_ADDR 0x00 #define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) #define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c index 41950f9c..ab981d2c 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/eqdma_soft_access/eqdma_soft_reg_dump.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -32,6 +32,7 @@ */ #include "eqdma_soft_reg.h" +#include "eqdma_soft_access.h" #include "qdma_reg_dump.h" #ifdef ENABLE_WPP_TRACING diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c index 84a95261..a39f4f18 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -681,11 +681,24 @@ int qdma_acc_reg_dump_buf_len(void *dev_hndl, enum qdma_ip_type ip_type, return rv; } +int qdma_reginfo_dump_buf_len(int *n_regs, struct xreg_info *config_regs) +{ + int i = 0, bitfield_val = 0; + uint32_t len = 0; + + for (i = 0; i < *n_regs; i++) + bitfield_val += config_regs[i].num_bitfields; + len = (((*n_regs + 1) * DEBGFS_REG_LINE_SZ) + + ((bitfield_val + 1) * DEBGFS_LINE_SZ)); + return len; +} + int qdma_acc_reg_info_len(void *dev_hndl, enum qdma_ip_type ip_type, enum qdma_device_type device_type, int *buflen, int *num_regs) { uint32_t len = 0; int rv = 0; + struct xreg_info *config_regs = NULL; if (!dev_hndl) { qdma_log_error("%s: dev_handle is NULL, err:%d\n", @@ -717,11 +730,13 @@ int qdma_acc_reg_info_len(void *dev_hndl, enum qdma_ip_type ip_type, break; case QDMA_VERSAL_HARD_IP: if (device_type == QDMA_DEVICE_VERSAL_CPM4) { - len = qdma_cpm4_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); + *num_regs = (int)qdma_cpm4_config_num_regs_get(); + config_regs = qdma_cpm4_config_regs_get(); + len = qdma_reginfo_dump_buf_len(num_regs, config_regs); } else if (device_type == QDMA_DEVICE_VERSAL_CPM5) { - len = eqdma_cpm5_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); + *num_regs = (int)eqdma_cpm5_config_num_regs_get(); + config_regs = eqdma_cpm5_config_regs_get(); + len = qdma_reginfo_dump_buf_len(num_regs, config_regs); } else { qdma_log_error("%s: Invalid device type, err = %d", __func__, -QDMA_ERR_INV_PARAM); @@ -729,8 +744,9 @@ int qdma_acc_reg_info_len(void *dev_hndl, enum qdma_ip_type ip_type, } break; case EQDMA_SOFT_IP: - len = eqdma_reg_dump_buf_len(); - *num_regs = (int)((len / REG_DUMP_SIZE_PER_LINE) - 1); + *num_regs = (int)eqdma_config_num_regs_get(); + config_regs = eqdma_config_regs_get(); + len = qdma_reginfo_dump_buf_len(num_regs, config_regs); break; default: qdma_log_error("%s: Invalid version number, err = %d", @@ -1383,9 +1399,6 @@ int qdma_hw_access_init(void *dev_hndl, uint8_t is_vf, qdma_log_info("IP Type: %s\n", qdma_get_ip_type(dev_hndl, is_vf, version_info.ip_type)); - qdma_log_info("Vivado Release: %s\n", - qdma_get_vivado_release_id(version_info.vivado_release)); - if (version_info.ip_type == QDMA_VERSAL_HARD_IP && version_info.device_type == QDMA_DEVICE_VERSAL_CPM4) { hw_access->qdma_init_ctxt_memory = diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h index 24a21897..8c2e05ba 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_common.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -364,63 +364,81 @@ struct qdma_descq_prefetch_ctxt { * struct qdma_descq_cmpt_ctxt - descq completion context config data structure */ struct qdma_descq_cmpt_ctxt { + union __lower_dword__ { + uint32_t reg; + struct { + /** @en_stat_desc - Enable Completion Status writes */ + uint8_t en_stat_desc :1; + /** @en_int - Enable Completion interrupts */ + uint8_t en_int :1; + /** @trig_mode - Interrupt and Completion + * Status Write Trigger Mode + */ + uint8_t trig_mode :3; + /** @fnc_id - Function ID */ + uint8_t fnc_id :8; + /** @counter_idx - Index to counter register */ + uint8_t counter_idx :4; + /** @timer_idx - Index to timer register */ + uint8_t timer_idx :4; + /** @in_st - Interrupt State */ + uint8_t in_st :2; + /** @color - initial color bit to be used on + * Completion + */ + uint8_t color :1; + /** @ringsz_idx - Completion ring size index to + * ring size registers + */ + uint8_t ringsz_idx :4; + } bit; + } lower_dword; /** @bs_addr - completion ring base address */ uint64_t bs_addr; - /** @vec - Interrupt Vector */ - uint16_t vec; /** @pidx_l - producer index low */ uint16_t pidx; /** @cidx - consumer index */ uint16_t cidx; - /** @en_stat_desc - Enable Completion Status writes */ - uint8_t en_stat_desc; - /** @en_int - Enable Completion interrupts */ - uint8_t en_int; - /** @trig_mode - Interrupt and Completion Status Write Trigger Mode */ - uint8_t trig_mode; - /** @fnc_id - Function ID */ - uint8_t fnc_id; - /** @counter_idx - Index to counter register */ - uint8_t counter_idx; - /** @timer_idx - Index to timer register */ - uint8_t timer_idx; - /** @in_st - Interrupt State */ - uint8_t in_st; - /** @color - initial color bit to be used on Completion */ - uint8_t color; - /** @ringsz_idx - Completion ring size index to ring size registers */ - uint8_t ringsz_idx; - /** @desc_sz -descriptor size */ - uint8_t desc_sz; - /** @valid - context valid */ - uint8_t valid; - /** @err - error status */ - uint8_t err; - /** - * @user_trig_pend - user logic initiated interrupt is - * pending to be generate - */ - uint8_t user_trig_pend; - /** @timer_running - timer is running on this queue */ - uint8_t timer_running; - /** @full_upd - Full update */ - uint8_t full_upd; - /** @ovf_chk_dis - Completion Ring Overflow Check Disable */ - uint8_t ovf_chk_dis; - /** @at -Address Translation */ - uint8_t at; - /** @int_aggr -Interrupt Aggregation */ - uint8_t int_aggr; - /** @dis_intr_on_vf - Disbale interrupt with VF */ - uint8_t dis_intr_on_vf; - /** @vio - queue is in VirtIO mode */ - uint8_t vio; - /** @dir_c2h - DMA direction is C2H */ - uint8_t dir_c2h; - /** @host_id - Host ID */ - uint8_t host_id; + union __higher_dword__ { + uint32_t reg; + struct { + /** @desc_sz -descriptor size */ + uint8_t desc_sz :2; + /** @valid - context valid */ + uint8_t valid :1; + /** @err - error status */ + uint8_t err :2; + /** + * @user_trig_pend - user logic initiated interrupt is + * pending to be generate + */ + uint8_t user_trig_pend :1; + /** @timer_running - timer is running on this queue */ + uint8_t timer_running :1; + /** @full_upd - Full update */ + uint8_t full_upd :1; + /** @ovf_chk_dis - Completion Ring Overflow + * Check Disable + */ + uint8_t ovf_chk_dis :1; + /** @at -Address Translation */ + uint8_t at : 1; + /** @vec - Interrupt Vector */ + uint16_t vec: 11; + /** @int_aggr -Interrupt Aggregation */ + uint8_t int_aggr :1; + /** @dis_intr_on_vf - Disbale interrupt with VF */ + uint8_t dis_intr_on_vf :1; + /** @dir_c2h - DMA direction is C2H */ + uint8_t dir_c2h :1; + /** @host_id - Host ID */ + uint8_t host_id :3; + } bit; + } higher_dword; /** @pasid - PASID */ uint32_t pasid; + /** @vio - queue is in VirtIO mode */ + uint8_t vio; /** @pasid_en - PASID Enable */ uint8_t pasid_en; /** @vio_eop - Virtio End-of-packet */ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h index 8eb2c582..7666c88e 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_errors.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h index dba81858..5fc66a3a 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_export.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h index 652a5550..9878c5d5 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_access_version.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -35,9 +35,9 @@ #define __QDMA_ACCESS_VERSION_H_ -#define QDMA_VERSION_MAJOR 2023 -#define QDMA_VERSION_MINOR 2 -#define QDMA_VERSION_PATCH 1 +#define QDMA_VERSION_MAJOR 2024 +#define QDMA_VERSION_MINOR 1 +#define QDMA_VERSION_PATCH 0 #define QDMA_VERSION_STR \ __stringify(QDMA_VERSION_MAJOR) "." \ diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c index b70e924e..c1fa6665 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -1314,27 +1314,42 @@ static void qdma_cpm4_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) */ static void qdma_cpm4_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) { - qdma_cpm4_cmpt_ctxt_entries[0].value = cmpt_ctxt->en_stat_desc; - qdma_cpm4_cmpt_ctxt_entries[1].value = cmpt_ctxt->en_int; - qdma_cpm4_cmpt_ctxt_entries[2].value = cmpt_ctxt->trig_mode; - qdma_cpm4_cmpt_ctxt_entries[3].value = cmpt_ctxt->fnc_id; - qdma_cpm4_cmpt_ctxt_entries[4].value = cmpt_ctxt->counter_idx; - qdma_cpm4_cmpt_ctxt_entries[5].value = cmpt_ctxt->timer_idx; - qdma_cpm4_cmpt_ctxt_entries[6].value = cmpt_ctxt->in_st; - qdma_cpm4_cmpt_ctxt_entries[7].value = cmpt_ctxt->color; - qdma_cpm4_cmpt_ctxt_entries[8].value = cmpt_ctxt->ringsz_idx; + qdma_cpm4_cmpt_ctxt_entries[0].value = + cmpt_ctxt->lower_dword.bit.en_stat_desc; + qdma_cpm4_cmpt_ctxt_entries[1].value = + cmpt_ctxt->lower_dword.bit.en_int; + qdma_cpm4_cmpt_ctxt_entries[2].value = + cmpt_ctxt->lower_dword.bit.trig_mode; + qdma_cpm4_cmpt_ctxt_entries[3].value = + cmpt_ctxt->lower_dword.bit.fnc_id; + qdma_cpm4_cmpt_ctxt_entries[4].value = + cmpt_ctxt->lower_dword.bit.counter_idx; + qdma_cpm4_cmpt_ctxt_entries[5].value = + cmpt_ctxt->lower_dword.bit.timer_idx; + qdma_cpm4_cmpt_ctxt_entries[6].value = + cmpt_ctxt->lower_dword.bit.in_st; + qdma_cpm4_cmpt_ctxt_entries[7].value = + cmpt_ctxt->lower_dword.bit.color; + qdma_cpm4_cmpt_ctxt_entries[8].value = + cmpt_ctxt->lower_dword.bit.ringsz_idx; qdma_cpm4_cmpt_ctxt_entries[9].value = cmpt_ctxt->bs_addr & 0xFFFFFFFF; qdma_cpm4_cmpt_ctxt_entries[10].value = (cmpt_ctxt->bs_addr >> 32) & 0xFFFFFFFF; - qdma_cpm4_cmpt_ctxt_entries[11].value = cmpt_ctxt->desc_sz; + qdma_cpm4_cmpt_ctxt_entries[11].value = + cmpt_ctxt->higher_dword.bit.desc_sz; qdma_cpm4_cmpt_ctxt_entries[12].value = cmpt_ctxt->pidx; qdma_cpm4_cmpt_ctxt_entries[13].value = cmpt_ctxt->cidx; - qdma_cpm4_cmpt_ctxt_entries[14].value = cmpt_ctxt->valid; - qdma_cpm4_cmpt_ctxt_entries[15].value = cmpt_ctxt->err; - qdma_cpm4_cmpt_ctxt_entries[16].value = cmpt_ctxt->user_trig_pend; - qdma_cpm4_cmpt_ctxt_entries[17].value = cmpt_ctxt->timer_running; - qdma_cpm4_cmpt_ctxt_entries[18].value = cmpt_ctxt->full_upd; + qdma_cpm4_cmpt_ctxt_entries[14].value = + cmpt_ctxt->higher_dword.bit.valid; + qdma_cpm4_cmpt_ctxt_entries[15].value = + cmpt_ctxt->higher_dword.bit.err; + qdma_cpm4_cmpt_ctxt_entries[16].value = + cmpt_ctxt->higher_dword.bit.user_trig_pend; + qdma_cpm4_cmpt_ctxt_entries[17].value = + cmpt_ctxt->higher_dword.bit.timer_running; + qdma_cpm4_cmpt_ctxt_entries[18].value = + cmpt_ctxt->higher_dword.bit.full_upd; } @@ -3033,19 +3048,23 @@ static int qdma_cpm4_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, return -QDMA_ERR_INV_PARAM; } - if ((ctxt->desc_sz > QDMA_DESC_SIZE_32B) || - (ctxt->ringsz_idx >= QDMA_NUM_RING_SIZES) || - (ctxt->counter_idx >= QDMA_NUM_C2H_COUNTERS) || - (ctxt->timer_idx >= QDMA_NUM_C2H_TIMERS) || - (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR)) { + if ((ctxt->higher_dword.bit.desc_sz > QDMA_DESC_SIZE_32B) || + (FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK, + ctxt->lower_dword.bit.ringsz_idx) >= QDMA_NUM_RING_SIZES) || + (FIELD_GET(CMPL_CTXT_DATA_W0_CNTER_IDX_MASK, + ctxt->lower_dword.bit.counter_idx) >= QDMA_NUM_C2H_COUNTERS) || + (FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK, + ctxt->lower_dword.bit.timer_idx) >= QDMA_NUM_C2H_TIMERS) || + (ctxt->lower_dword.bit.trig_mode > + QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR)) { qdma_log_error ("%s Inv dsz(%d)/ridx(%d)/cntr(%d)/tmr(%d)/tm(%d), err:%d\n", __func__, - ctxt->desc_sz, - ctxt->ringsz_idx, - ctxt->counter_idx, - ctxt->timer_idx, - ctxt->trig_mode, + ctxt->higher_dword.bit.desc_sz, + ctxt->lower_dword.bit.ringsz_idx, + ctxt->lower_dword.bit.counter_idx, + ctxt->lower_dword.bit.timer_idx, + ctxt->lower_dword.bit.trig_mode, -QDMA_ERR_INV_PARAM); return -QDMA_ERR_INV_PARAM; } @@ -3067,20 +3086,23 @@ static int qdma_cpm4_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, cmpt_ctxt[num_words_count++] = FIELD_SET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, ctxt->fnc_id) | + ctxt->lower_dword.bit.en_stat_desc) | + FIELD_SET(CMPL_CTXT_DATA_W0_EN_INT_MASK, + ctxt->lower_dword.bit.en_int) | + FIELD_SET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, + ctxt->lower_dword.bit.trig_mode) | + FIELD_SET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, + ctxt->lower_dword.bit.fnc_id) | FIELD_SET(CMPL_CTXT_DATA_W0_CNTER_IDX_MASK, - ctxt->counter_idx) | + ctxt->lower_dword.bit.counter_idx) | FIELD_SET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK, - ctxt->timer_idx) | + ctxt->lower_dword.bit.timer_idx) | FIELD_SET(CMPL_CTXT_DATA_W0_INT_ST_MASK, - ctxt->in_st) | + ctxt->lower_dword.bit.in_st) | FIELD_SET(CMPL_CTXT_DATA_W0_COLOR_MASK, - ctxt->color) | + ctxt->lower_dword.bit.color) | FIELD_SET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK, - ctxt->ringsz_idx) | + ctxt->lower_dword.bit.ringsz_idx) | FIELD_SET(CMPL_CTXT_DATA_W0_BADDR_64_L_MASK, baddr_l); @@ -3092,7 +3114,7 @@ static int qdma_cpm4_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, FIELD_SET(CMPL_CTXT_DATA_W2_BADDR_64_H_MASK, baddr_h) | FIELD_SET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, - ctxt->desc_sz) | + ctxt->higher_dword.bit.desc_sz) | FIELD_SET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, pidx_l); @@ -3100,14 +3122,16 @@ static int qdma_cpm4_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, FIELD_SET(CMPL_CTXT_DATA_W3_PIDX_H_MASK, pidx_h) | FIELD_SET(CMPL_CTXT_DATA_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, ctxt->err) | + FIELD_SET(CMPL_CTXT_DATA_W3_VALID_MASK, + ctxt->higher_dword.bit.valid) | + FIELD_SET(CMPL_CTXT_DATA_W3_ERR_MASK, + ctxt->higher_dword.bit.err) | FIELD_SET(CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, - ctxt->user_trig_pend) | + ctxt->higher_dword.bit.user_trig_pend) | FIELD_SET(CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK, - ctxt->timer_running) | + ctxt->higher_dword.bit.timer_running) | FIELD_SET(CMPL_CTXT_DATA_W3_FULL_UPD_MASK, - ctxt->full_upd); + ctxt->higher_dword.bit.full_upd); return qdma_cpm4_indirect_reg_write(dev_hndl, sel, hw_qid, cmpt_ctxt, num_words_count); @@ -3145,29 +3169,29 @@ static int qdma_cpm4_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, if (rv < 0) return rv; - ctxt->en_stat_desc = + ctxt->lower_dword.bit.en_stat_desc = FIELD_GET(CMPL_CTXT_DATA_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, + ctxt->lower_dword.bit.en_int = FIELD_GET(CMPL_CTXT_DATA_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = + ctxt->lower_dword.bit.trig_mode = FIELD_GET(CMPL_CTXT_DATA_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = + ctxt->lower_dword.bit.fnc_id = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_FNC_ID_MASK, cmpt_ctxt[0])); - ctxt->counter_idx = + ctxt->lower_dword.bit.counter_idx = (uint8_t)(FIELD_GET( CMPL_CTXT_DATA_W0_CNTER_IDX_MASK, cmpt_ctxt[0])); - ctxt->timer_idx = + ctxt->lower_dword.bit.timer_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_TIMER_IDX_MASK, cmpt_ctxt[0])); - ctxt->in_st = + ctxt->lower_dword.bit.in_st = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_INT_ST_MASK, cmpt_ctxt[0])); - ctxt->color = + ctxt->lower_dword.bit.color = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_COLOR_MASK, cmpt_ctxt[0])); - ctxt->ringsz_idx = + ctxt->lower_dword.bit.ringsz_idx = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W0_QSIZE_IDX_MASK, cmpt_ctxt[0])); @@ -3181,7 +3205,7 @@ static int qdma_cpm4_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, FIELD_GET(CMPL_CTXT_DATA_W2_BADDR_64_H_MASK, cmpt_ctxt[2]); - ctxt->desc_sz = + ctxt->higher_dword.bit.desc_sz = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W2_DESC_SIZE_MASK, cmpt_ctxt[2])); pidx_l = FIELD_GET(CMPL_CTXT_DATA_W2_PIDX_L_MASK, @@ -3192,20 +3216,20 @@ static int qdma_cpm4_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, ctxt->cidx = (uint16_t)(FIELD_GET(CMPL_CTXT_DATA_W3_CIDX_MASK, cmpt_ctxt[3])); - ctxt->valid = + ctxt->higher_dword.bit.valid = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_VALID_MASK, cmpt_ctxt[3])); - ctxt->err = + ctxt->higher_dword.bit.err = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_ERR_MASK, cmpt_ctxt[3])); - ctxt->user_trig_pend = + ctxt->higher_dword.bit.user_trig_pend = (uint8_t)(FIELD_GET( CMPL_CTXT_DATA_W3_USER_TRIG_PEND_MASK, cmpt_ctxt[3])); - ctxt->timer_running = + ctxt->higher_dword.bit.timer_running = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_TIMER_RUNNING_MASK, cmpt_ctxt[3])); - ctxt->full_upd = + ctxt->higher_dword.bit.full_upd = (uint8_t)(FIELD_GET(CMPL_CTXT_DATA_W3_FULL_UPD_MASK, cmpt_ctxt[3])); @@ -5973,7 +5997,7 @@ int qdma_cpm4_dump_reg_info(void *dev_hndl, uint32_t reg_addr, if (buf) { rv = QDMA_SNPRINTF_S(buf, buflen, DEBGFS_LINE_SZ, - "\n%-40s 0x%-7x %-#10x %-10d\n", + "\n%-40s 0x%-7x %-#10x %u\n", config_regs[j].name, config_regs[j].addr, reg_val, reg_val); @@ -5987,7 +6011,7 @@ int qdma_cpm4_dump_reg_info(void *dev_hndl, uint32_t reg_addr, data_len += rv; buflen -= rv; } else - qdma_log_info("%-40s 0x%-7x %-#10x %-10d\n", + qdma_log_info("%-40s 0x%-7x %-#10x %u\n", config_regs[j].name, config_regs[j].addr, reg_val, reg_val); @@ -5999,7 +6023,7 @@ int qdma_cpm4_dump_reg_info(void *dev_hndl, uint32_t reg_addr, bitfield = config_regs[j].bitfields[k].field_mask; bitfield_name = - config_regs[i].bitfields[k].field_name; + config_regs[j].bitfields[k].field_name; lsb = 0; msb = 31; diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h index a28f6336..9428f3a6 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_access.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -40,6 +40,8 @@ extern "C" { #include "qdma_platform.h" +#define DEBGFS_REG_LINE_SZ (74) + /** * enum qdma_error_idx - qdma errors */ @@ -293,6 +295,10 @@ uint32_t qdma_cpm4_get_config_num_regs(void); struct xreg_info *qdma_cpm4_get_config_regs(void); +uint32_t qdma_cpm4_config_num_regs_get(void); +struct xreg_info *qdma_cpm4_config_regs_get(void); + +int qdma_reginfo_dump_buf_len(int *n_regs, struct xreg_info *config_regs); #ifdef __cplusplus } #endif diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h index 00bba141..f396a277 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -88,8 +88,6 @@ extern "C" { sizeof(arr[0])) -uint32_t qdma_cpm4_config_num_regs_get(void); -struct xreg_info *qdma_cpm4_config_regs_get(void); #define QDMA_CPM4_CFG_BLK_IDENTIFIER_ADDR 0x00 #define CFG_BLK_IDENTIFIER_MASK GENMASK(31, 20) #define CFG_BLK_IDENTIFIER_1_MASK GENMASK(19, 16) diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c index 2955d7a9..d1a9855f 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_cpm4_access/qdma_cpm4_reg_dump.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -32,6 +32,7 @@ */ #include "qdma_cpm4_reg.h" +#include "qdma_cpm4_access.h" #include "qdma_reg_dump.h" #ifdef ENABLE_WPP_TRACING diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c index 6cea8aa3..ec3467a8 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h index f4224a4e..d2c9ac1b 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_list.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c index 3dbae0d8..0a8d30a7 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -548,7 +548,7 @@ static int mbox_compose_sw_context(void *dev_hndl, sw_ctxt->bypass = qctxt->descq_conf.en_bypass; sw_ctxt->wbk_en = qctxt->descq_conf.wbk_en; sw_ctxt->irq_en = qctxt->descq_conf.irq_en; - sw_ctxt->is_mm = ~qctxt->st; + sw_ctxt->is_mm = ((qctxt->st) ? 0 : 1); sw_ctxt->mm_chn = 0; sw_ctxt->qen = 1; sw_ctxt->frcd_en = qctxt->descq_conf.forced_en; @@ -626,22 +626,27 @@ static int mbox_compose_cmpt_context(void *dev_hndl, /* writeback context */ cmpt_ctxt->bs_addr = qctxt->descq_conf.cmpt_ring_bs_addr; - cmpt_ctxt->en_stat_desc = qctxt->descq_conf.cmpl_stat_en; - cmpt_ctxt->en_int = qctxt->descq_conf.cmpt_int_en; - cmpt_ctxt->trig_mode = qctxt->descq_conf.triggermode; - cmpt_ctxt->fnc_id = qctxt->descq_conf.func_id; - cmpt_ctxt->timer_idx = tmr_idx; - cmpt_ctxt->counter_idx = cntr_idx; - cmpt_ctxt->color = 1; - cmpt_ctxt->ringsz_idx = rng_idx; - - cmpt_ctxt->desc_sz = qctxt->descq_conf.cmpt_desc_sz; - - cmpt_ctxt->valid = 1; - - cmpt_ctxt->ovf_chk_dis = qctxt->descq_conf.dis_overflow_check; - cmpt_ctxt->vec = qctxt->descq_conf.intr_id; - cmpt_ctxt->int_aggr = qctxt->descq_conf.intr_aggr; + cmpt_ctxt->lower_dword.bit.en_stat_desc = + qctxt->descq_conf.cmpl_stat_en; + cmpt_ctxt->lower_dword.bit.en_int = qctxt->descq_conf.cmpt_int_en; + cmpt_ctxt->lower_dword.bit.trig_mode = qctxt->descq_conf.triggermode; + cmpt_ctxt->lower_dword.bit.fnc_id = qctxt->descq_conf.func_id; + cmpt_ctxt->lower_dword.bit.timer_idx = tmr_idx; + cmpt_ctxt->lower_dword.bit.counter_idx = cntr_idx; + cmpt_ctxt->lower_dword.bit.color = 1; + cmpt_ctxt->lower_dword.bit.ringsz_idx = rng_idx; + + cmpt_ctxt->higher_dword.bit.desc_sz = qctxt->descq_conf.cmpt_desc_sz; + + cmpt_ctxt->higher_dword.bit.valid = 1; + + if ((qctxt->st) && (qctxt->c2h)) + cmpt_ctxt->higher_dword.bit.dir_c2h = 1; + + cmpt_ctxt->higher_dword.bit.ovf_chk_dis = + qctxt->descq_conf.dis_overflow_check; + cmpt_ctxt->higher_dword.bit.vec = qctxt->descq_conf.intr_id; + cmpt_ctxt->higher_dword.bit.int_aggr = qctxt->descq_conf.intr_aggr; return QDMA_SUCCESS; } diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h index 243ee757..a6bfcf6f 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_mbox_protocol.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h index f44bd59d..704c514a 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_platform.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h index b1a63c02..3a19918d 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_reg_dump.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c index d903859d..8004fc08 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h index 3361f165..ec8728d7 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_resource_mgmt.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c index 2c14a858..462d3a11 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * @@ -1753,30 +1753,31 @@ static void qdma_fill_sw_ctxt(struct qdma_descq_sw_ctxt *sw_ctxt) */ static void qdma_fill_cmpt_ctxt(struct qdma_descq_cmpt_ctxt *cmpt_ctxt) { - cmpt_ctxt_entries[0].value = cmpt_ctxt->en_stat_desc; - cmpt_ctxt_entries[1].value = cmpt_ctxt->en_int; - cmpt_ctxt_entries[2].value = cmpt_ctxt->trig_mode; - cmpt_ctxt_entries[3].value = cmpt_ctxt->fnc_id; - cmpt_ctxt_entries[4].value = cmpt_ctxt->counter_idx; - cmpt_ctxt_entries[5].value = cmpt_ctxt->timer_idx; - cmpt_ctxt_entries[6].value = cmpt_ctxt->in_st; - cmpt_ctxt_entries[7].value = cmpt_ctxt->color; - cmpt_ctxt_entries[8].value = cmpt_ctxt->ringsz_idx; + cmpt_ctxt_entries[0].value = cmpt_ctxt->lower_dword.bit.en_stat_desc; + cmpt_ctxt_entries[1].value = cmpt_ctxt->lower_dword.bit.en_int; + cmpt_ctxt_entries[2].value = cmpt_ctxt->lower_dword.bit.trig_mode; + cmpt_ctxt_entries[3].value = cmpt_ctxt->lower_dword.bit.fnc_id; + cmpt_ctxt_entries[4].value = cmpt_ctxt->lower_dword.bit.counter_idx; + cmpt_ctxt_entries[5].value = cmpt_ctxt->lower_dword.bit.timer_idx; + cmpt_ctxt_entries[6].value = cmpt_ctxt->lower_dword.bit.in_st; + cmpt_ctxt_entries[7].value = cmpt_ctxt->lower_dword.bit.color; + cmpt_ctxt_entries[8].value = cmpt_ctxt->lower_dword.bit.ringsz_idx; cmpt_ctxt_entries[9].value = cmpt_ctxt->bs_addr & 0xFFFFFFFF; cmpt_ctxt_entries[10].value = (cmpt_ctxt->bs_addr >> 32) & 0xFFFFFFFF; - cmpt_ctxt_entries[11].value = cmpt_ctxt->desc_sz; + cmpt_ctxt_entries[11].value = cmpt_ctxt->higher_dword.bit.desc_sz; cmpt_ctxt_entries[12].value = cmpt_ctxt->pidx; cmpt_ctxt_entries[13].value = cmpt_ctxt->cidx; - cmpt_ctxt_entries[14].value = cmpt_ctxt->valid; - cmpt_ctxt_entries[15].value = cmpt_ctxt->err; - cmpt_ctxt_entries[16].value = cmpt_ctxt->user_trig_pend; - cmpt_ctxt_entries[17].value = cmpt_ctxt->timer_running; - cmpt_ctxt_entries[18].value = cmpt_ctxt->full_upd; - cmpt_ctxt_entries[19].value = cmpt_ctxt->ovf_chk_dis; - cmpt_ctxt_entries[20].value = cmpt_ctxt->at; - cmpt_ctxt_entries[21].value = cmpt_ctxt->vec; - cmpt_ctxt_entries[22].value = cmpt_ctxt->int_aggr; + cmpt_ctxt_entries[14].value = cmpt_ctxt->higher_dword.bit.valid; + cmpt_ctxt_entries[15].value = cmpt_ctxt->higher_dword.bit.err; + cmpt_ctxt_entries[16].value = + cmpt_ctxt->higher_dword.bit.user_trig_pend; + cmpt_ctxt_entries[17].value = cmpt_ctxt->higher_dword.bit.timer_running; + cmpt_ctxt_entries[18].value = cmpt_ctxt->higher_dword.bit.full_upd; + cmpt_ctxt_entries[19].value = cmpt_ctxt->higher_dword.bit.ovf_chk_dis; + cmpt_ctxt_entries[20].value = cmpt_ctxt->higher_dword.bit.at; + cmpt_ctxt_entries[21].value = cmpt_ctxt->higher_dword.bit.vec; + cmpt_ctxt_entries[22].value = cmpt_ctxt->higher_dword.bit.int_aggr; } /* @@ -3156,10 +3157,11 @@ static int qdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, return -QDMA_ERR_INV_PARAM; } - if (ctxt->trig_mode > QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { + if (ctxt->lower_dword.bit.trig_mode > + QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR) { qdma_log_error("%s: trig_mode(%d) > (%d) is invalid, err:%d\n", __func__, - ctxt->trig_mode, + ctxt->lower_dword.bit.trig_mode, QDMA_CMPT_UPDATE_TRIG_MODE_TMR_CNTR, -QDMA_ERR_INV_PARAM); return -QDMA_ERR_INV_PARAM; @@ -3174,43 +3176,57 @@ static int qdma_cmpt_context_write(void *dev_hndl, uint16_t hw_qid, cmpt_ctxt[num_words_count++] = FIELD_SET(QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK, - ctxt->en_stat_desc) | - FIELD_SET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, ctxt->en_int) | - FIELD_SET(QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK, ctxt->trig_mode) | - FIELD_SET(QDMA_COMPL_CTXT_W0_FNC_ID_MASK, ctxt->fnc_id) | + ctxt->lower_dword.bit.en_stat_desc) | + FIELD_SET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, + ctxt->lower_dword.bit.en_int) | + FIELD_SET(QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK, + ctxt->lower_dword.bit.trig_mode) | + FIELD_SET(QDMA_COMPL_CTXT_W0_FNC_ID_MASK, + ctxt->lower_dword.bit.fnc_id) | FIELD_SET(QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK, - ctxt->counter_idx) | - FIELD_SET(QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK, ctxt->timer_idx) | - FIELD_SET(QDMA_COMPL_CTXT_W0_INT_ST_MASK, ctxt->in_st) | - FIELD_SET(QDMA_COMPL_CTXT_W0_COLOR_MASK, ctxt->color) | - FIELD_SET(QDMA_COMPL_CTXT_W0_RING_SZ_MASK, ctxt->ringsz_idx); + ctxt->lower_dword.bit.counter_idx) | + FIELD_SET(QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK, + ctxt->lower_dword.bit.timer_idx) | + FIELD_SET(QDMA_COMPL_CTXT_W0_INT_ST_MASK, + ctxt->lower_dword.bit.in_st) | + FIELD_SET(QDMA_COMPL_CTXT_W0_COLOR_MASK, + ctxt->lower_dword.bit.color) | + FIELD_SET(QDMA_COMPL_CTXT_W0_RING_SZ_MASK, + ctxt->lower_dword.bit.ringsz_idx); cmpt_ctxt[num_words_count++] = FIELD_SET(QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK, baddr_l); cmpt_ctxt[num_words_count++] = FIELD_SET(QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK, baddr_h) | - FIELD_SET(QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK, ctxt->desc_sz) | + FIELD_SET(QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK, + ctxt->higher_dword.bit.desc_sz) | FIELD_SET(QDMA_COMPL_CTXT_W2_PIDX_L_MASK, pidx_l); cmpt_ctxt[num_words_count++] = FIELD_SET(QDMA_COMPL_CTXT_W3_PIDX_H_MASK, pidx_h) | FIELD_SET(QDMA_COMPL_CTXT_W3_CIDX_MASK, ctxt->cidx) | - FIELD_SET(QDMA_COMPL_CTXT_W3_VALID_MASK, ctxt->valid) | - FIELD_SET(QDMA_COMPL_CTXT_W3_ERR_MASK, ctxt->err) | + FIELD_SET(QDMA_COMPL_CTXT_W3_VALID_MASK, + ctxt->higher_dword.bit.valid) | + FIELD_SET(QDMA_COMPL_CTXT_W3_ERR_MASK, + ctxt->higher_dword.bit.err) | FIELD_SET(QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK, - ctxt->user_trig_pend); + ctxt->higher_dword.bit.user_trig_pend); cmpt_ctxt[num_words_count++] = FIELD_SET(QDMA_COMPL_CTXT_W4_TMR_RUN_MASK, - ctxt->timer_running) | - FIELD_SET(QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK, ctxt->full_upd) | + ctxt->higher_dword.bit.timer_running) | + FIELD_SET(QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK, + ctxt->higher_dword.bit.full_upd) | FIELD_SET(QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK, - ctxt->ovf_chk_dis) | - FIELD_SET(QDMA_COMPL_CTXT_W4_AT_MASK, ctxt->at) | - FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, ctxt->vec) | - FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK, ctxt->int_aggr); + ctxt->higher_dword.bit.ovf_chk_dis) | + FIELD_SET(QDMA_COMPL_CTXT_W4_AT_MASK, + ctxt->higher_dword.bit.at) | + FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, + ctxt->higher_dword.bit.vec) | + FIELD_SET(QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK, + ctxt->higher_dword.bit.int_aggr); return qdma_indirect_reg_write(dev_hndl, sel, hw_qid, cmpt_ctxt, num_words_count); @@ -3245,34 +3261,35 @@ static int qdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, if (rv < 0) return rv; - ctxt->en_stat_desc = + ctxt->lower_dword.bit.en_stat_desc = FIELD_GET(QDMA_COMPL_CTXT_W0_EN_STAT_DESC_MASK, cmpt_ctxt[0]); - ctxt->en_int = FIELD_GET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, cmpt_ctxt[0]); - ctxt->trig_mode = + ctxt->lower_dword.bit.en_int = + FIELD_GET(QDMA_COMPL_CTXT_W0_EN_INT_MASK, cmpt_ctxt[0]); + ctxt->lower_dword.bit.trig_mode = FIELD_GET(QDMA_COMPL_CTXT_W0_TRIG_MODE_MASK, cmpt_ctxt[0]); - ctxt->fnc_id = + ctxt->lower_dword.bit.fnc_id = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_FNC_ID_MASK, cmpt_ctxt[0])); - ctxt->counter_idx = + ctxt->lower_dword.bit.counter_idx = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_COUNTER_IDX_MASK, cmpt_ctxt[0])); - ctxt->timer_idx = + ctxt->lower_dword.bit.timer_idx = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_TIMER_IDX_MASK, cmpt_ctxt[0])); - ctxt->in_st = + ctxt->lower_dword.bit.in_st = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_INT_ST_MASK, cmpt_ctxt[0])); - ctxt->color = + ctxt->lower_dword.bit.color = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_COLOR_MASK, cmpt_ctxt[0])); - ctxt->ringsz_idx = + ctxt->lower_dword.bit.ringsz_idx = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W0_RING_SZ_MASK, cmpt_ctxt[0])); baddr_l = FIELD_GET(QDMA_COMPL_CTXT_W1_BADDR_64_L_MASK, cmpt_ctxt[1]); baddr_h = FIELD_GET(QDMA_COMPL_CTXT_W2_BADDR_64_H_MASK, cmpt_ctxt[2]); - ctxt->desc_sz = + ctxt->higher_dword.bit.desc_sz = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W2_DESC_SIZE_MASK, cmpt_ctxt[2])); pidx_l = FIELD_GET(QDMA_COMPL_CTXT_W2_PIDX_L_MASK, cmpt_ctxt[2]); @@ -3281,23 +3298,25 @@ static int qdma_cmpt_context_read(void *dev_hndl, uint16_t hw_qid, ctxt->cidx = (uint16_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_CIDX_MASK, cmpt_ctxt[3])); - ctxt->valid = + ctxt->higher_dword.bit.valid = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_VALID_MASK, cmpt_ctxt[3])); - ctxt->err = + ctxt->higher_dword.bit.err = (uint8_t)(FIELD_GET(QDMA_COMPL_CTXT_W3_ERR_MASK, cmpt_ctxt[3])); - ctxt->user_trig_pend = (uint8_t) + ctxt->higher_dword.bit.user_trig_pend = (uint8_t) (FIELD_GET(QDMA_COMPL_CTXT_W3_USR_TRG_PND_MASK, cmpt_ctxt[3])); - ctxt->timer_running = + ctxt->higher_dword.bit.timer_running = FIELD_GET(QDMA_COMPL_CTXT_W4_TMR_RUN_MASK, cmpt_ctxt[4]); - ctxt->full_upd = + ctxt->higher_dword.bit.full_upd = FIELD_GET(QDMA_COMPL_CTXT_W4_FULL_UPDT_MASK, cmpt_ctxt[4]); - ctxt->ovf_chk_dis = + ctxt->higher_dword.bit.ovf_chk_dis = FIELD_GET(QDMA_COMPL_CTXT_W4_OVF_CHK_DIS_MASK, cmpt_ctxt[4]); - ctxt->at = FIELD_GET(QDMA_COMPL_CTXT_W4_AT_MASK, cmpt_ctxt[4]); - ctxt->vec = FIELD_GET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, cmpt_ctxt[4]); - ctxt->int_aggr = (uint8_t) + ctxt->higher_dword.bit.at = + FIELD_GET(QDMA_COMPL_CTXT_W4_AT_MASK, cmpt_ctxt[4]); + ctxt->higher_dword.bit.vec = + FIELD_GET(QDMA_COMPL_CTXT_W4_INTR_VEC_MASK, cmpt_ctxt[4]); + ctxt->higher_dword.bit.int_aggr = (uint8_t) (FIELD_GET(QDMA_COMPL_CTXT_W4_INTR_AGGR_MASK, cmpt_ctxt[4])); ctxt->bs_addr = diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.h index 6640987b..63532ccd 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_access.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h index 53671a6b..b754cc83 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_access/qdma_soft_access/qdma_soft_reg.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * BSD LICENSE * diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_common.c b/QDMA/DPDK/drivers/net/qdma/qdma_common.c index a25127ed..02f689fa 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_common.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_common.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -646,9 +646,7 @@ int qdma_get_hw_version(struct rte_eth_dev *dev) version_info.qdma_rtl_version_str); PMD_DRV_LOG(INFO, "QDMA DEVICE TYPE : %s\n", version_info.qdma_device_type_str); - PMD_DRV_LOG(INFO, "QDMA VIVADO RELEASE ID : %s\n", - version_info.qdma_vivado_release_id_str); - if (version_info.ip_type == QDMA_VERSAL_HARD_IP) { + if (version_info.ip_type == QDMA_VERSAL_HARD_IP) { PMD_DRV_LOG(INFO, "QDMA VERSAL IP TYPE : %s\n", version_info.qdma_ip_type_str); } diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_devops.c b/QDMA/DPDK/drivers/net/qdma/qdma_devops.c index 45c9b4f1..8296c467 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_devops.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_devops.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -1523,20 +1523,22 @@ int qdma_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qid) q_prefetch_ctxt.valid = 1; #ifdef QDMA_LATENCY_OPTIMIZED - q_cmpt_ctxt.full_upd = 1; + q_cmpt_ctxt.higher_dword.bit.full_upd = 1; #endif //QDMA_LATENCY_OPTIMIZED - q_cmpt_ctxt.en_stat_desc = 1; - q_cmpt_ctxt.trig_mode = rxq->triggermode; - q_cmpt_ctxt.fnc_id = rxq->func_id; - q_cmpt_ctxt.counter_idx = rxq->threshidx; - q_cmpt_ctxt.timer_idx = rxq->timeridx; - q_cmpt_ctxt.color = CMPT_DEFAULT_COLOR_BIT; - q_cmpt_ctxt.ringsz_idx = rxq->cmpt_ringszidx; + q_cmpt_ctxt.lower_dword.bit.en_stat_desc = 1; + q_cmpt_ctxt.lower_dword.bit.trig_mode = rxq->triggermode; + q_cmpt_ctxt.lower_dword.bit.fnc_id = rxq->func_id; + q_cmpt_ctxt.lower_dword.bit.counter_idx = rxq->threshidx; + q_cmpt_ctxt.lower_dword.bit.timer_idx = rxq->timeridx; + q_cmpt_ctxt.lower_dword.bit.color = CMPT_DEFAULT_COLOR_BIT; + q_cmpt_ctxt.lower_dword.bit.ringsz_idx = rxq->cmpt_ringszidx; q_cmpt_ctxt.bs_addr = (uint64_t)rxq->rx_cmpt_mz->iova; - q_cmpt_ctxt.desc_sz = cmpt_desc_fmt; - q_cmpt_ctxt.valid = 1; + q_cmpt_ctxt.higher_dword.bit.desc_sz = cmpt_desc_fmt; + q_cmpt_ctxt.higher_dword.bit.valid = 1; + q_cmpt_ctxt.higher_dword.bit.dir_c2h = 1; if (qdma_dev->dev_cap.cmpt_ovf_chk_dis) - q_cmpt_ctxt.ovf_chk_dis = rxq->dis_overflow_check; + q_cmpt_ctxt.higher_dword.bit.ovf_chk_dis = + rxq->dis_overflow_check; q_sw_ctxt.desc_sz = SW_DESC_CNTXT_C2H_STREAM_DMA; diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_devops.h b/QDMA/DPDK/drivers/net/qdma/qdma_devops.h index 56c0d286..be8a8f7b 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_devops.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_devops.h @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2020-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.c b/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.c index 1b4e7671..d734c0ce 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.c @@ -1,3 +1,36 @@ +/*- + * BSD LICENSE + * + * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + #include #include #include @@ -23,7 +56,8 @@ #include "qdma_devops.h" -#if defined(QDMA_DPDK_21_11) || defined(QDMA_DPDK_22_11) +#if defined(QDMA_DPDK_21_11) || defined(QDMA_DPDK_22_11) || \ + defined(QDMA_DPDK_23_11) void qdma_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t queue_id) @@ -285,7 +319,9 @@ void rte_pmd_qdma_dev_started(int port_id, bool status) int rte_pmd_qdma_dev_fp_ops_config(int port_id) { -#if (defined(QDMA_DPDK_21_11) || defined(QDMA_DPDK_22_11)) +#if defined(QDMA_DPDK_21_11) || defined(QDMA_DPDK_22_11) || \ + defined(QDMA_DPDK_23_11) + struct rte_eth_dev *dev; struct rte_eth_fp_ops *fpo = rte_eth_fp_ops; diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.h b/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.h index dfe35864..548a2b70 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_dpdk_compat.h @@ -1,7 +1,41 @@ +/*- + * BSD LICENSE + * + * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + #ifndef __QDMA_DPDK_COMPAT_H__ #define __QDMA_DPDK_COMPAT_H__ -#if (defined(QDMA_DPDK_21_11) || defined(QDMA_DPDK_22_11)) +#if (defined(QDMA_DPDK_21_11) || defined(QDMA_DPDK_22_11) || \ + defined(QDMA_DPDK_23_11)) #include #include diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c b/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c index 6bd6147f..bc5f3a26 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_ethdev.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -596,13 +596,6 @@ int qdma_eth_dev_init(struct rte_eth_dev *dev) dma_priv->bypass_bar_idx = BAR_ID_INVALID; dma_priv->user_bar_idx = BAR_ID_INVALID; - /* Check and handle device devargs*/ - if (qdma_check_kvargs(dev->device->devargs, dma_priv)) { - PMD_DRV_LOG(INFO, "devargs failed\n"); - rte_free(dev->data->mac_addrs); - return -EINVAL; - } - /* Store BAR address and length of Config BAR */ baseaddr = (uint8_t *) pci_dev->mem_resource[dma_priv->config_bar_idx].addr; @@ -650,6 +643,13 @@ int qdma_eth_dev_init(struct rte_eth_dev *dev) /* Getting the device attributes from the Hardware */ qdma_device_attributes_get(dev); + /* Check and handle device devargs*/ + if (qdma_check_kvargs(dev->device->devargs, dma_priv)) { + PMD_DRV_LOG(INFO, "devargs failed\n"); + rte_free(dev->data->mac_addrs); + return -EINVAL; + } + /* Setting default Mode to RTE_PMD_QDMA_TRIG_MODE_USER_TIMER */ dma_priv->trigger_mode = RTE_PMD_QDMA_TRIG_MODE_USER_TIMER; diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_log.h b/QDMA/DPDK/drivers/net/qdma/qdma_log.h index 6851db75..75a5b274 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_log.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_log.h @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c index e1cd2a5e..f4a628b9 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h index d861342f..ec3534db 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_mbox.h @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_platform.c b/QDMA/DPDK/drivers/net/qdma/qdma_platform.c index 9abe8f65..2a9d3e4a 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_platform.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_platform.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h b/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h index 69d5e591..9383ca76 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_platform_env.h @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c index 186c1bb3..87966361 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h index 58ac9e56..29558991 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx.h @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx_vec_sse.c b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx_vec_sse.c index 34809dd6..2e13e8c2 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_rxtx_vec_sse.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_rxtx_vec_sse.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_user.c b/QDMA/DPDK/drivers/net/qdma/qdma_user.c index a487de66..9ce1dfc2 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_user.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_user.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_user.h b/QDMA/DPDK/drivers/net/qdma/qdma_user.h index 9c3de6f8..2bf475fa 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_user.h +++ b/QDMA/DPDK/drivers/net/qdma/qdma_user.h @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2018-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c b/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c index 219af04e..1c03b1b9 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_vf_ethdev.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -822,6 +822,7 @@ static int qdma_vf_dev_configure(struct rte_eth_dev *dev) qdma_dev->q_info[qid].rx_bypass_mode = qdma_dev->c2h_bypass_mode; qdma_dev->q_info[qid].trigger_mode = qdma_dev->trigger_mode; + qdma_dev->q_info[qid].en_prefetch = qdma_dev->en_desc_prefetch; qdma_dev->q_info[qid].timer_count = qdma_dev->timer_count; } @@ -1078,12 +1079,6 @@ static int eth_qdma_vf_dev_init(struct rte_eth_dev *dev) dma_priv->bypass_bar_idx = BAR_ID_INVALID; dma_priv->user_bar_idx = BAR_ID_INVALID; - if (qdma_check_kvargs(dev->device->devargs, dma_priv)) { - PMD_DRV_LOG(INFO, "devargs failed\n"); - rte_free(dev->data->mac_addrs); - return -EINVAL; - } - /* Store BAR address and length of Config BAR */ baseaddr = (uint8_t *) pci_dev->mem_resource[dma_priv->config_bar_idx].addr; @@ -1139,6 +1134,13 @@ static int eth_qdma_vf_dev_init(struct rte_eth_dev *dev) return -EINVAL; } + if (qdma_check_kvargs(dev->device->devargs, dma_priv)) { + PMD_DRV_LOG(INFO, "devargs failed\n"); + rte_free(dma_priv->hw_access); + rte_free(dev->data->mac_addrs); + return -EINVAL; + } + /* Setting default Mode to RTE_PMD_QDMA_TRIG_MODE_USER_TIMER */ dma_priv->trigger_mode = RTE_PMD_QDMA_TRIG_MODE_USER_TIMER; diff --git a/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c b/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c index 4cade046..cb38a8f6 100755 --- a/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c +++ b/QDMA/DPDK/drivers/net/qdma/qdma_xdebug.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -413,8 +413,6 @@ static int qdma_device_dump(uint8_t port_id) qdma_dev->en_desc_prefetch); xdebug_info("\t\t ip type :%x\n", qdma_dev->ip_type); - xdebug_info("\t\t vivado release :%x\n", - qdma_dev->vivado_rel); xdebug_info("\t\t rtl version :%x\n", qdma_dev->rtl_version); xdebug_info("\t\t is queue conigured :%x\n", @@ -729,7 +727,7 @@ static int qdma_c2h_context_dump(uint8_t port_id, uint16_t queue) qid = qdma_dev->queue_base + queue; ip_type = (enum qdma_ip_type)qdma_dev->ip_type; device_type = (enum qdma_device_type)qdma_dev->device_type; - st_mode = qdma_dev->q_info[qid].queue_mode; + st_mode = qdma_dev->q_info[queue].queue_mode; q_type = QDMA_DEV_Q_TYPE_C2H; if (queue >= dev->data->nb_rx_queues) { @@ -814,7 +812,7 @@ static int qdma_h2c_context_dump(uint8_t port_id, uint16_t queue) qid = qdma_dev->queue_base + queue; ip_type = (enum qdma_ip_type)qdma_dev->ip_type; device_type = (enum qdma_device_type)qdma_dev->device_type; - st_mode = qdma_dev->q_info[qid].queue_mode; + st_mode = qdma_dev->q_info[queue].queue_mode; q_type = QDMA_DEV_Q_TYPE_H2C; if (queue >= dev->data->nb_tx_queues) { @@ -900,7 +898,7 @@ static int qdma_cmpt_context_dump(uint8_t port_id, uint16_t queue) qid = qdma_dev->queue_base + queue; ip_type = (enum qdma_ip_type)qdma_dev->ip_type; device_type = (enum qdma_device_type)qdma_dev->device_type; - st_mode = qdma_dev->q_info[qid].queue_mode; + st_mode = qdma_dev->q_info[queue].queue_mode; q_type = QDMA_DEV_Q_TYPE_CMPT; if (queue >= dev->data->nb_rx_queues) { @@ -1388,7 +1386,6 @@ int rte_pmd_qdma_dbg_qinfo(uint8_t port_id, uint16_t queue) { struct rte_eth_dev *dev; struct qdma_pci_dev *qdma_dev; - uint16_t qid; uint8_t st_mode; int err; @@ -1399,8 +1396,7 @@ int rte_pmd_qdma_dbg_qinfo(uint8_t port_id, uint16_t queue) dev = &rte_eth_devices[port_id]; qdma_dev = dev->data->dev_private; - qid = qdma_dev->queue_base + queue; - st_mode = qdma_dev->q_info[qid].queue_mode; + st_mode = qdma_dev->q_info[queue].queue_mode; err = qdma_h2c_context_dump(port_id, queue); if (err) { diff --git a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c index d2b93ba1..759861d4 100755 --- a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c +++ b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.c @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -1501,19 +1501,21 @@ static int qdma_pf_cmptq_context_write(struct rte_eth_dev *dev, uint32_t qid) break; } - q_cmpt_ctxt.en_stat_desc = 1; - q_cmpt_ctxt.trig_mode = cmptq->triggermode; - q_cmpt_ctxt.fnc_id = cmptq->func_id; - q_cmpt_ctxt.counter_idx = cmptq->threshidx; - q_cmpt_ctxt.timer_idx = cmptq->timeridx; - q_cmpt_ctxt.color = CMPT_DEFAULT_COLOR_BIT; - q_cmpt_ctxt.ringsz_idx = cmptq->ringszidx; + q_cmpt_ctxt.lower_dword.bit.en_stat_desc = 1; + q_cmpt_ctxt.lower_dword.bit.trig_mode = cmptq->triggermode; + q_cmpt_ctxt.lower_dword.bit.fnc_id = cmptq->func_id; + q_cmpt_ctxt.lower_dword.bit.counter_idx = cmptq->threshidx; + q_cmpt_ctxt.lower_dword.bit.timer_idx = cmptq->timeridx; + q_cmpt_ctxt.lower_dword.bit.color = CMPT_DEFAULT_COLOR_BIT; + q_cmpt_ctxt.lower_dword.bit.ringsz_idx = cmptq->ringszidx; q_cmpt_ctxt.bs_addr = (uint64_t)cmptq->cmpt_mz->iova; - q_cmpt_ctxt.desc_sz = cmpt_desc_fmt; - q_cmpt_ctxt.valid = 1; - + q_cmpt_ctxt.higher_dword.bit.desc_sz = cmpt_desc_fmt; + q_cmpt_ctxt.higher_dword.bit.valid = 1; + if (cmptq->st_mode) + q_cmpt_ctxt.higher_dword.bit.dir_c2h = 1; if (qdma_dev->dev_cap.cmpt_ovf_chk_dis) - q_cmpt_ctxt.ovf_chk_dis = cmptq->dis_overflow_check; + q_cmpt_ctxt.higher_dword.bit.ovf_chk_dis = + cmptq->dis_overflow_check; /* Set Completion Context */ err = qdma_dev->hw_access->qdma_cmpt_ctx_conf(dev, (qid + queue_base), diff --git a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h index 8a6e95c9..ba8cc26b 100755 --- a/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h +++ b/QDMA/DPDK/drivers/net/qdma/rte_pmd_qdma.h @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2019-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/QDMA/DPDK/drivers/net/qdma/version.h b/QDMA/DPDK/drivers/net/qdma/version.h index 8e44e3a2..d0b7be18 100755 --- a/QDMA/DPDK/drivers/net/qdma/version.h +++ b/QDMA/DPDK/drivers/net/qdma/version.h @@ -2,7 +2,7 @@ * BSD LICENSE * * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -37,9 +37,9 @@ #define qdma_stringify1(x...) #x #define qdma_stringify(x...) qdma_stringify1(x) -#define QDMA_PMD_MAJOR 2023 -#define QDMA_PMD_MINOR 2 -#define QDMA_PMD_PATCHLEVEL 1 +#define QDMA_PMD_MAJOR 2024 +#define QDMA_PMD_MINOR 1 +#define QDMA_PMD_PATCHLEVEL 0 #define QDMA_PMD_VERSION \ qdma_stringify(QDMA_PMD_MAJOR) "." \ diff --git a/QDMA/DPDK/drivers/net/qdma/version.map b/QDMA/DPDK/drivers/net/qdma/version.map index 29441454..088cd043 100755 --- a/QDMA/DPDK/drivers/net/qdma/version.map +++ b/QDMA/DPDK/drivers/net/qdma/version.map @@ -1,37 +1,4 @@ -/*- - * BSD LICENSE - * - * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -DPDK_21 { +DPDK_24 { global: rte_pmd_qdma_set_immediate_data_state; @@ -65,102 +32,18 @@ DPDK_21 { rte_pmd_qdma_qstats_clear; rte_pmd_qdma_dev_close; rte_pmd_qdma_dev_fp_ops_config; + rte_pmd_qdma_compat_pci_write_reg; + rte_pmd_qdma_compat_pci_read_reg; + rte_pmd_qdma_compat_memzone_reserve_aligned; + rte_pmd_qdma_get_bdf; + rte_pmd_qdma_dev_remove; + rte_pmd_qdma_get_dev_id; + rte_pmd_qdma_dev_started; + rte_pmd_qdma_eth_dev_to_pci; + rte_pmd_qdma_get_device; + rte_pmd_qdma_validate_dev; local: *; }; -DPDK_22 { - global: - - rte_pmd_qdma_set_immediate_data_state; - rte_pmd_qdma_get_bar_details; - rte_pmd_qdma_get_queue_base; - rte_pmd_qdma_set_queue_mode; - rte_pmd_qdma_get_device_capabilities; - qdma_pci_read_reg; - qdma_pci_write_reg; - rte_pmd_qdma_set_mm_endpoint_addr; - rte_pmd_qdma_dbg_qdesc; - rte_pmd_qdma_dbg_regdump; - rte_pmd_qdma_dbg_reg_info_dump; - rte_pmd_qdma_dbg_qinfo; - - rte_pmd_qdma_get_pci_func_type; - rte_pmd_qdma_configure_tx_bypass; - rte_pmd_qdma_configure_rx_bypass; - rte_pmd_qdma_set_cmpt_descriptor_size; - rte_pmd_qdma_set_c2h_descriptor_prefetch; - rte_pmd_qdma_set_cmpt_overflow_check; - rte_pmd_qdma_set_cmpt_trigger_mode; - rte_pmd_qdma_set_cmpt_timer; - rte_pmd_qdma_get_immediate_data_state; - rte_pmd_qdma_dev_cmptq_setup; - rte_pmd_qdma_dev_cmptq_start; - rte_pmd_qdma_mm_cmpt_process; - rte_pmd_qdma_dev_cmptq_stop; - rte_pmd_qdma_dbg_qdevice; - rte_pmd_qdma_qstats; - rte_pmd_qdma_qstats_clear; - rte_pmd_qdma_dev_close; - rte_pmd_qdma_dev_fp_ops_config; - rte_pmd_qdma_compat_pci_write_reg; - rte_pmd_qdma_compat_pci_read_reg; - rte_pmd_qdma_compat_memzone_reserve_aligned; - rte_pmd_qdma_get_bdf; - rte_pmd_qdma_dev_remove; - rte_pmd_qdma_get_dev_id; - rte_pmd_qdma_dev_started; - rte_pmd_qdma_eth_dev_to_pci; - rte_pmd_qdma_get_device; - rte_pmd_qdma_validate_dev; - - local: *; -}; -DPDK_23 { - global: - - rte_pmd_qdma_set_immediate_data_state; - rte_pmd_qdma_get_bar_details; - rte_pmd_qdma_get_queue_base; - rte_pmd_qdma_set_queue_mode; - rte_pmd_qdma_get_device_capabilities; - qdma_pci_read_reg; - qdma_pci_write_reg; - rte_pmd_qdma_set_mm_endpoint_addr; - rte_pmd_qdma_dbg_qdesc; - rte_pmd_qdma_dbg_regdump; - rte_pmd_qdma_dbg_reg_info_dump; - rte_pmd_qdma_dbg_qinfo; - - rte_pmd_qdma_get_pci_func_type; - rte_pmd_qdma_configure_tx_bypass; - rte_pmd_qdma_configure_rx_bypass; - rte_pmd_qdma_set_cmpt_descriptor_size; - rte_pmd_qdma_set_c2h_descriptor_prefetch; - rte_pmd_qdma_set_cmpt_overflow_check; - rte_pmd_qdma_set_cmpt_trigger_mode; - rte_pmd_qdma_set_cmpt_timer; - rte_pmd_qdma_get_immediate_data_state; - rte_pmd_qdma_dev_cmptq_setup; - rte_pmd_qdma_dev_cmptq_start; - rte_pmd_qdma_mm_cmpt_process; - rte_pmd_qdma_dev_cmptq_stop; - rte_pmd_qdma_dbg_qdevice; - rte_pmd_qdma_qstats; - rte_pmd_qdma_qstats_clear; - rte_pmd_qdma_dev_close; - rte_pmd_qdma_dev_fp_ops_config; - rte_pmd_qdma_compat_pci_write_reg; - rte_pmd_qdma_compat_pci_read_reg; - rte_pmd_qdma_compat_memzone_reserve_aligned; - rte_pmd_qdma_get_bdf; - rte_pmd_qdma_dev_remove; - rte_pmd_qdma_get_dev_id; - rte_pmd_qdma_dev_started; - rte_pmd_qdma_eth_dev_to_pci; - rte_pmd_qdma_get_device; - rte_pmd_qdma_validate_dev; - - local: *; -}; diff --git a/QDMA/DPDK/tools/0001-Add-QDMA-xdebug-to-proc-info-of-dpdk-23.11.patch b/QDMA/DPDK/tools/0001-Add-QDMA-xdebug-to-proc-info-of-dpdk-23.11.patch new file mode 100644 index 00000000..be1dcc3b --- /dev/null +++ b/QDMA/DPDK/tools/0001-Add-QDMA-xdebug-to-proc-info-of-dpdk-23.11.patch @@ -0,0 +1,428 @@ +From 9b5e6f975624d14492e8e407d300a90e7dbb1f29 Mon Sep 17 00:00:00 2001 +From: Bharat Kumar Gogada +Date: Fri, 19 Jul 2024 14:39:01 +0530 +Subject: [PATCH] Add QDMA xdebug to proc-info of dpdk-23.11 + +Signed-off-by: Bharat Kumar Gogada +--- + app/proc-info/main.c | 281 +++++++++++++++++++++++++++++++------- + app/proc-info/meson.build | 2 +- + app/test-pmd/config.c | 2 + + 3 files changed, 232 insertions(+), 53 deletions(-) + +diff --git a/app/proc-info/main.c b/app/proc-info/main.c +index b672aaefbe..1aacd3d537 100644 +--- a/app/proc-info/main.c ++++ b/app/proc-info/main.c +@@ -31,6 +31,7 @@ + #ifdef RTE_LIB_METRICS + #include + #endif ++#include + #include + #ifdef RTE_LIB_SECURITY + #include +@@ -55,9 +56,31 @@ + STATS_BDR_FMT, s, w, STATS_BDR_FMT) + + /* mask of enabled ports */ +-static unsigned long enabled_port_mask; ++static uint64_t enabled_port_mask; ++/**< QID for queue context */ ++static uint32_t qid; ++/**< desc dump type */ ++static uint32_t desc_type; ++/**< QID for desc start value */ ++static uint32_t start; ++/**< QID for desc end value */ ++static uint32_t end; ++/**< Enable desc dump. */ ++static uint32_t enable_desc_dump; + /* Enable stats. */ + static uint32_t enable_stats; ++/**< Enable Device Structs */ ++static uint32_t qdma_device; ++/**< Enable QDMA Tx and Rx queue stats */ ++static uint32_t qdma_qstats; ++/**< Clear QDMA Tx and Rx queue stats */ ++static uint32_t qdma_qstats_clear; ++/**< Enable Queue context and Queue structs. */ ++static uint32_t queue_info; ++/**< Enable register field information. */ ++static uint32_t reg_info; ++/**< Register address */ ++static uint32_t reg_addr; + /* Enable xstats. */ + static uint32_t enable_xstats; + /* Enable collectd format */ +@@ -76,6 +99,8 @@ static uint32_t reset_stats; + static uint32_t reset_xstats; + /* Enable memory info. */ + static uint32_t mem_info; ++/**< Enable Global Errors . */ ++static uint32_t qdma_csr_info; + /* Enable displaying xstat name. */ + static uint32_t enable_xstats_name; + static char *xstats_name; +@@ -159,8 +184,15 @@ proc_info_usage(const char *prgname) + { + printf("%s [EAL options] -- -p PORTMASK\n" + " -m to display DPDK memory zones, segments and TAILQ information\n" ++ " -g to display DPDK QDMA PMD global CSR info\n" + " -p PORTMASK: hexadecimal bitmask of ports to retrieve stats for\n" + " --stats: to display port statistics, enabled by default\n" ++ " --qdevice: to display QDMA device structure\n" ++ " --qstats: to display QDMA Tx and Rx queue stats\n" ++ " --qstats_clr: to clear QDMA Tx and Rx queue stats\n" ++ " --qinfo: to display QDMA queue context and queue structures\n" ++ " --reg-info {reg_addr}: to display field info of a register at reg_addr offset\n" ++ " --desc-dump {rx | tx | cmpt}: to dump QDMA queue descriptors\n" + " --xstats: to display extended port statistics, disabled by " + "default\n" + #ifdef RTE_LIB_METRICS +@@ -205,7 +237,7 @@ proc_info_usage(const char *prgname) + /* + * Parse the portmask provided at run time. + */ +-static int ++static int64_t + parse_portmask(const char *portmask) + { + char *end = NULL; +@@ -222,6 +254,71 @@ parse_portmask(const char *portmask) + return 0; + } + ++/* ++ * * Parse the QID provided at run time. ++ **/ ++static int ++parse_int(const char *id) ++{ ++ char *end = NULL; ++ unsigned long val; ++ ++ errno = 0; ++ ++ /* parse hexadecimal string */ ++ val = strtoul(id, &end, 10); ++ if ((id[0] == '\0') || (end == NULL) || (*end != '\0') || ++ (errno != 0)) { ++ printf("%s ERROR parsing the QID\n", __func__); ++ return -1; ++ } ++ ++ return val; ++} ++ ++/* ++ * Parse the register address provided at run time. ++ */ ++static int32_t ++parse_reg_addr(const char *addr) ++{ ++ char *end = NULL; ++ ++ errno = 0; ++ ++ /* parse hexadecimal string */ ++ reg_addr = strtoul(addr, &end, 16); ++ if ((addr[0] == '\0') || (end == NULL) || (*end != '\0') || ++ (errno != 0)) { ++ printf("%s ERROR parsing the register address\n", __func__); ++ return -1; ++ } ++ ++ if (reg_addr == 0) ++ return -1; ++ ++ return reg_addr; ++} ++ ++/* ++ * * Parse the desc dump type provided at run time. ++ **/ ++static int ++parse_desc_type(const char *type) ++{ ++ if (!strcmp(type, "rx")) { ++ desc_type = RTE_PMD_QDMA_XDEBUG_DESC_C2H; ++ } else if (!strcmp(type, "tx")) { ++ desc_type = RTE_PMD_QDMA_XDEBUG_DESC_H2C; ++ } else if (!strcmp(type, "cmpt")) { ++ desc_type = RTE_PMD_QDMA_XDEBUG_DESC_CMPT; ++ } else { ++ printf("%s ERROR parsing the desc type\n", __func__); ++ return -1; ++ } ++ return 0; ++} ++ + /* + * Parse ids value list into array + */ +@@ -418,11 +515,17 @@ proc_info_preparse_args(int argc, char **argv) + static int + proc_info_parse_args(int argc, char **argv) + { +- int opt; ++ int opt, ret; + int option_index; + char *prgname = argv[0]; + static struct option long_option[] = { + {"stats", 0, NULL, 0}, ++ {"qdevice", 0, NULL, 0}, ++ {"qstats", 0, NULL, 0}, ++ {"qstats_clr", 0, NULL, 0}, ++ {"qinfo", 0, NULL, 0}, ++ {"reg-info", required_argument, NULL, 1}, ++ {"desc-dump", required_argument, NULL, 1}, + {"stats-reset", 0, NULL, 0}, + {"xstats", 0, NULL, 0}, + #ifdef RTE_LIB_METRICS +@@ -459,7 +562,7 @@ proc_info_parse_args(int argc, char **argv) + proc_info_usage(prgname); + + /* Parse command line */ +- while ((opt = getopt_long(argc, argv, "p:m", ++ while ((opt = getopt_long(argc, argv, "p:mq:gs:e:", + long_option, &option_index)) != EOF) { + switch (opt) { + /* portmask */ +@@ -472,11 +575,54 @@ proc_info_parse_args(int argc, char **argv) + case 'm': + mem_info = 1; + break; ++ case 'g': ++ qdma_csr_info = 1; ++ break; ++ case 'q': ++ ret = parse_int(optarg); ++ if (ret < 0) { ++ printf("Invalid queue\n"); ++ return -1; ++ } ++ qid = ret; ++ break; ++ case 's': ++ ret = parse_int(optarg); ++ if (ret < 0) { ++ printf("Invalid start value\n"); ++ return -1; ++ } ++ start = ret; ++ break; ++ case 'e': ++ ret = parse_int(optarg); ++ if (ret < 0) { ++ printf("Invalid end value\n"); ++ return -1; ++ } ++ end = ret; ++ break; + case 0: + /* Print stats */ + if (!strncmp(long_option[option_index].name, "stats", + MAX_LONG_OPT_SZ)) + enable_stats = 1; ++ /* Print qdma device */ ++ if (!strncmp(long_option[option_index].name, "qdevice", ++ MAX_LONG_OPT_SZ)) ++ qdma_device = 1; ++ /* Print qdma Tx and Rx queue stats */ ++ if (!strncmp(long_option[option_index].name, "qstats", ++ MAX_LONG_OPT_SZ)) ++ qdma_qstats = 1; ++ /* Clear qdma Tx and Rx queue stats */ ++ if (!strncmp(long_option[option_index].name, "qstats_clr", ++ MAX_LONG_OPT_SZ)) ++ qdma_qstats_clear = 1; ++ /* Print queue context and queue Structures*/ ++ if (!strncmp(long_option[option_index].name, "qinfo", ++ MAX_LONG_OPT_SZ)) ++ queue_info = 1; + /* Print xstats */ + else if (!strncmp(long_option[option_index].name, "xstats", + MAX_LONG_OPT_SZ)) +@@ -616,6 +762,24 @@ proc_info_parse_args(int argc, char **argv) + return -1; + } + enable_shw_tx_desc_dump = 1; ++ } else if (!strncmp(long_option[option_index].name, ++ "desc-dump", ++ MAX_LONG_OPT_SZ)) { ++ if (parse_desc_type(optarg) < 0) { ++ printf("desc-dump parse error.\n"); ++ proc_info_usage(prgname); ++ return -1; ++ } ++ enable_desc_dump = 1; ++ } else if (!strncmp(long_option[option_index].name, ++ "reg-info", ++ MAX_LONG_OPT_SZ)) { ++ if (parse_reg_addr(optarg) < 0) { ++ printf("reg-info parse error.\n"); ++ proc_info_usage(prgname); ++ return -1; ++ } ++ reg_info = 1; + } + break; + default: +@@ -2166,7 +2330,6 @@ main(int argc, char **argv) + + if (mem_info) { + meminfo_display(); +- return 0; + } + + if (eventdev_xstats() > 0) +@@ -2185,7 +2348,7 @@ main(int argc, char **argv) + for (i = 0; i < RTE_MAX_ETHPORTS; i++) { + + /* Skip if port is not in mask */ +- if ((enabled_port_mask & (1ul << i)) == 0) ++ if ((enabled_port_mask & ((uint64_t)1 << i)) == 0) + continue; + + /* Skip if port is unused */ +@@ -2209,51 +2372,65 @@ main(int argc, char **argv) + else if (enable_metrics) + metrics_display(i); + #endif ++ else if (qdma_csr_info) ++ rte_pmd_qdma_dbg_regdump(i); ++ else if (qdma_device) ++ rte_pmd_qdma_dbg_qdevice(i); ++ else if (qdma_qstats) ++ rte_pmd_qdma_qstats(i, qid); ++ else if (qdma_qstats_clear) ++ rte_pmd_qdma_qstats_clear(i, qid); ++ else if (queue_info) ++ rte_pmd_qdma_dbg_qinfo(i, qid); ++ else if (reg_info) ++ rte_pmd_qdma_dbg_reg_info_dump(i, ++ 1, reg_addr); ++ else if (enable_desc_dump) { ++ rte_pmd_qdma_dbg_qdesc(i, qid, ++ start, end, desc_type); ++ ++ if (enable_shw_rx_desc_dump) ++ nic_rx_descriptor_display(i, &rx_desc_param); ++ if (enable_shw_tx_desc_dump) ++ nic_tx_descriptor_display(i, &tx_desc_param); ++ } ++ } + +- if (enable_shw_rx_desc_dump) +- nic_rx_descriptor_display(i, &rx_desc_param); +- if (enable_shw_tx_desc_dump) +- nic_tx_descriptor_display(i, &tx_desc_param); +- } +- +-#ifdef RTE_LIB_METRICS +- /* print port independent stats */ +- if (enable_metrics) +- metrics_display(RTE_METRICS_GLOBAL); +-#endif +- +- /* show information for PMD */ +- if (enable_shw_port) +- show_port(); +- if (enable_shw_port_priv) +- show_port_private_info(); +- if (enable_shw_tm) +- show_tm(); +- if (enable_shw_crypto) +- show_crypto(); +- if (enable_shw_ring) +- show_ring(ring_name); +- if (enable_shw_mempool) +- show_mempool(mempool_name); +- if (enable_iter_mempool) +- iter_mempool(mempool_iter_name); +- if (enable_dump_regs) +- dump_regs(dump_regs_file_prefix); +- if (enable_shw_version) +- show_version(); +- if (enable_shw_fw_version) +- show_firmware_version(); +- if (enable_shw_rss_reta) +- show_port_rss_reta_info(); +- if (enable_shw_module_eeprom) +- show_module_eeprom_info(); +- +- RTE_ETH_FOREACH_DEV(i) +- rte_eth_dev_close(i); +- +- ret = rte_eal_cleanup(); +- if (ret) +- printf("Error from rte_eal_cleanup(), %d\n", ret); ++ #ifdef RTE_LIB_METRICS ++ /* print port independent stats */ ++ if (enable_metrics) ++ metrics_display(RTE_METRICS_GLOBAL); ++ #endif ++ ++ /* show information for PMD */ ++ if (enable_shw_port) ++ show_port(); ++ if (enable_shw_port_priv) ++ show_port_private_info(); ++ if (enable_shw_tm) ++ show_tm(); ++ if (enable_shw_crypto) ++ show_crypto(); ++ if (enable_shw_ring) ++ show_ring(ring_name); ++ if (enable_shw_mempool) ++ show_mempool(mempool_name); ++ if (enable_iter_mempool) ++ iter_mempool(mempool_iter_name); ++ if (enable_dump_regs) ++ dump_regs(dump_regs_file_prefix); ++ if (enable_shw_version) ++ show_version(); ++ if (enable_shw_fw_version) ++ show_firmware_version(); ++ if (enable_shw_rss_reta) ++ show_port_rss_reta_info(); ++ if (enable_shw_module_eeprom) ++ show_module_eeprom_info(); ++ ++ ret = rte_eal_cleanup(); ++ if (ret) ++ printf("Error from rte_eal_cleanup(), %d\n", ret); + +- return 0; +-} ++ return 0; ++ } +diff --git a/app/proc-info/meson.build b/app/proc-info/meson.build +index 4f83f29a64..f7b7fcbb17 100644 +--- a/app/proc-info/meson.build ++++ b/app/proc-info/meson.build +@@ -8,7 +8,7 @@ if is_windows + endif + + sources = files('main.c') +-deps += ['ethdev', 'security', 'eventdev'] ++deps += ['ethdev', 'metrics', 'security', 'eventdev', 'net_qdma'] + if dpdk_conf.has('RTE_LIB_METRICS') + deps += 'metrics' + endif +diff --git a/app/test-pmd/config.c b/app/test-pmd/config.c +index cad7537bc6..413ca0960a 100644 +--- a/app/test-pmd/config.c ++++ b/app/test-pmd/config.c +@@ -59,6 +59,8 @@ + #include "testpmd.h" + #include "cmdline_mtr.h" + ++#include ++ + #define ETHDEV_FWVERS_LEN 32 + + #ifdef CLOCK_MONOTONIC_RAW /* Defined in glibc bits/time.h */ +-- +2.34.1 diff --git a/QDMA/DPDK/tools/0001-PKTGEN-24.03.1-Patch-to-add-Jumbo-packet-support.patch b/QDMA/DPDK/tools/0001-PKTGEN-24.03.1-Patch-to-add-Jumbo-packet-support.patch new file mode 100644 index 00000000..575a1fd0 --- /dev/null +++ b/QDMA/DPDK/tools/0001-PKTGEN-24.03.1-Patch-to-add-Jumbo-packet-support.patch @@ -0,0 +1,423 @@ +diff --git a/app/lpktgenlib.c b/app/lpktgenlib.c +index b6b83bc..1873591 100644 +--- a/app/lpktgenlib.c ++++ b/app/lpktgenlib.c +@@ -13,7 +13,8 @@ + #include + #include + #include "lpktgenlib.h" +- ++#include ++#include + #include + #include + +diff --git a/app/meson.build b/app/meson.build +index 4acf900..1c6d257 100644 +--- a/app/meson.build ++++ b/app/meson.build +@@ -35,7 +35,7 @@ deps += [cc.find_library('rte_net_i40e', dirs: [dpdk_libs_path], required: false + deps += [cc.find_library('rte_net_ixgbe', dirs: [dpdk_libs_path], required: false)] + deps += [cc.find_library('rte_net_ice', dirs: [dpdk_libs_path], required: false)] + deps += [cc.find_library('rte_bus_vdev', dirs: [dpdk_libs_path], required: false)] +- ++deps += [cc.find_library('rte_net_qdma', required: true)] + deps += [dependency('threads')] + deps += [dependency('numa', required: true)] + deps += [dependency('pcap', required: true)] +diff --git a/app/pktgen-cmds.c b/app/pktgen-cmds.c +index ece20c6..788e630 100644 +--- a/app/pktgen-cmds.c ++++ b/app/pktgen-cmds.c +@@ -3125,19 +3125,20 @@ void + single_set_pkt_size(port_info_t *info, uint16_t size) + { + pkt_seq_t *pkt = &info->seq_pkt[SINGLE_PKT]; +- ++ uint16_t pktsize = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? ++ MAX_PKT_SIZE : (RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN); + if (size < RTE_ETHER_CRC_LEN) + size = RTE_ETHER_CRC_LEN; +- + if ((size - RTE_ETHER_CRC_LEN) < MIN_PKT_SIZE) + size = pktgen.eth_min_pkt; +- if ((size - RTE_ETHER_CRC_LEN) > MAX_PKT_SIZE) +- size = pktgen.eth_max_pkt; ++ if ((size - RTE_ETHER_CRC_LEN) > pktsize) ++ size = pktsize + RTE_ETHER_CRC_LEN; + + if ((pkt->ethType == RTE_ETHER_TYPE_IPV6) && (size < (MIN_v6_PKT_SIZE + RTE_ETHER_CRC_LEN))) + size = MIN_v6_PKT_SIZE + RTE_ETHER_CRC_LEN; + + pkt->pktSize = (size - RTE_ETHER_CRC_LEN); ++ pkt->pktSize = size; + + pktgen_packet_ctor(info, SINGLE_PKT, -1); + pktgen_packet_rate(info); +@@ -4273,6 +4274,8 @@ range_set_cos_id(port_info_t *info, char *what, uint8_t id) + void + range_set_pkt_size(port_info_t *info, char *what, uint16_t size) + { ++ uint32_t pktsize = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? ++ MAX_9K_SIZE : RTE_ETHER_MAX_LEN; + if (!strcmp(what, "inc") || !strcmp(what, "increment")) { + if (size > pktgen.eth_max_pkt) + size = pktgen.eth_max_pkt; +@@ -4280,8 +4283,8 @@ range_set_pkt_size(port_info_t *info, char *what, uint16_t size) + } else { + if (size < pktgen.eth_min_pkt) + size = MIN_PKT_SIZE; +- else if (size > pktgen.eth_max_pkt) +- size = MAX_PKT_SIZE; ++ else if (size > pktsize) ++ size = pktsize; + else + size -= RTE_ETHER_CRC_LEN; + +diff --git a/app/pktgen-constants.h b/app/pktgen-constants.h +index 6e685ab..47679b8 100644 +--- a/app/pktgen-constants.h ++++ b/app/pktgen-constants.h +@@ -19,7 +19,7 @@ enum { + MAX_PKT_TX_BURST = 128, /* Used to create Max array sizes */ + DEFAULT_PKT_RX_BURST = 64, /* Increasing this number consumes memory very fast */ + DEFAULT_PKT_TX_BURST = 64, /* Increasing this number consumes memory very fast */ +- DEFAULT_RX_DESC = (MAX_PKT_RX_BURST * 8), ++ DEFAULT_RX_DESC = (MAX_PKT_RX_BURST * 8 * 2), + DEFAULT_TX_DESC = (MAX_PKT_TX_BURST * 16), + + DEFAULT_MBUFS_PER_PORT_MULTIPLER = 8, /* Multipler for number of mbufs per port */ +@@ -27,7 +27,7 @@ enum { + MBUF_CACHE_SIZE = 128, + + DEFAULT_PRIV_SIZE = 0, +- ++ MBUF_9K_SIZE = 9018 + RTE_PKTMBUF_HEADROOM + DEFAULT_PRIV_SIZE, + NUM_Q = 64, /**< Number of queues per port. */ + }; + +diff --git a/app/pktgen-latency.c b/app/pktgen-latency.c +index 68ef958..9a69669 100644 +--- a/app/pktgen-latency.c ++++ b/app/pktgen-latency.c +@@ -7,7 +7,8 @@ + /* Created 2016 by Keith Wiles @ intel.com */ + + #include +- ++#include ++#include + #include "lua_config.h" + + #include "pktgen-cmds.h" +diff --git a/app/pktgen-main.c b/app/pktgen-main.c +index da2dc5e..177ac5c 100644 +--- a/app/pktgen-main.c ++++ b/app/pktgen-main.c +@@ -29,6 +29,7 @@ + #include "pktgen-log.h" + #include "cli-functions.h" + ++#include + /* Offset to the mbuf dynamic field holding pktgen data. */ + int pktgen_dynfield_offset = -1; + +@@ -207,8 +208,8 @@ pktgen_parse_args(int argc, char **argv) + pktgen.mbuf_buf_size = RTE_MBUF_DEFAULT_BUF_SIZE; + + pktgen.verbose = 0; +- while ((opt = getopt_long(argc, argvopt, "p:m:f:l:s:g:hPNGTvjtrc", lgopts, &option_index)) != +- EOF) ++ while ((opt = getopt_long(argc, argvopt, "p:m:f:l:s:g:hPNGTvjtr9", lgopts, &option_index)) != ++ EOF) + switch (opt) { + case 't': + pktgen.nb_txd = atoi(optarg); +@@ -319,8 +320,11 @@ pktgen_parse_args(int argc, char **argv) + + case 'h': /* print out the help message */ + pktgen_usage(prgname); +- return -1; +- ++ return -1; ++ case '9': /* MTU 9K support */ ++ pktgen_log_info("%s: case 9... \n", __func__); ++ pktgen.flags |= MTU9K_SUPPORT_FLAG; ++ break; + case 0: /* crc-strip for all ports */ + printf(">>> Strip CRC in hardware is the default\n"); + pktgen_set_hw_strip_crc(1); +@@ -418,7 +422,8 @@ pktgen_lua_dofile(void *ld, const char *filename) + int + main(int argc, char **argv) + { +- uint32_t i; ++ uint32_t nb_ports; ++ int32_t i; + int32_t ret; + struct sigaction sa; + sigset_t set; +@@ -595,13 +600,14 @@ main(int argc, char **argv) + pktgen_stop_running(); + + /* Wait for all of the cores to stop running and exit. */ +- rte_eal_mp_wait_lcore(); +- +- RTE_ETH_FOREACH_DEV(i) +- { +- rte_eth_dev_stop(i); +- rte_delay_us_sleep(100 * 1000); +- } ++ rte_eal_mp_wait_lcore(); ++ nb_ports = rte_eth_dev_count_avail(); ++ for (i = nb_ports-1; i >= 0; i--) { ++ if (rte_pmd_qdma_dev_remove(i)) ++ printf("Failed to detach port '%d'\n", i); ++ else ++ printf("successfully removed port '%d'\n", i); ++} + + cli_destroy(); + scrn_destroy(); +diff --git a/app/pktgen-port-cfg.c b/app/pktgen-port-cfg.c +index 1e6a78d..2f39514 100644 +--- a/app/pktgen-port-cfg.c ++++ b/app/pktgen-port-cfg.c +@@ -10,6 +10,9 @@ + #include + #include + ++#include ++#include ++ + #include "pktgen-port-cfg.h" + + #include "pktgen.h" +@@ -94,22 +97,21 @@ pktgen_mbuf_pool_create(const char *type, uint8_t pid, uint8_t queue_id, uint32_ + struct rte_mempool *mp; + char name[RTE_MEMZONE_NAMESIZE]; + uint64_t sz; +- ++ uint16_t mbuf_sz = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? ++ MBUF_9K_SIZE : DEFAULT_MBUF_SIZE; + snprintf(name, sizeof(name), "%-12s%u:%u", type, pid, queue_id); +- +- sz = nb_mbufs * DEFAULT_MBUF_SIZE; ++ sz = nb_mbufs * (mbuf_sz + sizeof(struct rte_mbuf)); + sz = RTE_ALIGN_CEIL(sz + sizeof(struct rte_mempool), 1024); + + if (pktgen.verbose) +- pktgen_log_info(" Create: '%-*s' - Memory used (MBUFs %6u x size %6u) = %6lu KB", 16, +- name, nb_mbufs, DEFAULT_MBUF_SIZE, sz / 1024); +- ++ pktgen_log_info(" Create: '%-*s' - Memory used (MBUFs %6u x size %6u) = %6lu KB", 16, ++ name, nb_mbufs, mbuf_sz, sizeof(struct rte_mbuf)); + pktgen.mem_used += sz; + pktgen.total_mem_used += sz; + + /* create the mbuf pool */ +- mp = rte_pktmbuf_pool_create(name, nb_mbufs, cache_size, DEFAULT_PRIV_SIZE, DEFAULT_MBUF_SIZE, +- socket_id); ++ mp = rte_pktmbuf_pool_create(name, nb_mbufs, cache_size, DEFAULT_PRIV_SIZE, mbuf_sz, ++ socket_id); + if (mp == NULL) + pktgen_log_panic( + "Cannot create mbuf pool (%s) port %d, queue %d, nb_mbufs %d, socket_id %d: %s", name, +@@ -190,7 +192,8 @@ pktgen_config_ports(void) + pg_port_matrix_dump(pktgen.l2p); + + pktgen_log_info(">>>> Configuring %d ports, MBUF Size %d, MBUF Cache Size %d", +- pktgen.nb_ports, DEFAULT_MBUF_SIZE, MBUF_CACHE_SIZE); ++ pktgen.nb_ports, (pktgen.flags & MTU9K_SUPPORT_FLAG) ? MBUF_9K_SIZE : ++ DEFAULT_MBUF_SIZE, MBUF_CACHE_SIZE); + } + + /* For each lcore setup each port that is handled by that lcore. */ +@@ -315,9 +318,9 @@ pktgen_config_ports(void) + + pktgen.mem_used = 0; + +- if ((ret = rte_eth_dev_set_mtu(pid, pktgen.eth_mtu)) < 0) +- pktgen_log_panic("Cannot set MTU %u on port %u, (%d)%s", pktgen.eth_mtu, pid, -ret, +- rte_strerror(-ret)); ++ //if ((ret = rte_eth_dev_set_mtu(pid, pktgen.eth_mtu)) < 0) ++ // pktgen_log_panic("Cannot set MTU %u on port %u, (%d)%s", pktgen.eth_mtu, pid, -ret, ++ // rte_strerror(-ret)); + + for (int q = 0; q < rt.rx; q++) { + struct rte_eth_rxconf rxq_conf; +diff --git a/app/pktgen-port-cfg.h b/app/pktgen-port-cfg.h +index 130619f..8f19955 100644 +--- a/app/pktgen-port-cfg.h ++++ b/app/pktgen-port-cfg.h +@@ -412,7 +412,7 @@ rte_get_rx_capa_list(uint64_t rx_capa, char *buf, size_t len) + {RTE_ETH_RX_OFFLOAD_TIMESTAMP, _(TIMESTAMP)}, + {RTE_ETH_RX_OFFLOAD_SECURITY, _(SECURITY)}, + {RTE_ETH_RX_OFFLOAD_KEEP_CRC, _(KEEP_CRC)}, +- {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, _(SCTP_CKSUM)}, ++ {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, _(SCTP_CKSUM)}, + {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, _(OUTER_UDP_CKSUM)}, + {RTE_ETH_RX_OFFLOAD_RSS_HASH, _(RSS_HASH)}, + {RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT, _(BUFFER_SPLIT)}}; +diff --git a/app/pktgen-range.c b/app/pktgen-range.c +index 2c43e00..1c84f8a 100644 +--- a/app/pktgen-range.c ++++ b/app/pktgen-range.c +@@ -744,7 +744,8 @@ pktgen_range_setup(port_info_t *info) + range->pkt_size = MIN_PKT_SIZE; + range->pkt_size_inc = 0; + range->pkt_size_min = MIN_PKT_SIZE; +- range->pkt_size_max = MAX_PKT_SIZE; ++ range->pkt_size_max = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? ++ MAX_PKT_SIZE : (RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN); + + range->vxlan_gid = info->seq_pkt[SINGLE_PKT].group_id; + range->vxlan_gid_inc = 0; +diff --git a/app/pktgen-rate.c b/app/pktgen-rate.c +index 1dbd654..400c75b 100644 +--- a/app/pktgen-rate.c ++++ b/app/pktgen-rate.c +@@ -7,7 +7,8 @@ + /* Created 2020 by Keith Wiles @ intel.com */ + + #include +- ++#include ++#include + #include "lua_config.h" + + #include "pktgen-cmds.h" +diff --git a/app/pktgen-stats.c b/app/pktgen-stats.c +index 798f11f..4070529 100644 +--- a/app/pktgen-stats.c ++++ b/app/pktgen-stats.c +@@ -7,7 +7,8 @@ + /* Created 2010 by Keith Wiles @ intel.com */ + + #include +- ++#include ++#include + #include + #include + +diff --git a/app/pktgen.c b/app/pktgen.c +index 6598399..4fac1c2 100644 +--- a/app/pktgen.c ++++ b/app/pktgen.c +@@ -76,6 +76,7 @@ pktgen_wire_size(port_info_t *info) + } else + size = info->seq_pkt[SINGLE_PKT].pktSize + PKT_OVERHEAD_SIZE; + } ++ size -= (PKT_PREAMBLE_SIZE + INTER_FRAME_GAP + RTE_ETHER_CRC_LEN); + return size; + } + +@@ -283,7 +284,6 @@ pktgen_send_burst(port_info_t *info, uint16_t qid) + struct eth_tx_buffer *mtab = info->q[qid].txbuff; + struct rte_mbuf **pkts; + uint32_t tap, rnd; +- + tap = pktgen_tst_port_flags(info, PROCESS_TX_TAP_PKTS); + rnd = pktgen_tst_port_flags(info, SEND_RANDOM_PKTS); + +@@ -866,7 +866,9 @@ pktgen_setup_cb(struct rte_mempool *mp, void *opaque, void *obj, unsigned obj_id + port_info_t *info; + pkt_seq_t *pkt; + uint16_t qid, idx; +- ++ uint32_t pktsize = (pktgen.flags & MTU9K_SUPPORT_FLAG) ? ++ MAX_PKT_SIZE : ++ (RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN); + info = data->info; + qid = data->qid; + +@@ -895,7 +897,7 @@ pktgen_setup_cb(struct rte_mempool *mp, void *opaque, void *obj, unsigned obj_id + + pktgen_packet_ctor(info, idx, -1); + +- rte_memcpy((uint8_t *)m->buf_addr + m->data_off, (uint8_t *)&pkt->hdr, MAX_PKT_SIZE); ++ rte_memcpy((uint8_t *)m->buf_addr + m->data_off, (uint8_t *)&pkt->hdr, pktsize); + + m->pkt_len = pkt->pktSize; + m->data_len = pkt->pktSize; +@@ -1097,7 +1099,7 @@ pktgen_main_receive(port_info_t *info, uint8_t lid, struct rte_mbuf **pkts_burst + { + uint8_t pid; + uint16_t qid, nb_rx; +- capture_t *capture; ++ __rte_unused capture_t *capture; + eth_stats_t *qstats; + int i; + +@@ -1116,9 +1118,13 @@ pktgen_main_receive(port_info_t *info, uint8_t lid, struct rte_mbuf **pkts_burst + return; + + qstats->q_ipackets[qid] += nb_rx; +- for (i = 0; i < nb_rx; i++) ++ for (i = 0; i < nb_rx; i++) + qstats->q_ibytes[qid] += rte_pktmbuf_data_len(pkts_burst[i]); + ++ info->pkt_sizes._64 += nb_rx; ++ rte_pktmbuf_free_bulk(pkts_burst, nb_rx); ++ ++#if 0 + pktgen_tstamp_check(info, pkts_burst, nb_rx); + + /* packets are not freed in the next call. */ +@@ -1134,6 +1140,7 @@ pktgen_main_receive(port_info_t *info, uint8_t lid, struct rte_mbuf **pkts_burst + } + + rte_pktmbuf_free_bulk(pkts_burst, nb_rx); ++#endif + } + + struct pq_info { +diff --git a/app/pktgen.h b/app/pktgen.h +index 728eecd..a67034c 100644 +--- a/app/pktgen.h ++++ b/app/pktgen.h +@@ -243,8 +243,9 @@ enum { + SOCKET0 = 0 /**< Socket ID value for allocation */ + }; + ++#define MAX_9K_SIZE 9018 + #define MIN_PKT_SIZE (pktgen.eth_min_pkt - RTE_ETHER_CRC_LEN) +-#define MAX_PKT_SIZE (pktgen.eth_max_pkt - RTE_ETHER_CRC_LEN) ++#define MAX_PKT_SIZE (MAX_9K_SIZE - RTE_ETHER_CRC_LEN) + + typedef struct rte_mbuf rte_mbuf_t; + +@@ -339,6 +340,7 @@ enum { /* Pktgen flags bits */ + FAKE_PORTS_FLAG = (1 << 9), /**< Fake ports enabled */ + BLINK_PORTS_FLAG = (1 << 10), /**< Blink the port leds */ + ENABLE_THEME_FLAG = (1 << 11), /**< Enable theme or color support */ ++ MTU9K_SUPPORT_FLAG = (1 << 15), /**< MTU 9K support */ + CLOCK_GETTIME_FLAG = (1 << 12), /**< Enable clock_gettime() instead of rdtsc() */ + JUMBO_PKTS_FLAG = (1 << 13), /**< Enable Jumbo frames */ + RESERVED_14 = (1 << 14), +diff --git a/lib/cli/cli_map.c b/lib/cli/cli_map.c +index 1018594..384c81b 100644 +--- a/lib/cli/cli_map.c ++++ b/lib/cli/cli_map.c +@@ -7,7 +7,7 @@ + #include <_atoip.h> + + #include "cli.h" +- ++#include "ctype.h" + int + cli_map_list_search(const char *fmt, char *item, int index) + { +diff --git a/lib/common/pg_strings.c b/lib/common/pg_strings.c +index 38fdf46..eb1c9d0 100644 +--- a/lib/common/pg_strings.c ++++ b/lib/common/pg_strings.c +@@ -3,6 +3,7 @@ + */ + + #include "pg_strings.h" ++#include "ctype.h" + + char * + pg_strtrim(char *str) diff --git a/QDMA/DPDK/tools/README.txt b/QDMA/DPDK/tools/README.txt index 2cddef88..e40e516b 100755 --- a/QDMA/DPDK/tools/README.txt +++ b/QDMA/DPDK/tools/README.txt @@ -1,3 +1,5 @@ +0001-PKTGEN-24.03.1-Patch-to-add-Jumbo-packet-support.patch +is the patch file over dpdk-pktgen v23.11.0 and 0001-PKTGEN-22.04.1-Patch-to-add-Jumbo-packet-support.patch is the patch file over dpdk-pktgen v22.11.0 and 0001-PKTGEN-20.12.0-Patch-to-add-Jumbo-packet-support.patch @@ -14,7 +16,7 @@ This patch is used for performance testing with dpdk-pktgen application. * BSD LICENSE * * Copyright (c) 2017-2022 Xilinx, Inc. All rights reserved. - * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions From 31a4a12ad30fd1aaf1567ed1396f08c24b9ed7b2 Mon Sep 17 00:00:00 2001 From: Devendar Gali Date: Thu, 9 Jan 2025 12:12:54 +0530 Subject: [PATCH 3/8] QDMA: Windows: Update readme file Update the readme file with the current driver support information. Signed-off-by: Devendar Gali --- QDMA/windows/README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/QDMA/windows/README.md b/QDMA/windows/README.md index 414fde44..c02d6da2 100644 --- a/QDMA/windows/README.md +++ b/QDMA/windows/README.md @@ -256,6 +256,7 @@ _____________________________________________________________________________ * Driver installation gives warning due to test signature. * Driver is not fully tuned to achieve maximum IP performance + * The provided example drivers are intended for testing or to be used as a reference, for driver development and will not receive further support for issues or queries. 7. References @@ -263,4 +264,4 @@ _____________________________________________________________________________ [ref2]: https://www.xilinx.com/support/documentation/ip_documentation/qdma/v3_0/pg302-qdma.pdf [ref3]: https://developer.microsoft.com/en-us/windows/hardware/windows-driver-kit [ref4]: https://msdn.microsoft.com/en-us/windows/hardware/drivers/develop/building-a-driver - [ref5]: https://msdn.microsoft.com/en-us/windows/hardware/drivers/install/the-testsigning-boot-configuration-option \ No newline at end of file + [ref5]: https://msdn.microsoft.com/en-us/windows/hardware/drivers/install/the-testsigning-boot-configuration-option From 0b9793ec13cab9c7631910e7f911713b68b272ed Mon Sep 17 00:00:00 2001 From: Devendar Gali Date: Tue, 18 Feb 2025 14:11:04 +0530 Subject: [PATCH 4/8] QDMA: Fix mailbox interrupt registration on VF Register mailbox interrupt handler for VF. Signed-off-by: Devendar Gali --- QDMA/linux-kernel/driver/libqdma/qdma_intr.c | 8 ++++++++ QDMA/linux-kernel/driver/libqdma/qdma_mbox.c | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_intr.c b/QDMA/linux-kernel/driver/libqdma/qdma_intr.c index 7446c1a5..1b1c320c 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_intr.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_intr.c @@ -602,7 +602,11 @@ int intr_setup(struct xlnx_dma_dev *xdev) #ifndef MBOX_INTERRUPT_DISABLE /** Dedicate 1 vector for mailbox interrupts */ +#ifndef __QDMA_VF__ if (xdev->dev_cap.mailbox_en && qdma_mbox_is_irq_available(xdev)) +#else + if (qdma_mbox_is_irq_available(xdev)) +#endif num_vecs_req++; #endif @@ -658,7 +662,11 @@ int intr_setup(struct xlnx_dma_dev *xdev) i = 0; /* This is mandatory, do not delete */ #ifndef MBOX_INTERRUPT_DISABLE +#ifndef __QDMA_VF__ if (xdev->dev_cap.mailbox_en && qdma_mbox_is_irq_available(xdev)) { +#else + if (qdma_mbox_is_irq_available(xdev)) { +#endif /* Mail box interrupt */ rv = intr_vector_setup(xdev, i, INTR_TYPE_MBOX, mbox_intr_handler); diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c b/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c index a2dd527b..620500c1 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c @@ -489,7 +489,11 @@ void qdma_mbox_stop(struct xlnx_dma_dev *xdev) } while (retry_count != 0); mbox_timer_stop(&xdev->mbox); pr_debug("func_id=%d retry_count=%d\n", xdev->func_id, retry_count); +#ifndef __QDMA_VF__ if (xdev->dev_cap.mailbox_en && qdma_mbox_is_irq_available(xdev)) { +#else + if (qdma_mbox_is_irq_available(xdev)) { +#endif if (!xdev->mbox.rx_poll) qdma_mbox_disable_interrupts(xdev, QDMA_DEV); } @@ -574,7 +578,11 @@ int qdma_mbox_init(struct xlnx_dma_dev *xdev) #endif /* ack any received messages in the Q */ qdma_mbox_hw_init(xdev, QDMA_DEV); +#ifndef __QDMA_VF__ if (xdev->dev_cap.mailbox_en && qdma_mbox_is_irq_available(xdev)) { +#else + if (qdma_mbox_is_irq_available(xdev)) { +#endif if ((xdev->conf.qdma_drv_mode != POLL_MODE) && (xdev->conf.qdma_drv_mode != LEGACY_INTR_MODE)) { mbox->rx_poll = 0; From e8ec40374c4c7831195c23109f586ecd03f6b11f Mon Sep 17 00:00:00 2001 From: Apurv Padole Date: Tue, 4 Mar 2025 13:01:36 +0530 Subject: [PATCH 5/8] Update for compilation issue caused by kernel update in Alma 9.4 Signed-off-by: Apurv Padole --- XDMA/linux-kernel/xdma/cdev_ctrl.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/XDMA/linux-kernel/xdma/cdev_ctrl.c b/XDMA/linux-kernel/xdma/cdev_ctrl.c index df60d631..6460d1f0 100644 --- a/XDMA/linux-kernel/xdma/cdev_ctrl.c +++ b/XDMA/linux-kernel/xdma/cdev_ctrl.c @@ -235,8 +235,14 @@ int bridge_mmap(struct file *file, struct vm_area_struct *vma) */ #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) vm_flags_set(vma, VMEM_FLAGS); +#elif defined(RHEL_RELEASE_CODE) + #if (RHEL_RELEASE_CODE > RHEL_RELEASE_VERSION(9, 4)) + vm_flags_set(vma, VMEM_FLAGS); + #else + vma->vm_flags |= VMEM_FLAGS; + #endif #else - vma->vm_flags |= VMEM_FLAGS; + vma->vm_flags |= VMEM_FLAGS; #endif /* make MMIO accessible to user space */ rv = io_remap_pfn_range(vma, vma->vm_start, phys >> PAGE_SHIFT, From b04acfb09c5496016113fb3a4a1cfc4a7073abcd Mon Sep 17 00:00:00 2001 From: Manoj Takasi Date: Fri, 22 Aug 2025 16:32:05 +0530 Subject: [PATCH 6/8] Fix for compilation error caused by kernel update in RHEL 10.0 --- QDMA/linux-kernel/driver/libqdma/qdma_mbox.c | 1 + 1 file changed, 1 insertion(+) diff --git a/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c b/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c index 620500c1..6438c6a2 100755 --- a/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c +++ b/QDMA/linux-kernel/driver/libqdma/qdma_mbox.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "qdma_compat.h" #include "xdev.h" From dd06c2f5478fc5154c49fd6500bb17e56aae34b3 Mon Sep 17 00:00:00 2001 From: "alhussein.jamil" Date: Fri, 10 Oct 2025 15:58:53 +0200 Subject: [PATCH 7/8] Enhance DMA submission interface and fix aperture transfer handling - Introduced new ioctl for DMA submission with error handling. - Updated aperture DMA function to handle full aperture transfers correctly. - Adjusted endpoint address calculations in xdma_xfer_aperture. - Modified descriptor length definition for improved transfer capabilities. --- XDMA/linux-kernel/xdma/cdev_sgdma.c | 88 ++++++++++++++++++++++++++--- XDMA/linux-kernel/xdma/cdev_sgdma.h | 12 ++++ XDMA/linux-kernel/xdma/libxdma.c | 11 +--- XDMA/linux-kernel/xdma/libxdma.h | 2 +- 4 files changed, 97 insertions(+), 16 deletions(-) diff --git a/XDMA/linux-kernel/xdma/cdev_sgdma.c b/XDMA/linux-kernel/xdma/cdev_sgdma.c index 42711732..ee47fc66 100755 --- a/XDMA/linux-kernel/xdma/cdev_sgdma.c +++ b/XDMA/linux-kernel/xdma/cdev_sgdma.c @@ -775,8 +775,7 @@ static int ioctl_do_align_get(struct xdma_engine *engine, unsigned long arg) return put_user(engine->addr_align, (int __user *)arg); } - -static int ioctl_do_aperture_dma(struct xdma_engine *engine, unsigned long arg, +static int ioctl_do_aperture_dma(struct xdma_dev *xdev, struct xdma_engine *engine, unsigned long arg, bool write) { struct xdma_aperture_ioctl io; @@ -819,9 +818,16 @@ static int ioctl_do_aperture_dma(struct xdma_engine *engine, unsigned long arg, return rv; io.error = 0; - res = xdma_xfer_aperture(engine, write, io.ep_addr, io.aperture, - &cb.sgt, 0, write ? h2c_timeout * 1000 : - c2h_timeout * 1000); + if (io.aperture == io.len) { + /* Use read/write interface for full aperture transfers */ + res = xdma_xfer_submit(xdev, engine->channel, write, io.ep_addr, + &cb.sgt, 0, write ? h2c_timeout * 1000 : + c2h_timeout * 1000); + } else { + res = xdma_xfer_aperture(engine, write, io.ep_addr, io.aperture, + &cb.sgt, 0, write ? h2c_timeout * 1000 : + c2h_timeout * 1000); + } char_sgdma_unmap_user_buf(&cb, write); if (res < 0) @@ -840,6 +846,68 @@ static int ioctl_do_aperture_dma(struct xdma_engine *engine, unsigned long arg, return io.error; } +static int ioctl_do_submit_dma(struct xdma_dev *xdev, struct xdma_engine *engine, unsigned long arg, bool write) +{ + struct xdma_submit_ioctl io; + struct xdma_io_cb cb; + ssize_t res; + int rv; + + rv = copy_from_user(&io, (struct xdma_submit_ioctl __user *)arg, + sizeof(struct xdma_submit_ioctl)); + if (rv < 0) { + dbg_tfr("%s failed to copy from user space 0x%lx\n", + engine->name, arg); + return -EINVAL; + } + + dbg_tfr("%s, Submit W %d, buf 0x%lx,%lu, ep %llu.\n", + engine->name, write, io.buffer, io.len, io.ep_addr); + + if ((write && engine->dir != DMA_TO_DEVICE) || + (!write && engine->dir != DMA_FROM_DEVICE)) { + pr_err("r/w mismatch. W %d, dir %d.\n", write, engine->dir); + return -EINVAL; + } + + rv = check_transfer_align(engine, (char *)io.buffer, io.len, + io.ep_addr, 1); + if (rv) { + pr_info("Invalid transfer alignment detected\n"); + return rv; + } + + memset(&cb, 0, sizeof(struct xdma_io_cb)); + cb.buf = (char __user *)io.buffer; + cb.len = io.len; + cb.ep_addr = io.ep_addr; + cb.write = write; + rv = char_sgdma_map_user_buf_to_sgl(&cb, write); + if (rv < 0) + return rv; + + io.error = 0; + res = xdma_xfer_submit(xdev, engine->channel, write, io.ep_addr, + &cb.sgt, 0, write ? h2c_timeout * 1000 : + c2h_timeout * 1000); + + char_sgdma_unmap_user_buf(&cb, write); + if (res < 0) + io.error = res; + else + io.done = res; + + rv = copy_to_user((struct xdma_submit_ioctl __user *)arg, &io, + sizeof(struct xdma_submit_ioctl)); + if (rv < 0) { + dbg_tfr("%s failed to copy to user space 0x%lx, %ld\n", + engine->name, arg, res); + return -EINVAL; + } + + return io.error; +} + static long char_sgdma_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { @@ -876,10 +944,16 @@ static long char_sgdma_ioctl(struct file *file, unsigned int cmd, rv = ioctl_do_align_get(engine, arg); break; case IOCTL_XDMA_APERTURE_R: - rv = ioctl_do_aperture_dma(engine, arg, 0); + rv = ioctl_do_aperture_dma(xdev, engine, arg, 0); break; case IOCTL_XDMA_APERTURE_W: - rv = ioctl_do_aperture_dma(engine, arg, 1); + rv = ioctl_do_aperture_dma(xdev, engine, arg, 1); + break; + case IOCTL_XDMA_SUBMIT_R: + rv = ioctl_do_submit_dma(xdev, engine, arg, 0); + break; + case IOCTL_XDMA_SUBMIT_W: + rv = ioctl_do_submit_dma(xdev, engine, arg, 1); break; default: dbg_perf("Unsupported operation\n"); diff --git a/XDMA/linux-kernel/xdma/cdev_sgdma.h b/XDMA/linux-kernel/xdma/cdev_sgdma.h index 6f7ae158..4b3a6cc0 100644 --- a/XDMA/linux-kernel/xdma/cdev_sgdma.h +++ b/XDMA/linux-kernel/xdma/cdev_sgdma.h @@ -67,6 +67,16 @@ struct xdma_aperture_ioctl { unsigned long done; }; +struct xdma_submit_ioctl { + uint64_t ep_addr; + int channel; + unsigned long buffer; + size_t len; + int timeout_ms; + int error; + size_t done; +}; + /* IOCTL codes */ @@ -78,5 +88,7 @@ struct xdma_aperture_ioctl { #define IOCTL_XDMA_ALIGN_GET _IOR('q', 6, int) #define IOCTL_XDMA_APERTURE_R _IOW('q', 7, struct xdma_aperture_ioctl *) #define IOCTL_XDMA_APERTURE_W _IOW('q', 8, struct xdma_aperture_ioctl *) +#define IOCTL_XDMA_SUBMIT_R _IOW('q', 9, struct xdma_submit_ioctl *) +#define IOCTL_XDMA_SUBMIT_W _IOW('q', 10, struct xdma_submit_ioctl *) #endif /* _XDMA_IOCALLS_POSIX_H_ */ diff --git a/XDMA/linux-kernel/xdma/libxdma.c b/XDMA/linux-kernel/xdma/libxdma.c index 3d9c8652..fe0b83f7 100644 --- a/XDMA/linux-kernel/xdma/libxdma.c +++ b/XDMA/linux-kernel/xdma/libxdma.c @@ -3163,7 +3163,6 @@ ssize_t xdma_xfer_aperture(struct xdma_engine *engine, bool write, u64 ep_addr, unsigned int maxlen = min_t(unsigned int, aperture, desc_blen_max); unsigned int sg_max; unsigned int tlen = 0; - u64 ep_addr_max = ep_addr + aperture - 1; ssize_t done = 0; int i, rv = 0; @@ -3267,7 +3266,7 @@ ssize_t xdma_xfer_aperture(struct xdma_engine *engine, bool write, u64 ep_addr, /* build transfer */ sg = req->sg; - ep_addr = req->ep_addr + (req->offset & (aperture - 1)); + ep_addr = req->ep_addr + req->offset; i = req->sg_idx; for (sg = req->sg; i < sg_max && desc_idx < desc_max; @@ -3284,12 +3283,6 @@ ssize_t xdma_xfer_aperture(struct xdma_engine *engine, bool write, u64 ep_addr, unsigned int len = min_t(unsigned int, tlen, maxlen); - if (ep_addr > ep_addr_max) - ep_addr = req->ep_addr; - - if ((ep_addr + len) > ep_addr_max) - len = ep_addr_max - ep_addr + 1; - xdma_desc_set(engine->desc + desc_idx, addr, ep_addr, len, dir); @@ -3622,6 +3615,8 @@ ssize_t xdma_xfer_submit(void *dev_hndl, int channel, bool write, u64 ep_addr, } else done += xfer->len; + req->ep_addr += xfer->len; + break; case TRANSFER_STATE_FAILED: pr_info("xfer 0x%p,%u, failed, ep 0x%llx.\n", xfer, diff --git a/XDMA/linux-kernel/xdma/libxdma.h b/XDMA/linux-kernel/xdma/libxdma.h index f26f3c2b..32b1cbcb 100755 --- a/XDMA/linux-kernel/xdma/libxdma.h +++ b/XDMA/linux-kernel/xdma/libxdma.h @@ -97,7 +97,7 @@ #define XDMA_ENGINE_CREDIT_XFER_MAX_DESC 0x3FF /* maximum size of a single DMA transfer descriptor */ -#define XDMA_DESC_BLEN_BITS 28 +#define XDMA_DESC_BLEN_BITS 27 #define XDMA_DESC_BLEN_MAX ((1 << (XDMA_DESC_BLEN_BITS)) - 1) /* bits of the SG DMA control register */ From 4a1bf62f45d85aaac32a2abec6b62609fa65ae2c Mon Sep 17 00:00:00 2001 From: "alhussein.jamil" Date: Fri, 10 Oct 2025 16:23:44 +0200 Subject: [PATCH 8/8] Add .gitignore for kernel module build files and update XDMA_DESC_BLEN_BITS to 28 --- .gitignore | 100 +++++++++++++++++++++++++++++++ XDMA/linux-kernel/xdma/libxdma.h | 2 +- 2 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 .gitignore diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..b1e4b0f9 --- /dev/null +++ b/.gitignore @@ -0,0 +1,100 @@ +# Linux Kernel Module Build Files +*.o +*.ko +*.mod +*.mod.c +*.order +*.symvers +*.cmd +.tmp_versions/ +modules.order +Module.symvers + +# Kernel module specific +*.ko.unsigned +*.ko.cmd + +# Object files +*.o.cmd +*.mod.o +*.mod.o.cmd + +# Compiled binaries (tools) +XDMA/linux-kernel/tools/dma_from_device +XDMA/linux-kernel/tools/dma_to_device +XDMA/linux-kernel/tools/performance +XDMA/linux-kernel/tools/reg_rw +XDMA/linux-kernel/tools/test_chrdev +XDMA/linux-kernel/tools/*.o + +# Editor and IDE files +*.swp +*.swo +*~ +.*.sw? +.vscode/ +.idea/ +*.sublime-* +.DS_Store + +# Backup files +*.bak +*.orig +*~ + +# Dependency files +*.d + +# Generated documentation +*.html +*.pdf +/Documentation/DocBook/ + +# Patch files +*.patch +*.diff + +# Compressed files +*.tar +*.tar.gz +*.tar.bz2 +*.zip + +# Core dumps +core + +# Python +__pycache__/ +*.py[cod] +*$py.class +*.so +.Python +venv/ +env/ +ENV/ + +# C/C++ build artifacts +*.a +*.la +*.lo +.libs/ +.deps/ + +# Temporary files +*.tmp +*.temp +/tmp/ + +# Log files +*.log +*.out +*.err + +# Test results +test_results/ +*.test + +# Personal notes and documentation +DRIVER_STATUS.md +notes.txt +TODO.txt diff --git a/XDMA/linux-kernel/xdma/libxdma.h b/XDMA/linux-kernel/xdma/libxdma.h index 32b1cbcb..f26f3c2b 100755 --- a/XDMA/linux-kernel/xdma/libxdma.h +++ b/XDMA/linux-kernel/xdma/libxdma.h @@ -97,7 +97,7 @@ #define XDMA_ENGINE_CREDIT_XFER_MAX_DESC 0x3FF /* maximum size of a single DMA transfer descriptor */ -#define XDMA_DESC_BLEN_BITS 27 +#define XDMA_DESC_BLEN_BITS 28 #define XDMA_DESC_BLEN_MAX ((1 << (XDMA_DESC_BLEN_BITS)) - 1) /* bits of the SG DMA control register */