IP_Integrator

Vivado™ Design Flow Specific Tutorials See Vivado™ Development Environment on amd.com

Vivado Architecture-Independent Tutorials

IP Integrator Tutorials

Tutorial	Description
Basic MicroBlaze Design	This tutorial demonstrates a basic MicroBlaze design using IP Integrator in UltraScale+. This will showcase some basic IP Integrator features like adding IPs from the IP Catalog, running connection automation, and many more.
Designing with IP Integrator using Block Design Containers	This tutorial demonstrates the use of Block Design Containers through both the Top Down and Bottom Up flow. These flows have been shown through a tcl-based design and an IP Integrator-based design.
Module Referencing in IP Integrator	This tutorial demonstrates the RTL module reference feature, the RTL inference feature, and lastly the new X_MODULE_SPEC feature, which combines the existing X_INTERFACE_INFO and X_INTERFACE_PARAMETER HDL attributes.
Basic Versal Design	This tutorial demonstrates how to create a basic Versal design by configuring the CIPS IP, the hardened DDR Memory Controller (DDRMC) through the NoC IP, and takes you through some other IP Integrator features as well. NOTE: This tutorial is located in the Versal branch of this repository.
Designing with IP Integrator Design with RTL top	This tutorial walks you through the steps of building an IPI design with RTL as top. You will generate the post implementation xsa and run it on the petalinux, and learn how the BD addressing of an RTL top design gets mapped to device tree generated in the petaliux through Xilinx shell archive (xsa).

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