Author : Vaanya Sharma
This is a workshop which is about ASIC design using OPEN source tools.
Day1 – Inception of open-source EDA, OpenLANE and Sky130 PDK
How to talk to computers
SoC design and OpenLANE
Get familiar to open-source EDA tools
Day 2 - Understand importance of good floorplan vs bad floorplan and introduction to library cells
Chip Floor planning considerations
Library Binding and Placement
Cell design and characterization flows
Day 3 - Design and characterize one library cell using Magic Layout tool and ngspice
Labs for CMOS inverter ngspice simulations
Inception of Layout – CMOS fabrication process
Day 4 - Pre-layout timing analysis and importance of good clock tree
Timing modelling using delay tables
Timing analysis with ideal clocks using openSTA
Clock tree synthesis TritonCTS and signal integrity
Timing analysis with real clocks using openSTA
Day 5 - Final steps for RTL2GDS
Routing and design rule check (DRC)
PNR interactive flow tutorial
Acknowledgements
Before starting with the concepts, here are some basic termonologies that will help you understand the after written things the better way:-
1.PACKAGE:- The case which has the chip and is connected to the circuit board. It is kind of a housing in which the chip is placed.
2.WIRE BONDS:- Through which the chip is connected to the package and the outside signals are received by the chip.
3.Pads:- Through which we can send in the signals to the chip or recive the signals from the chip.
4.CORE:- Where all the logic sits. All the AND, NOT gates and the MUXES are placed here.
5.DIE:- It is basically, the size of the entire chip.
6.FOUNDRY:- It is a very critical term for chip design. It is a like a big factory with many large machines. It is where the chip gets manufactured.
7.IPs:- Intellectual Property. It requires some intelligence to be built.
1.MACROs:- They are pure logic based.
You must have seen a circuit board like an arduino.
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The highlighted part of the circuit board is the chip or preferably the package.
For designing such a circuit, we would first need to represent it using a block diagram.
Like this :-
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So, now in the same manner of block diagram based representation; let us go inside the package.......................
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So as you saw that inside the package (the white outline) is kept the chip. And what are those white thread like structures ?? You must be wondering. These are the WIRE BONDS. You can know what is there function at termonologies
The package shown above is a QFN-48 whose size is 7mm by 7mm, and these obviously vary in size and model.
So what if we try to know this package in a more detailed manner. Let us see the insides of a package :-
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As you can see that there are many parts of a package namely PADS, CORE AND DIE.You can know about these terms by looking at the termonologies
Now you know what is a core, lets get deep into it and know what kind of logic sits in the core. So if we take an example of a RISC V processor, let us know what sits in its core.
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It consists of many components such as SoC, SRAM and other couple of components. Other typical packages usually have the same kind of components. Out of these components, some are defined as FOUNDRY IPs and MACROs.
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You can know about these terms by going to termonologies.
To build a chip like this,we need to constantly keep in contact with the foundry using some interface. This interface might be a file that the foundry provides us with
So let us arrive at a very important question. HOW DO APPLICATION SOFTWARES WORK ?
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As you can see in the image that there is a c type program and a layout. For apps to work, we in the same way need to convert the c-type program to the kind of layout shown. Let us see how........
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These application softwares enter into a box called the SYSTEM SOFTWARE, which converts these applications to BINARY FORMAT. This system software has many components namely
OPERATING SYSTEM
COMPILER
ASSEMBLER
First is the job of the OS, whose regular jobs are to handle:-
IO OPERATIONS
ALLOCATION OF MEMORY
LOW LEVEL SYSTEM FUNCTION
The main job apart from the regular jobs of the OS is to convert the app to its respective assembly language program and finally to binary language program, so it can be understood by the hardware. The output of the OS are nothing but small instructions in c, c++ or java format.
These are then taken by the compiler and converted to respective instructions. The syntax of these instructions depend upon the type of hardware.
Example- If, the type of hardware is RISC V, then the instructions will also be RISC V instruction set architecture.
Now next is the job of the assembler.It takes in the output of the compiler that is instructions and converts them to their respective binary format. This binary language is also known as the MACHINE LANGUAGE.
MACHINE LANGUAGE- Its name is very much self-explanatory. It is a language that is understood by machines.
Then the output of this assembler is fed to the hardware, and the required function is performed.
LET US NOW SEE AN EXAMPLE OF AN APPLICATION TO UNDERSTAND THIS BETTER.
STOPWATCH
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NOW IS THERE SOMETHING THAT WE CAN KNOW UPON EXPANDING THE PROCESS ??
Yes!!
The instructions that we got as an output of the compiler act as an ABSTRACT interface between C- program and the hardware. This interface is known as the Instruction set Architecture or The architecture of the computer. It basically represents your hardware.
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Now there is another interface known as the Hardware Description Language.
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As you can see in the image that there are some instructions and the output of the assembler. The instruction is to add x6, x10, x6 and the output of the asssembler has to be in binary so that the hardware or we can say the machine can actually understand what is to be done. So its output will be somewhat like 000000000110010110000001100110011.
NOW! You would require a RTL Description Language that would understand and perform the given specifications. It is known as the implementation of specifications.
After this, it is getting synthesized into netlist. This basically is in form of ANDs, NOTs, FLIP FLOPS and so on.....
Then the physical design implementation of the netlist is done.
(image below as a representation of the above written process)
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SOC DESIGN USING OPENLANE
DIGITAL APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC) DESIGN.
For designing an ASIC design, there are many componenets tht must be presesnt:-
~ RTL IPs
~ EDA TOOLS
~ PDK DATA
"For designing 100% open source digital ASIC Design ......" by this statement it is meant that the RTL, EDA, PDK, all must be opensource.
On the internet, there are many open source RTL Designs like:-
librecores.org
github.com
On the internet, there are many open source EDA Tools like:-
QFlow
OpenLANE
WHAT IS A PDK ??
~ PDK is the short form for Process design Kit.
~ It is the interface between the FAB (Semiconductor Fabrication Plant) and the designers
~ It is a collection of files used to model a fabrication process for the EDA Tools used to design an IC (Integrated Circuit or we can call it a Chip).
~ It contains alot of important information like :-
} Process Design Rules
} Device Models
} Digigtal Standard Cell Libraries
} I/O Libraries
For open source PDK, there is collabration between Google and SkyWater Technology Foundry to provide a 100% open source PDK. the pdk is named as 130 nm Production PDK.
Now that we have all the essential components for ASIC Design.
ASIC DESIGN FLOW
It is a piece of software.
Its main objective is to take ASIC design from Resistor-Transistor Level to GDS-II
format, which is used for final layout.
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The above is the image of the simplified ASIC Design flow.
First major step of ASIC Design Flow is SYNTHESIS. In this RTL is converted to a circuit out of components from the Standard Cell Library (SCL). The Circuit is described in HDL and usually reffered as Gate Level Netlist.
The next step is Floor and Power Planning. Floor Planning has different meaning depending whether we want to implement the whole chip or just the small elements known as MACROS about which you can know in the termonologies.
If we try to know the difference , it would be like:-
CHIP FLOOR PLANNING
Partition the chip die termonologies between different system building blocks and place the I/O pads.
MACRO FLOOR PLANNING
In this Dimensions, Pin Locations and Rows are defined.
POWER PLANNING- To provide power to the every macros and standard cells present in the design.
The next step is PLACEMENT.
For MACROs, we'll place gate level netlist cells on the floor plan rows. Obviously these cells must be placed very close to each other to reduce interconnect delay.
It is done in 2 steps:-
GLOBAL:- Tries to find optimal position for more cells, Such positions are not necessarily leagal. So cells might overlap.
DETAILED:- In this the positions recieved from the global step are minimally altered to be legal.
The next step is CLOCK TREE SYNTHESIS. The CTS is used to create network namely the CLOCK DISTRIBUTION NETWORK WHICH GIVES THE CLOCK TO ALL SEQUENTIAL ELEMENTS.
The next step is ROUTING. SIGNAL ROUTING. Given the placement and fixed metal layers, is required to know the pattern of horizontal and vertical wires to implement the nets. It is done on routing grids for least DRC erreors.
The last step is SIGN-OFF. Basically, it is the step in which verification are done.
Like:- PHYSICAL VERIFICATION -DESIGN CHECKING AND LAYOUT VERSUS SCHEMATIC.
TIMING VERIFICATION- STATIC TIMING ANALYSIS.
OPENLANE
It started as an opensource flow for a true open source tape out experiments.
STRIVE SOC FAMILY
It has many open source SoCs with different features, the list is as follows:-
striVe- SKY130 SCL+ SYNTHESIZED 1KB SRAM.
striVe 2- SKY130 SCL + 1KB OPENRAM BLOCK
striVe 2a- striVe 2 WITH A SINGLE CHIP CORE MODULE
striVe 3- OSUSCL + SYNTHESIZED 1KB SRAM
striVe 5- SKY130 SCL + SYNTHESIZED 1KB SRAM.
striVe 6- striVe 2 WITH DFT.
MAIN GOAL OF OPEN LANE ASIC FLOW- to produce a clean GDS II with no human in the loop or human intervention.
Here the word CLEAN means :-
No LVS violations
No DRC violations
Timing violations (work in progress)
It can be used to harden(to generate GDS II orthe final layout)
It has two modes of operation :-
Autonomous- We configure the flow, push the button. Wait for some time as per the design size. And the GDS II layout is generated.
Interactive- As per the interactive we can run commands and steps one by one. So that we can look at the intermediate result while completing the process. This can be helpful for experimentation.
OpenLANE has the following main folders and their divisions.
DESIGN PREPARATION
To invoke openLANE, use the docker command.Then put the interactive command (./flow.tcl-interactive). % package require openlane 0.9 runs version 0.9 of OpenLANE.
OpenLANE has many design types and the one we'll be using is picorv32a. the command is prep -design picorv32a.
THE NEXT STEP IS TO SYNTHESIZE. YOU CAN DO THIS THROUGH THE COMMAND run_synthesis. It might take a couple of minutes for it to complethe process.
The result after synthesisis:-
THE DFF COUNT IS 1613 AND TOTAL NO. OF CELLS IS 14876.
THE D FLIP-FLOP RATIO = 1613/14876= 0.108429685
After synthesis you can check the reports by going to the shown location below....
First we will be knowing how to know the length and width of the chip die and core.
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This, in the physical design overview flow was first step. So let us look how to get the values oh W and H.
So let us begin with a basic netlist. With two filpflops (lounge and capture) and a basic
combinational logic between them. So it is like two flops and and two gates with connection as shown.
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So for the netlist let us have proper dimensions. The would look something like below......
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basically we depend on the dimensions of the gates and the flops. So in this we donot care about the dimensions of wires but the gates and flops. Obviously wires will be in use in later operations but not when we want to know the dimensions of the chip's die and core.
So let us try giving these standard cells rough dimensions. If we consider their to be length and width to be 1 unit by 1 unit. Area is 1 sq. unit. And let us consider the same dimensions for the flipflops as well. So now let us join four of the components in single plate without the wires. now if we try to calculate the area, it would by 2 by 2 unit and the area will be 4 sq. unit.
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So now we know the rough dimensions of the netlist or we can say that we have found the minimum area that will be covered by the netlist when placed anywhere.
So now let us know the core and the die section of the chip. Here is the image of a silicon wafer and the location of the chip's die and core.
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Now what if we place our logic inside the chip. We have to place it in the core of our chip.
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As your cells cover all the area of the chip, it is known as 100 % utilization. Here comes a term from 100 % utilization that is utilization factor. It is the factor that is equal to the AREA OCCUPIED BY THE NETLIST/TOTAL AREA OF CORE. So if we put in the dimensions here it would be = 4x1 sq. unit/2 unit x 2 unit= 4 sq. unit/ 4 sq. unit. So the utilization factor will 1. The utilization factor being 1 means that the core of the chip is fully occupied and if in any cas we have to add any more cells, it is not possible. If we look at it as a practical scenario, we donot opt for 100% utilization rather we opt for 50-60 % utilization. So the utilization factor should 0.5 or 0.6.
Now there comes another term related to these dimensions which is aspect ratio. If we look at its definition it would be HEIGHT/WIDTH. 2 unit/2 unit = 1. If the aspect ratio is 1, it signifies that the chip is square in shape. If the aspect ratio is some other no. rather than 1, it signifies that it is rectangle in shape.
So the next step is to define the location of preplaced cells. So what exactly are preplaced cells ?? To understand, let us take an example of a combinational logic. The assumption about this logic is that it does some amount of function. It does such a big task that its output is a huge circuit. The output circuit is so huge that it almost consists of 50k-100k gates. The circuit is :-
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There is another way in which we could implement this circuit. That is by dividing it into two parts. If the circuit is of 100k gates, we could divide it into 50k and 50k gate blocks. Its division could be something like this.
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The block 1 and 2 will be implemented separately. After making two blocks (or parts) we need to extend the IO pins.
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Next step, would be black boxing the blocks. Which would be like this :-
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To implement these two separately, we need separate them like below.
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These type of blocks can be given separately to different users and implemented separately but only once. They are being placed only once in a chip. That is why they are known as preplaced cells as they must be placed before routing. So these basically are macros or IPs which are implemented once but used several times.
We need to place them in such a manner that their output pins are on one side and input pins on the other side. And once they are placed their location cannot be moved and they are not touched again.
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And this was how we define the location of preplaced cells. So now next step is to surround them using decoupling capacitors.
Consider the following image.
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Let us consider the piece of circuit to be a part of block A, B or C. Whenever the logic switches, like from 0 to 1; it demands for switching current that is peak current. What actually happens is that there is some capacitance sitting near the gates and the transition of logic from 0 to 1 will make the capacitor require some current so that the capacitor can represent the logic 1. This current will be provided to the circuit by supply voltage. But if the logic is changing from 1 to 0, it is the responsibility of the vss to take that amount of charge from the circuit. This will make all the capacitances to get discharged and these discharged current should be handled very well by the ground line of the power supply.
But in a practical scenario, when the voltage is supplied to the circuit there is a voltage drop. This because of inductance, resistance and capacitance peresent in the wire. The wires have physical dimensions and anything that has a physical dimension will surely have some inductance, resistance and capacitance. This drop is reffered as VDD'. Also there is a issue in this. This is that we need to make sure that this vdd falls in the noise margin region. If it is somewhere in the undefined region, it will be dangerous. That is the problem of having a large physical distance from the power supply and the main circuit.
So if there is a problem, there must be a solution. And the solution to this problem is the use of DECOUPLING CAPACITORS. You can consider them as large capacitors completely filled with charge, the equivalent voltage across the capacitor is same as seen in the voltage supply.
And if we try to understand its exact meaning, it can be understood by its name. That is, it decouples the main circuit and provides the circuit with voltage supply. But how would it solve the problem ?? So if we see our main problem was the voltage drop. It mainly happened because of large physical gap between the supply and the main circuit. Placing our capacitor would reduce that gap.
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Let us consider a problem. Refer to problem image of the previous step. In that we provided it with current using a capacitor. Now let us imagine that circuit as a black box which repeated on a chip multiple times.
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So consider the above image. You can see that the particular macro is being repeated 4 times on the chip. Now if you see, there is a line drawn from the driver to the load. It is specifying that there is a signal being sent from the driver to the load. And our problem question is, we have to make sure that the line maintains the signal so that the load recieves the same shape of the signals.
So first we will provide them all with power supply, something like below......
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Now for the line to retain the same signal i.e 0 to 1 it has to get necessary supply from the power as there is no decoupling capacitor over here to take care of the signal. It is the power supply which has to supply power to this line. Also it is not so feasible to put capacitors all over the circuit. Now if you notice, the power supply is far from the line, so there is always a chance of voltage drop. and vdd at the point near Rdd might be something different from the vdd on the line. Let us see what could be the vdd and the gnd on the line.
We could assume that this is a 16 bit bus. Whenever there is a 1 that means that the capacitor is charged to vdd. If there is 0 it means that the capacitors is getting discharged to gnd.
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As you could see in the image before this one that there was a inverter in the load that was connected to the line. So you can see in the image that the input value is 1110010111000110. So when it would be put by the inverter the output will be fully opposite of the input. It means that the capacitors that were charged to vdd will be discharged to ground and the ones that were discharged wil be charged.
Now since all the discharging will happen at the same time and we have a single ground line for all, there will be several taps at the ground line and this would create a bounce. Due to this bounce the things might get unpredictable and they might get into the undefined region about which we read earlier.
About the charging if we say, that all the charging capacitors will ask for supply at the same time. Due to this there wil be a voltage droop. This is like one tap multiple buckets requiring water at the same time. And the voltage droop will be like shortage of water.
Exactly what is the reason of this problem ??
The main reason is that there is only one power supply. If there would have been multiple sources, this problem wouldn't have occured.
So let me show you how it should have been.
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Before directly moving on to pin placement, let us before take an example.
There are two sections of a circuitry. And also some preplaced cells are their in these two parts of the circuits. It has 4 input pins and 3 output pins till now. And the connections are as follows.
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Now there are more 2 sections of a circuit, almost same to the ones seen earlier. Now we know 2 new input and 2 new output pins. And another preplaced cell, block c.
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So let us now see the whole complete design.
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Now let's try to modify this circuit a bit. Starting with the repitition of Clk1 and Clk2 input pins twice and we could form just 1 pin and join to both the points. And this connectivity information is defined using a language known as VHDL or Verilog language and is called as the netlist.
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So let us put this design in the chip we are trying to design. It would look something like this.
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Now we will do some thing known as Logical Cell Placement Blockage. This would not allow any cell to be placed in the area where the pins have been placed.
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Now let us look at the labs. Till now we have done the labs till the command run_synthesis. So in our design flow the next step is run_floorplan. So we will be in the OpenLANE % prompt.
Now there is another file that contains the dimensions of core and die.
And now if you wish to the see the layout after program, you can visit magic.
Through this we can review the layout of our design. So there are some features that we would need to know for using magic, as below:-
1st - If you want the the layout to fit to your screen, select the layout and click on V.
2nd - If you want to zoom in, left click on mouse then right click and then Z on the keyboard.
Now if youn want to know about any component in the layout window, hover your pointer over it. Press S on your keyboard. And go the tkcon window opened. An while the component is selected type what in the tckon window.
You can also zoom in and look at the details of many components. Also to tell this layout that we call is the floorplan, So it doesnot care about the placement of standard cells.
To know what this step means let us have a look at the netlist we took earlier.
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Now you must have seen the specific shapes of the gates. Like the NOT gate has a triangle which as a bubble at the tip. So basically these shapes represent the functionality of the gate. But in our physical world these gates are in shape of a box either square or rectangle. And perform the function the gate they are supposed to perform. Now you can consider these cells as some books on a shelf. this shelf has many kind of these books and is known as a library. This library along with the cells has many kinds of information about them like - timing info, dimensions and the conditions for them to omit an output. It also has the same cell in various sizes. The bigger the size, the less the resistance, the faster the cell.
So what are the components that we have all ready. A well defined flooor plan, A netlist and a physical view of logic gates.
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Now. We won't be using the shapes of the gates from the netlist but the connections. And the shapes we will be taking from the physical view of logic gates. Now on our floor plan there are some preplaced cells, that were placed during the floor planning step. In this step we need to make sure that automated router does not effect or move these cells and no components are placed on the area where these cells are placed.
How do we place these cells?? We have to place in such a manner that they are almost as in the circuit. Like in the circuit the FF 1 in the 1st section is near the Din 1, in the floor plan it should be in the same way. This would reduce the large physical gap, which can lead to delay.
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So now there is a thing that is to be noticed:-
As the blue section input pin is Din3 and output pin is Dout3, then how will we place it as both pins are way far from each other...? And same is the problem for the green section....
So let us first see how will be the blue section placed.
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Now still we can see that there is a large gap between the input pin and the output pin. We will look at that problem after placing the green section. If you would have noticed that even the distance from the Din 4 to Dout 4 is still large, these two are the pins of section 4 green.So its placement would look something like below.
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Let us now arrive at our problems. The only answer to our problem is optimize placement.
So first we will make some estimations. The estimations we are going to make will be about the capacitances even before the wiring or we can say routing. But how would it make a difference ??
So in actual there is a wire from one point to another. Like from Din2 to yellow FF1. So if we look at the area of the wire from the Din2 and FF1(yellow) it is pretty large. So the capacitance and resistance will also be more.
If we see it would be like two people, one standing at the point Din 2 and one at the flipflop. So if the person at Din2 shouts it would be very much difficult for the person to hear as the distance is huge. So this problem can be solved by placing two people in between so that they hear the other person clearly and pass on the message. This is known as signal integrity. Here comes the task of repeaters. These repeaters are basically buffers, they will recondition your signal make a new signal that replicates your signal and send it again.
But again there comes a problem, which is that these repeaters will occupy more n more space on the floorplan.
Now turn by turn we will seeing where there is a need of a repeater.
First let us look at the orange section. Here if we see, all the components have decent distance in between. So hee the signal integrity can be maintained without any use of repeaters.
Now let us move onto the yellow section. In this case the distance between FF1 and Din2 is pretty large, so here some repeaters should be placed to maintain the integrity.
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Here comes the turn of blue section of circuit. First if we see the distance between Din3 and FF1, it is feasible here for the signals to pass without any repeaters. The same is the case, with the distances between FF1 and gate 1, and gate 1 and gate 2.But the distance between gate 2 and FF2 is bit longer. So we need to place a buffer in this area. Next is the distance between FF2 and Dout3, which can let signals pass without repeaters.
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Green section now. First if we see the distance between Din4 and FF1, it is not feasible here for the signals to pass without any repeaters, so we will place a repeater here.
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Now as you can see, the line we have drawn for the placement of the repeater passes through the preplaced cells. It is (as we discussed earlier) a area where we are not supposed to put any component. So we will place a buffer above the area already occupied. Now if we look at the distance betwen FF1 and gate 1, the distance is decent but there is a kind of criss cross as the wire of the connection blue Buff and Blue FF2 are also going the same way. And this is completely okay and how to fix this, we will be seeing ahead. If I tryna explain it simply,it is like that there are different layers. And if there are some overlapping wires, we can print them in different layer. So now the gate 1 and gate 2. The distance between them is pretty large and there is a cell in between and as I told earlier it was completely normal. So yeah we would place a buffer in between. And the distances between gate 2 to FF2 and FF2 to Dout4 is pretty feasible to cover without repeaters.
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Lab lesson 5-
So till now we have done till the process of floorplanning. Now our next step is placement. For the command will run_placement.
For checking onto your placement, go to maic with the following directory.
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The above chip is placed and routed. If you take up any cell like a buffer, gate or a flipflop it would be known as STANDARD CELL. This term is an essential one.
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These all standard cells are placed into a section known as Library. Also here the macros, The IPs and the DECAPs are kept in this library. This library is also discussed earlier.
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Now, if you take any gate, like inverter only. We might consider it as a only a single input gate. But for a IC design, it has got something else to do with it. This simple cell has to go through a great design flow.
This process has got 3 major steps :- Inputs, Design steps and Outputs.
Inputs- These are the inputs that we need to create this cell.
PDKs consisting of DRC & LVS rules, SPICE models, library and user-defined specs.
Design Steps- designing stage.
Circuit design, layout design, characterization.
Outputs- The outputs actually used by the EDA tools.
CDL (circuit description language), GDSII, LEF, extracted spice netlist (.cir), timing, noise, power .libs, function.
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We have the following things from the 3 steps we about which read you earlier :-
Layout, description, spice extracted netlist, inverter sub circuit.
Let us now using these things follow the characterization flow.
1st step - Read the model file. 2nd step - Read the extracted spice netlist file. 3rd step - Define or recognise the behaviour of the buffer. 4th step - Read the sub circuit file. 5th step - Attach the necessary power supplies. 6th step - Apply the stimulus. 7th step - Provide the necessary output capacitances. 8th step - Provide the necessary simulation command
The last step is to provide all this data to a software namely GUNA in form of a configuration.
Using guna, we can classify characterization into mainly 3 types:-
>Timing
>Power
>Noise
Now we will doing some spice simulations on some MOSFETS. But first we need to create a spice deck. A spice deck is a connectivity information of a netlist. So we need to create for PMOS And NMOS as well. We need to define the following things for creating this spice deck.....
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The connectivity information of PMOS.
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The connectivity information of NMOS.
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The connectivity information of CLOAD(capacitor load).
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The connectivity information of VDD.
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Now we will git clone a repository which has the .magic file. The github repository github repository
Then gitclone the repository link through:-
Now after copying go to openlane directory in terminal........
Put git clone command and then paste the URL.
This will create a folder of the same name as the repository.
Now lets look at what is there inside this..
Now if you look at the repository and the terminal, they have the same files.
Now we will go to magic with our cloned file.
16 MASK CMOS PROCESS
- Selecting a Substrate
A substrate is something onto which you fabricate your design. The one we will be choosing will be a p-type. Out of all the qualities of the substrate, we will be mainly focusing on resistivity and doping level. The main focus for our doping level will be that the Substrate doping should be less than well doping.
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- Creating active region for transistors.
These are the regions where actually you see the pmos and nmos transistors. So basically we will be creating some bucket kind of in the substrate, where we will create pmos and nmos. First we will create some isolation between the pockets so they don't interfere in eachother's working. So for this you can deposit layers. First, a 40 nm SiO 2. Then, 80 nm Si3N4 and a 1um photoresist.
There is a term Mask. The layout particularly in the fabrication term is known as mask. The layouts that we see in custom design are converted to these masks.
Now the areas where we donot want any chemical reactions to happen, we will place the masks over there. Then we will the expose the areas not covered to UV light. Then we will wash or remove the area which was not covered.
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Then you remove this mask layer. Now if you do any reactions or depositions, the area under the photoresist won't be effected.
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Now we will also remove the layer of 80 nm Si3N4 that was exposed to UV light and the photoresist as well. The remaining layer of Si3N4 will also act as a good layer of protection as well.
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When we will put this substrate in a very hi temperature furnace, the area of SiO 2 that is not covered by Si3N4 will grow and the area that was covered won't grow. Let us see how. So first we need to place this in an oxidation furnace. It looks something like this.....
SOURCE OF THE IMAGE- THE WEB PAGE OF IIT KANPUR.
THE LINK- (https://www.iitk.ac.in/dordold/index.php?option=com_content&view=category&layout=blog&id=186&Itemid=205#:~:text=Oxidation%20Furnace&text=Thermal%20oxidation%20is%20a%20simple,filler%20material%20in%20gaps%20etc).
THIS WOULD NOW LOOK SOMETHING LIKE BELOW.........
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The grown part is referred to field oxide or the bird's beak. And the process is known as "LOCOS"(Local Oxidation of Silicon.).
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Si3N4 will be stripped using hot phosphoric acid.
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Now, let me define the regions. The well kind of regions that were protected regions are the active regions. And the grown part is the isolated region, which won't allow one transistor to interfere in other transistor's working.
- Creating N-well and P-well.
Now the N-well will be used for the fabrication of PMOS transistors and the P-well will be used for NMOS transistors. In this also, one area needs to be protected as both the wells cannot be formed at the same time. The process to be followed now is pretty similar to the one followed earlier. First put a layer of photoresist, and then the mask upon the area you want to protect. Expose to UV light. Wash off the exposed area. Remove the mask. And now for making a P-well in the exposed area, we will use Boron. Boron is a P-type substance. To diffuse Boron into the well, we would use the process namely Ion implant.
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You follow the same steps for N-well as well. But in place of Boron you use Phosphurous as it is an N-type substance.
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These wells are also known as the twin tubs. Now we need to diffuse the well, so that it covers almost half of the substrate. This will decide the depth of the wells. So for this we will be putting this into a high temperature furnace.
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- Formation of Gate
Gate as we see now, is the most important termianl of the transistors beacause you control the threshold voltage(turning on voltage of the transistor) from here. So the fabrication of gate terminal becomes really important.
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So, we need to control the oxide capacitance and doping concentration.
First let us control doping capacitance. Now, we will follow the same steps as before. Now we will be using the mask4, and as the name suggests for this CMOS process we will be using total of 16 masks. And for this we will be using boron but with lesser force. We will maintain the dose of boron in such a manner, so that we have the required doping concentration. And this doping concentration depends upon the threshold voltage seen in the above images.
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Now using mask 5 we will be following same process for NMOS but again using phosphorous or we can also use arsenic.
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As we have been implementing many layers an P & N type substances, So our oxide is being damaged multiple times. So we will repair this layer.
First we etch the original damaged oxide layer using dilute hydrofluoric solution. Then we regrow this layer to give high quality oxide.
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Now we will deposit a layer of 0.4 um polysilicon layer.
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Then we ion implant any N-type substance either phosphurous or arsenic for low gate resistence.
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Now using photoresist and mask 6, we will make something like below.
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Now we can remove the mask and etch away the polysilicon layer that was not covered by photoresist. And then remove the photoresist layer.
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- Lightly Doped Drain formation
We need to create LDD of two types, P- and N-. First we will put a layer of photoresist then mask7 and expose the other side to UV light. Then remove the mask. And as firstly we have exposed the P well to UV light. So we tend to make a NMOS there. So we would use phosphorous for ion implant. So for this we will be choosing the force and the dosage very carefully, so the n- implant does not penetrate fully into the well and hovers at the top.
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But why is it n- and not n+ ?? It is so, because if p or n type has "-" as after them, it means it is lightly doped.
Same process for PMOS. But with Boron.
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Now somehow we have to protect the implants so in the further processes nothing gets into them. So we will put some spacers over there. So first deposit a thick layer of either SiO 2 or Si3N4. So we will do Plasma anisotropic etching. In this all of the layer is etched but the substance near the side walls remains.
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- Source and Drain formation.
Now add a thin layer of screen oxide. The purpose of adding it is to avoid the effect of channeling. The effect of channeling is when we do alot of ion implant and when the vector velocity of the crystaline structure of our P substrate matches with the velocity of the ions. When this happens, the ions might go deep into the substrate without even hitting any of the silicon atoms.
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Now again thesame process. Photoresistor, Mask 9, other side's exposure to UV light, Ion implant of arsenic.
Same for the otherside. Ion implant with Boron.
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Now we will do High Temperature Annealinng.
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- Steps to form contacts and interconnects(local)
So contacts are really important because, that is the only thing that is accessible to an user. It is a medium through which you can control the electrical characteristics of your transistors.
So to start with, we will first etch the thin oxide layer that we had put in the earlier steps. Then, deposit titanium on wafer surface, using sputtering. But what is sputtering?? It is a process in which we take the metal, which in this example is titanium and hit argon gas at it. And this will make the atoms of the titanium sputter and enter into the substrate.
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Apart from the above result for the N2 being an ambient there is another result. That is TiN that is used only for local comunication.
So now, If you look at the previous image you will able to see a dark blue layer which is in the area where there are no thick layers. That layer is TiSi2. And the light blue layer above every structure is TiN.
Now we need to decide which contacts to bring to the next level. As some connections can be made internally and there is no need of taking them above.
Now we will put the layers of photoresist and mask 11 on the areas which we want to reach above.
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Then remove the mask and etch off the extra TiN using RCA cleaning. RCA cleaning is done a solution known as RCA only. Its solutes vary from use to use. In this it would consist of:-
1. De-ionized water (H2O), 5 parts
2. Ammonium hydroxide (NH4OH), 1 part
3. Hydrogen peroxide (H2O2O), 1 part
It would look ssomething like below-
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Now we remove the photoresist layer.
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- Higher level metal formation.
Now if we see surface topogaraphy of this state of the substrate is not suitable for further ados.
So for this we will deposit a thick layer of SiO 2. And this is a specific SiO 2 doped with phosphorous or boron (known as phosphosiicate glass or borophosphosilicate glass) depsited on wafer surface.
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Now, we will use the Chemical Mechanical Polishing technique for planarizing wafer surface.
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Now we will follow some more processes and form the below kind of substrate.
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Labs -
So this is the layout for our inverter that we got in the previous labs. In this are two transistors PMOS and NMOS.
And the red line is polysilicon. In the repository mentioned, the steps of making an inverter from scratch are also given.
As of now, we have done till placement in the flow and extracted a spice file given a .magic file. Now if we see into the amgic layout, it has many kinds of information, but we donot need that file for routing purpose. We need the info inside that layout. And this is where the .lef file comes in picture. This lef file contains all the info. So our first task will be the extraction of lef file. But beforehand we should know some guidelines---
1st- Always put input and output ports on the intersection of the vertical and the horrizontal tracks.
2nd - The width of the standard cell must be in the odd multiples of the track pitch and the height in the odd multiples of the vertical track pitch.