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jdoerfertjdoerfert
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[OpenMP] Add NVIDIA annotations for static grid thread limit
We already add AMD GPU annotations, the NVIDIA ones are just a little more convoluted to add/update but otherwise the same. We see again that the interplay of ompx_attribute and deduced value needs to be improved, see the TODO. Differential Revision: https://reviews.llvm.org/D158383
1 parent 7481b46 commit f3958ce

9 files changed

+1775
-1709
lines changed

‎clang/test/OpenMP/distribute_simd_codegen.cpp‎

Lines changed: 444 additions & 444 deletions
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‎clang/test/OpenMP/target_ompx_dyn_cgroup_mem_codegen.cpp‎

Lines changed: 44 additions & 44 deletions
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‎clang/test/OpenMP/target_teams_codegen.cpp‎

Lines changed: 36 additions & 36 deletions
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‎clang/test/OpenMP/target_teams_distribute_codegen.cpp‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -935,7 +935,7 @@ int bar(int n){
935935
//
936936
//
937937
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
938-
// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR7:[0-9]+]] {
938+
// CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {
939939
// CHECK1-NEXT: entry:
940940
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
941941
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
@@ -1015,7 +1015,7 @@ int bar(int n){
10151015
//
10161016
//
10171017
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
1018-
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR7]] {
1018+
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
10191019
// CHECK1-NEXT: entry:
10201020
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
10211021
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
@@ -1106,7 +1106,7 @@ int bar(int n){
11061106
//
11071107
//
11081108
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
1109-
// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR7]] {
1109+
// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
11101110
// CHECK1-NEXT: entry:
11111111
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
11121112
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
@@ -1665,7 +1665,7 @@ int bar(int n){
16651665
//
16661666
//
16671667
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
1668-
// CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR7]] {
1668+
// CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
16691669
// CHECK1-NEXT: entry:
16701670
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
16711671
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
@@ -1778,7 +1778,7 @@ int bar(int n){
17781778
//
17791779
//
17801780
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
1781-
// CHECK1-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR7]] {
1781+
// CHECK1-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
17821782
// CHECK1-NEXT: entry:
17831783
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
17841784
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
@@ -1932,7 +1932,7 @@ int bar(int n){
19321932
//
19331933
//
19341934
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
1935-
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR7]] {
1935+
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
19361936
// CHECK1-NEXT: entry:
19371937
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
19381938
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
@@ -2680,7 +2680,7 @@ int bar(int n){
26802680
//
26812681
//
26822682
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
2683-
// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR7:[0-9]+]] {
2683+
// CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {
26842684
// CHECK3-NEXT: entry:
26852685
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
26862686
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
@@ -2760,7 +2760,7 @@ int bar(int n){
27602760
//
27612761
//
27622762
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
2763-
// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR7]] {
2763+
// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
27642764
// CHECK3-NEXT: entry:
27652765
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
27662766
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
@@ -2851,7 +2851,7 @@ int bar(int n){
28512851
//
28522852
//
28532853
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
2854-
// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR7]] {
2854+
// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
28552855
// CHECK3-NEXT: entry:
28562856
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
28572857
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
@@ -3410,7 +3410,7 @@ int bar(int n){
34103410
//
34113411
//
34123412
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
3413-
// CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR7]] {
3413+
// CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
34143414
// CHECK3-NEXT: entry:
34153415
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
34163416
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
@@ -3523,7 +3523,7 @@ int bar(int n){
35233523
//
35243524
//
35253525
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
3526-
// CHECK3-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR7]] {
3526+
// CHECK3-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
35273527
// CHECK3-NEXT: entry:
35283528
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
35293529
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
@@ -3677,7 +3677,7 @@ int bar(int n){
36773677
//
36783678
//
36793679
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
3680-
// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR7]] {
3680+
// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
36813681
// CHECK3-NEXT: entry:
36823682
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
36833683
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
@@ -3868,7 +3868,7 @@ int bar(int n){
38683868
//
38693869
//
38703870
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
3871-
// CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2:[0-9]+]] {
3871+
// CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] {
38723872
// CHECK9-NEXT: entry:
38733873
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
38743874
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
@@ -3948,7 +3948,7 @@ int bar(int n){
39483948
//
39493949
//
39503950
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
3951-
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
3951+
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
39523952
// CHECK9-NEXT: entry:
39533953
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
39543954
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
@@ -4039,7 +4039,7 @@ int bar(int n){
40394039
//
40404040
//
40414041
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
4042-
// CHECK9-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
4042+
// CHECK9-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
40434043
// CHECK9-NEXT: entry:
40444044
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
40454045
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
@@ -4224,7 +4224,7 @@ int bar(int n){
42244224
//
42254225
//
42264226
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
4227-
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
4227+
// CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
42284228
// CHECK9-NEXT: entry:
42294229
// CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
42304230
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
@@ -4378,7 +4378,7 @@ int bar(int n){
43784378
//
43794379
//
43804380
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
4381-
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
4381+
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
43824382
// CHECK9-NEXT: entry:
43834383
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
43844384
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
@@ -4491,7 +4491,7 @@ int bar(int n){
44914491
//
44924492
//
44934493
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
4494-
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
4494+
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
44954495
// CHECK9-NEXT: entry:
44964496
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
44974497
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
@@ -4675,7 +4675,7 @@ int bar(int n){
46754675
//
46764676
//
46774677
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
4678-
// CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2:[0-9]+]] {
4678+
// CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] {
46794679
// CHECK11-NEXT: entry:
46804680
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
46814681
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
@@ -4755,7 +4755,7 @@ int bar(int n){
47554755
//
47564756
//
47574757
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
4758-
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
4758+
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
47594759
// CHECK11-NEXT: entry:
47604760
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
47614761
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
@@ -4846,7 +4846,7 @@ int bar(int n){
48464846
//
48474847
//
48484848
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
4849-
// CHECK11-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
4849+
// CHECK11-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
48504850
// CHECK11-NEXT: entry:
48514851
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
48524852
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
@@ -5031,7 +5031,7 @@ int bar(int n){
50315031
//
50325032
//
50335033
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
5034-
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5034+
// CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
50355035
// CHECK11-NEXT: entry:
50365036
// CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
50375037
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
@@ -5185,7 +5185,7 @@ int bar(int n){
51855185
//
51865186
//
51875187
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
5188-
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
5188+
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
51895189
// CHECK11-NEXT: entry:
51905190
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
51915191
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
@@ -5298,7 +5298,7 @@ int bar(int n){
52985298
//
52995299
//
53005300
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
5301-
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5301+
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
53025302
// CHECK11-NEXT: entry:
53035303
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
53045304
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4

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