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Weixing Shizeddii
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malta uhci quirks: make allowance for slow 4k(e)c
This works around an unexpected IRQ torvalds#255 seen during initial USB host mass storage device initialization and access. * wait up to 50us for HCRESET to clear, a slow 4kc needs a longer time. * leave FSBR enabled so that a slow 4kec/24kec will not be overwhelmed. Signed-off-by: <[email protected]> Weixing Shi Signed-off-by: <[email protected]> Bruce Ashfield
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drivers/usb/host/pci-quirks.c

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -637,6 +637,9 @@ EXPORT_SYMBOL_GPL(usb_amd_pt_check_port);
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*/
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void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
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{
640+
#ifdef CONFIG_MIPS_MALTA
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int timeout = 10;
642+
#endif
640643
/* Turn off PIRQ enable and SMI enable. (This also turns off the
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* BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
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*/
@@ -650,9 +653,16 @@ void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
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outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
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mb();
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udelay(5);
653-
if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
654-
dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
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657+
#ifdef CONFIG_MIPS_MALTA
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while (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) {
659+
if (--timeout < 0) {
660+
dev_warn(&pdev->dev, "HCRESET timed out!\n");
661+
break;
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}
663+
udelay(5);
664+
}
665+
#endif
656666
/* Just to be safe, disable interrupt requests and
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* make sure the controller is stopped.
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*/

drivers/usb/host/uhci-q.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,9 @@ static void uhci_fsbr_off(struct uhci_hcd *uhci)
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static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb)
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{
7474
struct urb_priv *urbp = urb->hcpriv;
75-
75+
#ifdef CONFIG_MIPS_MALTA
76+
return;
77+
#endif
7678
urbp->fsbr = 1;
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}
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