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26 | 26 |
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27 | 27 | #include "irq_arch.h" |
28 | 28 | #include "esp_attr.h" |
29 | | -#include "hal/interrupt_controller_types.h" |
30 | | -#include "hal/interrupt_controller_ll.h" |
| 29 | +#include "esp_cpu.h" |
31 | 30 | #include "hal/usb_serial_jtag_ll.h" |
32 | 31 | #include "soc/periph_defs.h" |
33 | 32 | #include "rom/ets_sys.h" |
34 | 33 |
|
| 34 | +#define USB_SERIAL_JTAG_PACKET_SZ_BYTES 64 |
| 35 | + |
35 | 36 | static tsrb_t serial_tx_rb; |
36 | 37 | static uint8_t serial_tx_rb_buf[USB_SERIAL_JTAG_PACKET_SZ_BYTES]; |
37 | 38 |
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@@ -98,18 +99,18 @@ static void _init(void) |
98 | 99 | intr_matrix_set(PRO_CPU_NUM, ETS_USB_SERIAL_JTAG_INTR_SOURCE, CPU_INUM_SERIAL_JTAG); |
99 | 100 |
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100 | 101 | /* enable the CPU interrupt */ |
101 | | - intr_cntrl_ll_set_int_handler(CPU_INUM_SERIAL_JTAG, _serial_intr_handler, NULL); |
102 | | - intr_cntrl_ll_enable_interrupts(BIT(CPU_INUM_SERIAL_JTAG)); |
| 102 | + esp_cpu_intr_set_handler(CPU_INUM_SERIAL_JTAG, _serial_intr_handler, NULL); |
| 103 | + esp_cpu_intr_enable(BIT(CPU_INUM_SERIAL_JTAG)); |
103 | 104 |
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104 | 105 | #ifdef SOC_CPU_HAS_FLEXIBLE_INTC |
105 | 106 | /* set interrupt level */ |
106 | | - intr_cntrl_ll_set_int_level(CPU_INUM_SERIAL_JTAG, 1); |
| 107 | + esp_cpu_intr_set_priority(CPU_INUM_SERIAL_JTAG, 1); |
107 | 108 | #endif |
108 | 109 | } |
109 | 110 |
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110 | 111 | static void _detach(void) |
111 | 112 | { |
112 | | - intr_cntrl_ll_disable_interrupts(BIT(CPU_INUM_SERIAL_JTAG)); |
| 113 | + esp_cpu_intr_disable(BIT(CPU_INUM_SERIAL_JTAG)); |
113 | 114 | } |
114 | 115 |
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115 | 116 | STDIO_PROVIDER(STDIO_ESP32_SERIAL_JTAG, _init, _detach, _write) |
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