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cpu/esp32/periph/uart: migration to ESP-IDF v5.4
1 parent 5a378ed commit 6083a01

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+40
-9
lines changed

2 files changed

+40
-9
lines changed

cpu/esp32/include/periph_cpu.h

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -986,6 +986,38 @@ typedef struct {
986986
gpio_t rxd; /**< GPIO used as RxD pin */
987987
} uart_conf_t;
988988

989+
#ifndef DOXYGEN
990+
/**
991+
* @brief Override UART stop bits
992+
*/
993+
typedef enum {
994+
UART_STOP_BITS_1 = 0x1, /*!< stop bit: 1bit*/
995+
UART_STOP_BITS_1_5 = 0x2, /*!< stop bit: 1.5bits*/
996+
UART_STOP_BITS_2 = 0x3, /*!< stop bit: 2bits*/
997+
} uart_stop_bits_t;
998+
999+
#define HAVE_UART_STOP_BITS_T
1000+
1001+
/**
1002+
* @brief Marker for unsupported UART parity modes
1003+
*/
1004+
#define UART_MODE_UNSUPPORTED 0xf0
1005+
1006+
/**
1007+
* @brief Override UART parity values
1008+
*/
1009+
typedef enum {
1010+
UART_PARITY_NONE = 0x0,
1011+
UART_PARITY_EVEN = 0x2,
1012+
UART_PARITY_ODD = 0x3,
1013+
UART_PARITY_MARK = UART_MODE_UNSUPPORTED | 0,
1014+
UART_PARITY_SPACE = UART_MODE_UNSUPPORTED | 1,
1015+
} uart_parity_t;
1016+
1017+
#define HAVE_UART_PARITY_T
1018+
1019+
#endif /* !DOXYGEN */
1020+
9891021
/**
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* @brief Maximum number of UART interfaces
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*/

cpu/esp_common/periph/uart.c

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -59,11 +59,10 @@
5959

6060
#else /* defined(CPU_ESP8266) */
6161

62-
#include "driver/periph_ctrl.h"
62+
#include "esp_cpu.h"
63+
#include "esp_idf_api/uart.h"
64+
#include "esp_private/periph_ctrl.h"
6365
#include "esp_rom_gpio.h"
64-
#include "esp_rom_uart.h"
65-
#include "hal/interrupt_controller_types.h"
66-
#include "hal/interrupt_controller_ll.h"
6766
#include "soc/gpio_reg.h"
6867
#include "soc/gpio_sig_map.h"
6968
#include "soc/gpio_struct.h"
@@ -189,7 +188,7 @@ int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
189188
gpio_set_pin_usage(uart_config[uart].txd, _UART);
190189
gpio_set_pin_usage(uart_config[uart].rxd, _UART);
191190

192-
esp_rom_uart_tx_wait_idle(uart);
191+
esp_idf_esp_rom_output_tx_wait_idle(uart);
193192
esp_rom_gpio_connect_out_signal(uart_config[uart].txd,
194193
_uarts[uart].signal_txd, false, false);
195194
esp_rom_gpio_connect_in_signal(uart_config[uart].rxd,
@@ -276,7 +275,7 @@ void uart_print_config(void)
276275

277276
static void IRAM _uart_intr_handler(void *arg)
278277
{
279-
/* to satisfy the compiler */
278+
/* to satisfy the compiler */
280279
(void)arg;
281280

282281
irq_isr_enter();
@@ -416,11 +415,11 @@ static void _uart_config(uart_t uart)
416415
/* route all UART interrupt sources to same the CPU interrupt */
417416
intr_matrix_set(PRO_CPU_NUM, _uarts[uart].int_src, CPU_INUM_UART);
418417
/* we have to enable therefore the CPU interrupt here */
419-
intr_cntrl_ll_set_int_handler(CPU_INUM_UART, _uart_intr_handler, NULL);
420-
intr_cntrl_ll_enable_interrupts(BIT(CPU_INUM_UART));
418+
esp_cpu_intr_set_handler(CPU_INUM_UART, _uart_intr_handler, NULL);
419+
esp_cpu_intr_enable(BIT(CPU_INUM_UART));
421420
#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
422421
/* set interrupt level */
423-
intr_cntrl_ll_set_int_level(CPU_INUM_UART, 1);
422+
esp_cpu_intr_set_priority(CPU_INUM_UART, 1);
424423
#endif
425424
#endif /* CPU_ESP8266 */
426425
}

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