cpu/esp32: changes for RTOS SDK

Author: gschorcht

cpu/esp32/exceptions.c

@@ -205,3 +205,10 @@ void IRAM NORETURN panic_arch(void)
 
     UNREACHABLE();
 }
+
+void _panic_handler(uint32_t addr)
+{
+    ets_printf("#! _xt_panic called from 0x%08x: powering off\n", addr);
+    pm_off();
+    while (1) { };
+}

cpu/esp32/include/periph_cpu.h

@@ -325,6 +325,11 @@ typedef struct {
     gpio_t sda;             /**< GPIO used as SDA pin */
 } i2c_conf_t;
 
+/**
+ * @brief   Maximum number of I2C interfaces that can be used by board definitions
+ */
+#define I2C_NUMOF_MAX   (2)
+
 #define PERIPH_I2C_NEED_READ_REG    /**< i2c_read_reg required */
 #define PERIPH_I2C_NEED_READ_REGS   /**< i2c_read_regs required */
 #define PERIPH_I2C_NEED_WRITE_REG   /**< i2c_write_reg required */
@@ -333,7 +338,6 @@ typedef struct {
 
 /**
  * @name   PWM configuration
- * @{
  *
  * PWM implementation uses ESP32's high-speed MCPWM modules. ESP32 has 2 such
  * modules, each with up to 6 channels (PWM_CHANNEL_NUM_DEV_MAX). Thus, the
@@ -355,6 +359,8 @@ typedef struct {
  * @note As long as the GPIOs listed in PWM0_GPIOS and PMW1_GPIOS are not
  * initialized as PWM channels with the *pwm_init* function, they can be used
  * other purposes.
+ *
+ * @{
  */
 
 /**
@@ -402,6 +408,8 @@ typedef struct {
  *
  * SPI_NUMOF is determined automatically from the board-specific peripheral
  * definitions of SPIn_*.
+ *
+ * @{
  */
 
 /**
@@ -423,6 +431,11 @@ typedef struct {
     gpio_t cs;              /**< GPIO used as CS0 pin */
 } spi_conf_t;
 
+/**
+ * @brief   Maximum number of SPI interfaces that can be used by board definitions
+ */
+#define SPI_NUMOF_MAX   2
+
 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE  /**< requires function spi_transfer_byte */
 #define PERIPH_SPI_NEEDS_TRANSFER_REG   /**< requires function spi_transfer_reg */
 #define PERIPH_SPI_NEEDS_TRANSFER_REGS  /**< requires function spi_transfer_regs */