merge: 'upstream' into pst-v4.3.99 zephyrproject-rtos#8

Author: ndrs-pst

MAINTAINERS.yml

@@ -3476,7 +3476,7 @@ NVMEM:
   collaborators:
     - henrikbrixandersen
   files:
-    - doc/services/nvmem/
+    - doc/services/storage/nvmem/
     - dts/bindings/nvmem/
     - include/zephyr/devicetree/nvmem.h
     - include/zephyr/nvmem.h
@@ -4586,7 +4586,7 @@ Retention:
     - dts/bindings/retention/
     - include/zephyr/retention/
     - subsys/retention/
-    - doc/services/retention/
+    - doc/services/storage/retention/
   labels:
     - "area: Retention"
 

arch/arm/include/cortex_m/dwt.h

@@ -82,7 +82,7 @@ static inline void dwt_access(bool ena)
 static inline int z_arm_dwt_init(void)
 {
 	/* Enable tracing */
-	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+	DCB->DEMCR |= DCB_DEMCR_TRCENA_Msk;
 
 	/* Unlock DWT access if any */
 	dwt_access(true);
@@ -149,7 +149,7 @@ static inline void z_arm_dwt_enable_debug_monitor(void)
 	 * unpredictable if the DebugMonitor exception is triggered. We
 	 * assert that the CPU is in normal mode.
 	 */
-	__ASSERT((CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) == 0,
+	__ASSERT((DCB->DHCSR & DCB_DHCSR_C_DEBUGEN_Msk) == 0,
 		 "Cannot enable DBM when CPU is in Debug mode\n");
 
 #if defined(CONFIG_ARMV8_M_SE) && !defined(CONFIG_ARM_NONSECURE_FIRMWARE)
@@ -160,7 +160,7 @@ static inline void z_arm_dwt_enable_debug_monitor(void)
 	 * when enabling the DebugMonitor exception, assert that
 	 * it is not targeting the Non Secure domain.
 	 */
-	__ASSERT((CoreDebug->DEMCR & DCB_DEMCR_SDME_Msk) != 0, "DebugMonitor targets Non-Secure\n");
+	__ASSERT((DCB->DEMCR & DCB_DEMCR_SDME_Msk) != 0, "DebugMonitor targets Non-Secure\n");
 #endif
 
 	/* The DebugMonitor handler priority is set already
@@ -169,7 +169,7 @@ static inline void z_arm_dwt_enable_debug_monitor(void)
 	 */
 
 	/* Enable debug monitor exception triggered on debug events */
-	CoreDebug->DEMCR |= CoreDebug_DEMCR_MON_EN_Msk;
+	DCB->DEMCR |= DCB_DEMCR_MON_EN_Msk;
 }
 
 #endif /* CONFIG_CORTEX_M_DWT */

arch/xtensa/core/ptables.c

@@ -67,6 +67,13 @@
 /** Construct a page table entry (PTE) */
 #define PTE(paddr, ring, attr) PTE_WITH_BCKUP(paddr, ring, attr, RING_KERNEL, PTE_ATTR_ILLEGAL)
 
+/** Get the Physical Page Number from a PTE */
+#define PTE_PPN_GET(pte) ((pte) & XTENSA_MMU_PTE_PPN_MASK)
+
+/** Set the Physical Page Number in a PTE */
+#define PTE_PPN_SET(pte, ppn)                                                                      \
+	(((pte) & ~XTENSA_MMU_PTE_PPN_MASK) | ((ppn) & XTENSA_MMU_PTE_PPN_MASK))
+
 /** Get the attributes from a PTE */
 #define PTE_ATTR_GET(pte) (((pte) & PTE_ATTR_MASK) >> PTE_ATTR_SHIFT)
 
@@ -388,7 +395,7 @@ static void map_memory_range(const uint32_t start, const uint32_t end,
 				PTE((uint32_t)l2_table, RING_KERNEL, XTENSA_MMU_PAGE_TABLE_ATTR);
 		}
 
-		l2_table = (uint32_t *)(xtensa_kernel_ptables[l1_pos] & XTENSA_MMU_PTE_PPN_MASK);
+		l2_table = (uint32_t *)PTE_PPN_GET(xtensa_kernel_ptables[l1_pos]);
 		l2_table[l2_pos] = pte;
 	}
 }
@@ -552,7 +559,7 @@ static bool l2_page_table_map(uint32_t *l1_table, void *vaddr, uintptr_t phys,
 	}
 #endif
 
-	l2_table = (uint32_t *)(l1_table[l1_pos] & XTENSA_MMU_PTE_PPN_MASK);
+	l2_table = (uint32_t *)PTE_PPN_GET(l1_table[l1_pos]);
 	l2_table[l2_pos] = PTE(phys, is_user ? RING_USER : RING_KERNEL, attrs);
 
 	if (IS_ENABLED(PAGE_TABLE_IS_CACHED)) {
@@ -732,7 +739,7 @@ static void l2_page_table_unmap(uint32_t *l1_table, void *vaddr)
 	dup_l2_table_if_needed(l1_table, l1_pos);
 #endif
 
-	l2_table = (uint32_t *)(l1_table[l1_pos] & XTENSA_MMU_PTE_PPN_MASK);
+	l2_table = (uint32_t *)PTE_PPN_GET(l1_table[l1_pos]);
 
 	if (IS_ENABLED(PAGE_TABLE_IS_CACHED)) {
 		sys_cache_data_invd_range((void *)&l2_table[l2_pos], sizeof(l2_table[0]));
@@ -1072,8 +1079,7 @@ static uint32_t *dup_l1_table(void)
 			uint32_t *l2_table, *src_l2_table;
 			bool l2_need_dup = false;
 
-			src_l2_table = (uint32_t *)(xtensa_kernel_ptables[l1_pos] &
-						    XTENSA_MMU_PTE_PPN_MASK);
+			src_l2_table = (uint32_t *)PTE_PPN_GET(xtensa_kernel_ptables[l1_pos]);
 
 			/* Need to check if the L2 table has been modified between boot and
 			 * this function call. We do not want to inherit any changes in
@@ -1097,7 +1103,7 @@ static uint32_t *dup_l1_table(void)
 				 * duplicate the L2 table.
 				 */
 				vaddr = vaddr_from_pt_pos(l1_pos, l2_pos);
-				if ((src_l2_table[l2_pos] & XTENSA_MMU_PTE_PPN_MASK) != vaddr) {
+				if (PTE_PPN_GET(src_l2_table[l2_pos]) != vaddr) {
 					l2_need_dup = true;
 					break;
 				}
@@ -1129,7 +1135,7 @@ static void dup_l2_table_if_needed(uint32_t *l1_table, uint32_t l1_pos)
 {
 	uint32_t *l2_table, *src_l2_table;
 
-	src_l2_table = (uint32_t *)(l1_table[l1_pos] & XTENSA_MMU_PTE_PPN_MASK);
+	src_l2_table = (uint32_t *)PTE_PPN_GET(l1_table[l1_pos]);
 
 	if (l2_page_tables_counter[l2_table_to_counter_pos(src_l2_table)] == 1) {
 		/* Only one user of L2 table, no need to duplicate. */
@@ -1214,13 +1220,14 @@ static void region_map_update(uint32_t *l1_table, uintptr_t start,
 		dup_l2_table_if_needed(l1_table, l1_pos);
 #endif
 
-		l2_table = (uint32_t *)(l1_table[l1_pos] & XTENSA_MMU_PTE_PPN_MASK);
+		l2_table = (uint32_t *)PTE_PPN_GET(l1_table[l1_pos]);
 
 		if (IS_ENABLED(PAGE_TABLE_IS_CACHED)) {
 			sys_cache_data_invd_range((void *)&l2_table[l2_pos], sizeof(l2_table[0]));
 		}
 
 		pte = l2_table[l2_pos];
+		pte = PTE_PPN_SET(pte, start + offset);
 
 		if ((option & OPTION_RESTORE_ATTRS) == OPTION_RESTORE_ATTRS) {
 			new_attrs = PTE_BCKUP_ATTR_GET(pte);
@@ -1430,7 +1437,7 @@ static bool page_validate(uint32_t *ptables, uint32_t page, uint8_t ring, bool w
 		return false;
 	}
 
-	l2_table = (uint32_t *)(ptables[l1_pos] & XTENSA_MMU_PTE_PPN_MASK);
+	l2_table = (uint32_t *)PTE_PPN_GET(ptables[l1_pos]);
 	pte = l2_table[l2_pos];
 
 	if (is_pte_illegal(pte)) {

boards/arduino/portenta_c33/arduino_portenta_c33.dts

@@ -37,12 +37,12 @@
 		};
 
 		led2: led2 {
-			gpios = <&ioport4 0 GPIO_ACTIVE_HIGH>;
+			gpios = <&ioport4 0 GPIO_ACTIVE_LOW>;
 			label = "LEDG";
 		};
 
 		led3: led3 {
-			gpios = <&ioport8 0 GPIO_ACTIVE_HIGH>;
+			gpios = <&ioport8 0 GPIO_ACTIVE_LOW>;
 			label = "LEDB";
 		};
 	};

boards/arm/mps2/Kconfig

@@ -4,5 +4,6 @@
 
 config BOARD_MPS2
 	select HAS_COVERAGE_SUPPORT
-	select QEMU_TARGET if BOARD_MPS2_AN385 || BOARD_MPS2_AN521_CPU0 || BOARD_MPS2_AN521_CPU0_NS || BOARD_MPS2_AN521_CPU1
+	select QEMU_TARGET if BOARD_MPS2_AN385 || BOARD_MPS2_AN386 || \
+		BOARD_MPS2_AN521_CPU0 || BOARD_MPS2_AN521_CPU0_NS || BOARD_MPS2_AN521_CPU1
 	select TRUSTED_EXECUTION_NONSECURE if BOARD_MPS2_AN521_CPU0_NS

boards/arm/mps2/board.cmake

@@ -15,13 +15,20 @@ elseif(CONFIG_BOARD_MPS2_AN383)
   set(SUPPORTED_EMU_PLATFORMS armfvp)
   set(ARMFVP_BIN_NAME FVP_MPS2_Cortex-M0plus)
   set(ARMFVP_FLAGS
-  -C armcortexm0plusct.NUM_MPU_REGION=8
-  -C armcortexm0plusct.USER=1
-  -C armcortexm0plusct.VTOR=1
-  )
+    -C armcortexm0plusct.NUM_MPU_REGION=8
+    -C armcortexm0plusct.USER=1
+    -C armcortexm0plusct.VTOR=1
+    )
 elseif(CONFIG_BOARD_MPS2_AN386)
-  set(SUPPORTED_EMU_PLATFORMS armfvp)
+  set(SUPPORTED_EMU_PLATFORMS qemu armfvp)
   set(ARMFVP_BIN_NAME FVP_MPS2_Cortex-M4)
+  set(QEMU_CPU_TYPE_${ARCH} cortex-m4)
+  set(QEMU_FLAGS_${ARCH}
+    -cpu ${QEMU_CPU_TYPE_${ARCH}}
+    -machine mps2-an386
+    -nographic
+    -vga none
+    )
 elseif(CONFIG_BOARD_MPS2_AN500)
   set(SUPPORTED_EMU_PLATFORMS armfvp)
   set(ARMFVP_BIN_NAME FVP_MPS2_Cortex-M7)

boards/arm/mps2/mps2_an386.yaml

@@ -3,6 +3,7 @@ name: ARM V2M MPS2-an386
 type: mcu
 arch: arm
 simulation:
+  - name: qemu
   - name: armfvp
     exec: FVP_MPS2_Cortex-M4
 toolchain:

boards/arm/mps2/mps2_an386_defconfig

@@ -5,6 +5,7 @@
 #
 
 CONFIG_RUNTIME_NMI=y
+CONFIG_QEMU_ICOUNT_SHIFT=7
 
 # GPIOs
 CONFIG_GPIO=y

boards/microchip/sam/sam_e54_cult/Kconfig.sam_e54_cult

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_SAM_E54_CULT
+	select SOC_ATSAME54P20A

boards/microchip/sam/sam_e54_cult/board.cmake

@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)