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merge: 'upstream' into pst-v4.3.99 zephyrproject-rtos#62
# Conflicts: # drivers/flash/flash_shell.c # include/zephyr/shell/shell.h # subsys/shell/shell.c
2 parents 4d5d028 + a04d895 commit 9cbf0ff

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arch/riscv/Kconfig.isa

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Original file line numberDiff line numberDiff line change
@@ -237,6 +237,14 @@ config RISCV_ISA_EXT_ZBC
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The Zbc instructions can be used for carry-less multiplication that
238238
is the multiplication in the polynomial ring over GF(2).
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config RISCV_ISA_EXT_ZBKB
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bool
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help
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(Zbkb) - Zbkb BitManip Extension (Bit-manipulation for Cryptography)
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The Zbkb instructions can be used for accelerating cryptography workloads
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and contain rotation, reversion, packing and some advanced bit-manipulation.
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config RISCV_ISA_EXT_ZBS
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bool
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help

boards/native/nrf_bsim/common/cmsis/cmsis.c

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Original file line numberDiff line numberDiff line change
@@ -97,3 +97,156 @@ void __SEV(void)
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{
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nrfbsim_SEV_model();
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}
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/*
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* Implement the following ARM instructions
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*
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* - STR Exclusive(8,16 & 32bit) (__STREX{B,H,W})
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* - LDR Exclusive(8,16 & 32bit) (__LDREX{B,H,W})
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* - CLREX : Exclusive lock removal (__CLREX)
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*
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* Description:
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* From ARMs description it is relatively unclear how the LDREX/STREX/CLREX
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* are really implemented in M4/M33 devices.
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*
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* The current model simply sets a local monitor (local to the processor)
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* exclusive lock for the current MCU when a LDREX is executed.
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* STREX check this lock, and succeeds if set, fails otherwise.
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* The lock is cleared whenever STREX or CLREX are run, or when we return
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* from an interrupt handler.
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* See Arm v8-M Architecture Reference Manual: "B9.2 The local monitors" and
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* "B9.4 Exclusive access instructions and the monitors".
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*
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* The address is ignored, and we do not model a "system/global" monitor.
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* The access width is ignored from the locking point of view.
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* In principle this model would seem to fulfill the functionality described
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* by ARM.
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*
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* Note that as the POSIX arch will not make an embedded
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* thread lose context while just executing its own code, and it does not
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* allow parallel embedded SW threads to execute at the same exact time,
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* there is no real need to protect atomicity.
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* But, some embedded code may use this instructions in between busy waits,
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* and expect that an interrupt in the meanwhile will indeed cause a
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* following STREX to fail.
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*
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* As this ARM exclusive access monitor mechanism can in principle be
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* used for other, unexpected, purposes, this simple replacement may not be
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* enough.
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*/
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static bool ex_lock; /* LDREX/STREX/CLREX lock state */
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bool nrfbsim_STREXlock_model(void)
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{
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if (ex_lock == false) {
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return true;
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}
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ex_lock = false;
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return false;
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}
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void nrfbsim_clear_excl_access(void)
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{
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ex_lock = false;
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}
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/**
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* \brief Pretend to execute a STR Exclusive (8 bit)
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* \details Executes an exclusive STR instruction for 8 bit values.
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* \param [in] value Value to store
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* \param [in] ptr Pointer to location
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* \return 0 Function succeeded
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* \return 1 Function did not succeeded (value not changed)
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*/
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uint32_t __STREXB(uint8_t value, volatile uint8_t *ptr)
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{
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if (nrfbsim_STREXlock_model()) {
166+
return 1;
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}
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*ptr = value;
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return 0;
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}
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/**
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* \brief Pretend to execute a STR Exclusive (16 bit)
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* \details Executes a exclusive STR instruction for 16 bit values.
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* \param [in] value Value to store
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* \param [in] ptr Pointer to location
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* \return 0 Function succeeded
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* \return 1 Function did not succeeded (value not changed)
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*/
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uint32_t __STREXH(uint16_t value, volatile uint16_t *ptr)
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{
182+
if (nrfbsim_STREXlock_model()) {
183+
return 1;
184+
}
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*ptr = value;
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return 0;
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}
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/**
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* \brief Pretend to execute a STR Exclusive (32 bit)
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* \details Executes a exclusive~ STR instruction for 32 bit values.
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* \param [in] value Value to store
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* \param [in] ptr Pointer to location
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* \return 0 Function succeeded
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* \return 1 Function did not succeeded (value not changed)
196+
*/
197+
uint32_t __STREXW(uint32_t value, volatile uint32_t *ptr)
198+
{
199+
if (nrfbsim_STREXlock_model()) {
200+
return 1;
201+
}
202+
*ptr = value;
203+
return 0;
204+
}
205+
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/**
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* \brief Pretend to execute a LDR Exclusive (8 bit)
208+
* \details Executes an exclusive LDR instruction for 8 bit value.
209+
* Meaning, set an exclusive lock, and load the stored value
210+
* \param [in] ptr Pointer to data
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* \return value of type uint8_t at (*ptr)
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*/
213+
uint8_t __LDREXB(volatile uint8_t *ptr)
214+
{
215+
ex_lock = true;
216+
return *ptr;
217+
}
218+
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/**
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* \brief Pretend to execute a LDR Exclusive (16 bit)
221+
* \details Executes an ~exclusive~ LDR instruction for 16 bit value.
222+
* Meaning, set an exclusive lock, and load the stored value
223+
* \param [in] ptr Pointer to data
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* \return value of type uint8_t at (*ptr)
225+
*/
226+
uint16_t __LDREXH(volatile uint16_t *ptr)
227+
{
228+
ex_lock = true;
229+
return *ptr;
230+
}
231+
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/**
233+
* \brief Execute a LDR Exclusive (32 bit)
234+
* \details Executes an exclusive LDR instruction for 32 bit value.
235+
* Meaning, set an exclusive lock, and load the stored value
236+
* \param [in] ptr Pointer to data
237+
* \return value of type uint8_t at (*ptr)
238+
*/
239+
uint32_t __LDREXW(volatile uint32_t *ptr)
240+
{
241+
ex_lock = true;
242+
return *ptr;
243+
}
244+
245+
/**
246+
* \brief Remove the exclusive lock
247+
* \details Removes the exclusive lock which is created by LDREX
248+
*/
249+
void __CLREX(void)
250+
{
251+
ex_lock = false;
252+
}

boards/native/nrf_bsim/common/cmsis/cmsis.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,8 @@ void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
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uint32_t NVIC_GetPriority(IRQn_Type IRQn);
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void NVIC_SystemReset(void);
3838

39+
void nrfbsim_clear_excl_access(void);
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3941
#ifdef __cplusplus
4042
}
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#endif

boards/native/nrf_bsim/common/cmsis/cmsis_instr.h

Lines changed: 7 additions & 110 deletions
Original file line numberDiff line numberDiff line change
@@ -40,116 +40,13 @@ void __WFE(void);
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void __WFI(void);
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void __SEV(void);
4242

43-
/*
44-
* Implement the following ARM intrinsics as non-exclusive accesses
45-
*
46-
* - STR Exclusive(8,16 & 32bit) (__STREX{B,H,W})
47-
* - LDR Exclusive(8,16 & 32bit) (__LDREX{B,H,W})
48-
* - CLREX : Exclusive lock removal (__CLREX) - no-op
49-
*
50-
* Description:
51-
* These accesses always succeed, and do NOT set any kind of internal
52-
* exclusive access flag;
53-
* There is no local/global memory monitors, MPU control of what are
54-
* shareable regions, exclusive reservations granules, automatic clearing
55-
* on context switch, or so.
56-
*
57-
* This should be enough for the expected uses of LDR/STREXB
58-
* (locking mutexes or guarding other atomic operations, inside a few lines
59-
* of code in the same function): As the POSIX arch will not make an embedded
60-
* thread lose context while just executing its own code, and it does not
61-
* allow parallel embedded SW threads to execute at the same exact time,
62-
* there is no actual need to protect atomicity.
63-
*
64-
* But as this ARM exclusive access monitor mechanism can in principle be
65-
* used for other, unexpected, purposes, this simple replacement may not be
66-
* enough.
67-
*/
68-
69-
/**
70-
* \brief Pretend to execute a STR Exclusive (8 bit)
71-
* \details Executes a ~exclusive~ STR instruction for 8 bit values.
72-
* \param [in] value Value to store
73-
* \param [in] ptr Pointer to location
74-
* \return 0 Function succeeded (always)
75-
*/
76-
static inline uint32_t __STREXB(uint8_t value, volatile uint8_t *ptr)
77-
{
78-
*ptr = value;
79-
return 0;
80-
}
81-
82-
/**
83-
* \brief Pretend to execute a STR Exclusive (16 bit)
84-
* \details Executes a ~exclusive~ STR instruction for 16 bit values.
85-
* \param [in] value Value to store
86-
* \param [in] ptr Pointer to location
87-
* \return 0 Function succeeded (always)
88-
*/
89-
static inline uint32_t __STREXH(uint16_t value, volatile uint16_t *ptr)
90-
{
91-
*ptr = value;
92-
return 0;
93-
}
94-
95-
/**
96-
* \brief Pretend to execute a STR Exclusive (32 bit)
97-
* \details Executes a ~exclusive~ STR instruction for 32 bit values.
98-
* \param [in] value Value to store
99-
* \param [in] ptr Pointer to location
100-
* \return 0 Function succeeded (always)
101-
*/
102-
static inline uint32_t __STREXW(uint32_t value, volatile uint32_t *ptr)
103-
{
104-
*ptr = value;
105-
return 0;
106-
}
107-
108-
/**
109-
* \brief Pretend to execute a LDR Exclusive (8 bit)
110-
* \details Executes an ~exclusive~ LDR instruction for 8 bit value.
111-
* Meaning, it does not set a exclusive lock,
112-
* instead just loads the stored value
113-
* \param [in] ptr Pointer to data
114-
* \return value of type uint8_t at (*ptr)
115-
*/
116-
static inline uint8_t __LDREXB(volatile uint8_t *ptr)
117-
{
118-
return *ptr;
119-
}
120-
121-
/**
122-
* \brief Pretend to execute a LDR Exclusive (16 bit)
123-
* \details Executes an ~exclusive~ LDR instruction for 16 bit value.
124-
* Meaning, it does not set a exclusive lock,
125-
* instead just loads the stored value
126-
* \param [in] ptr Pointer to data
127-
* \return value of type uint8_t at (*ptr)
128-
*/
129-
static inline uint16_t __LDREXH(volatile uint16_t *ptr)
130-
{
131-
return *ptr;
132-
}
133-
134-
/**
135-
* \brief Pretend to execute a LDR Exclusive (32 bit)
136-
* \details Executes an ~exclusive~ LDR instruction for 32 bit value.
137-
* Meaning, it does not set a exclusive lock,
138-
* instead just loads the stored value
139-
* \param [in] ptr Pointer to data
140-
* \return value of type uint8_t at (*ptr)
141-
*/
142-
static inline uint32_t __LDREXW(volatile uint32_t *ptr)
143-
{
144-
return *ptr;
145-
}
146-
147-
/**
148-
* \brief Pretend to remove the exclusive lock
149-
* \details The real function would removes the exclusive lock which is created
150-
* by LDREX, this one does nothing
151-
*/
152-
static inline void __CLREX(void) { /* Nothing to be done */ }
43+
uint32_t __STREXB(uint8_t value, volatile uint8_t *ptr);
44+
uint32_t __STREXH(uint16_t value, volatile uint16_t *ptr);
45+
uint32_t __STREXW(uint32_t value, volatile uint32_t *ptr);
46+
uint8_t __LDREXB(volatile uint8_t *ptr);
47+
uint16_t __LDREXH(volatile uint16_t *ptr);
48+
uint32_t __LDREXW(volatile uint32_t *ptr);
49+
void __CLREX(void);
15350

15451
/**
15552
* \brief Model of an ARM CLZ instruction

boards/native/nrf_bsim/irq_handler.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,7 @@ void posix_irq_handler(void)
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118118
currently_running_irq = irq_nbr;
119119
vector_to_irq(irq_nbr, &may_swap);
120+
nrfbsim_clear_excl_access();
120121
currently_running_irq = last_running_irq;
121122

122123
hw_irq_ctrl_reeval_level_irq(cpu_n, irq_nbr);

boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml

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Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
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#
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identifier: frdm_mcxn947/mcxn947/cpu0/qspi
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name: NXP FRDM-MCXN947 QSPI (CPU0)
8+
name: NXP FRDM-MCXN947 (CPU0) (QSPI)
99
type: mcu
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arch: arm
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ram: 320

boards/nxp/lpcxpresso11u68/lpcxpresso11u68.yaml

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@@ -1,5 +1,5 @@
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identifier: lpcxpresso11u68
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name: NXP LPCxpresso 11U68
2+
name: NXP LPCxpresso11U68
33
type: mcu
44
arch: arm
55
ram: 32

boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml

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Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
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#
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identifier: lpcxpresso54114/lpc54114/m0
8-
name: NXP LPCXpresso54114 M0
8+
name: NXP LPCXpresso54114 (M0)
99
type: mcu
1010
arch: arm
1111
ram: 32

boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml

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@@ -5,7 +5,7 @@
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#
66

77
identifier: lpcxpresso54114/lpc54114/m4
8-
name: NXP LPCXpresso54114 M4
8+
name: NXP LPCXpresso54114 (M4)
99
type: mcu
1010
arch: arm
1111
ram: 64

boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml

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Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
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#
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identifier: lpcxpresso55s69/lpc55s69/cpu0/ns
8-
name: NXP LPCXpresso55S69 (Non-Secure)
8+
name: NXP LPCXpresso55S69 (CPU0) (Non-Secure)
99
type: mcu
1010
arch: arm
1111
ram: 136

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