diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/buffers.json.j2 b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/buffers.json.j2 new file mode 100644 index 0000000000..f34a844f4a --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/buffers.json.j2 @@ -0,0 +1,2 @@ +{%- set default_topo = 't2' %} +{%- include 'buffers_config.j2' %} diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/buffers_defaults_t2.j2 b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/buffers_defaults_t2.j2 new file mode 100644 index 0000000000..d3576d0021 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/buffers_defaults_t2.j2 @@ -0,0 +1,49 @@ +{%- set default_cable = '300m' %} + +{%- set ports2cable = { + 'torrouter_server' : '300m', + 'leafrouter_torrouter' : '300m', + 'spinerouter_leafrouter' : '2000m', + 'upperspinerouter_spinerouter' : '50m', + 'regionalhub_upperspinerouter': '120000m', + 'aznghub_upperspinerouter' : '120000m', + 'regionalhub_spinerouter': '120000m', + 'aznghub_spinerouter' : '120000m' + } +-%} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(0,144,8) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "6441610000", + "type": "both", + "mode": "dynamic", + "xoff": "792476467" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "xon_offset": "0", + "dynamic_th":"0" + }, + "egress_lossless_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "dynamic_th":"-1" + }, + "egress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "dynamic_th":"-4" + } + }, +{%- endmacro %} diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/context_config.json b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/context_config.json new file mode 100644 index 0000000000..3da200f065 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/context_config.json @@ -0,0 +1,25 @@ +{ + "CONTEXTS": [ + { + "guid" : 0, + "name" : "syncd", + "dbAsic" : "ASIC_DB", + "dbCounters" : "COUNTERS_DB", + "dbFlex": "FLEX_COUNTER_DB", + "dbState" : "STATE_DB", + "zmq_enable": false, + "zmq_endpoint": "tcp://127.0.0.1:5555", + "zmq_ntf_endpoint": "tcp://127.0.0.1:5556", + "switches": [ + { + "index" : 0, + "hwinfo" : "09:00.0" + }, + { + "index" : 1, + "hwinfo" : "03:00.0" + } + ] + } + ] +} diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/jr2p-a7280dra3-36-36x400G.config.bcm b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/jr2p-a7280dra3-36-36x400G.config.bcm new file mode 100644 index 0000000000..7b464e74eb --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/jr2p-a7280dra3-36-36x400G.config.bcm @@ -0,0 +1,987 @@ +soc_family=BCM8885X +system_ref_core_clock_khz=1600000 + +dpp_db_path=/usr/share/bcm/db +programmability_ucode_relative_path.BCM8885X=pemla/ucode/standard_1/jer2pemla/u_code_db2pem.txt +sai_postinit_cmd_file=/usr/share/sonic/hwsku/sai_postinit_cmd.soc +#################################################### +##Reference applications related properties - Start +#################################################### + +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +pmf_sexem3_stage=IPMF2 + +#################################################### +##Reference applications related properties - End +#################################################### + +# Jericho2-mode (description 0x1 used for Jericho 2 mode) +system_headers_mode=1 + +# HW mode to support 1024 16-member system wide LAGs +trunk_group_max_members=16 + +# Disable link-training +port_init_cl72=0 + +###Default interfaces for Jericho2Plus +#CPU interfaces +ucode_port_0=CPU.0:core_0.0 +ucode_port_200=CPU.8:core_1.200 +ucode_port_201=CPU.16:core_0.201 +ucode_port_202=CPU.24:core_1.202 +ucode_port_203=CPU.32:core_0.203 + +#NIF ETH interfaces on device +ucode_port_1=CDGE9:core_1.1 +ucode_port_2=CDGE10:core_1.2 +ucode_port_3=CDGE11:core_1.3 +ucode_port_4=CDGE12:core_1.4 +ucode_port_5=CDGE13:core_1.5 +ucode_port_6=CDGE14:core_1.6 +ucode_port_7=CDGE15:core_1.7 +ucode_port_8=CDGE16:core_1.8 +ucode_port_9=CDGE17:core_1.9 + +ucode_port_10=CDGE8:core_0.10 +ucode_port_11=CDGE7:core_0.11 +ucode_port_12=CDGE6:core_0.12 +ucode_port_13=CDGE5:core_0.13 +ucode_port_14=CDGE4:core_0.14 +ucode_port_15=CDGE3:core_0.15 +ucode_port_16=CDGE2:core_0.16 +ucode_port_17=CDGE1:core_0.17 +ucode_port_18=CDGE0:core_0.18 + +#NIF default speeds +port_init_speed_xe=10000 +port_init_speed_xl=40000 +port_init_speed_le=50000 +port_init_speed_ce=100000 +port_init_speed_cc=200000 +port_init_speed_cd=400000 +port_init_speed_il=10312 + +port_priorities=8 + +#special ports +ucode_port_240=OLP:core_0.240 + +# NIF lane mapping +lane_to_serdes_map_nif_lane0=rx0:tx3 +lane_to_serdes_map_nif_lane1=rx3:tx7 +lane_to_serdes_map_nif_lane2=rx1:tx2 +lane_to_serdes_map_nif_lane3=rx6:tx6 +lane_to_serdes_map_nif_lane4=rx4:tx1 +lane_to_serdes_map_nif_lane5=rx7:tx5 +lane_to_serdes_map_nif_lane6=rx2:tx0 +lane_to_serdes_map_nif_lane7=rx5:tx4 +lane_to_serdes_map_nif_lane8=rx15:tx10 +lane_to_serdes_map_nif_lane9=rx11:tx9 +lane_to_serdes_map_nif_lane10=rx13:tx13 +lane_to_serdes_map_nif_lane11=rx14:tx8 +lane_to_serdes_map_nif_lane12=rx10:tx15 +lane_to_serdes_map_nif_lane13=rx8:tx12 +lane_to_serdes_map_nif_lane14=rx9:tx14 +lane_to_serdes_map_nif_lane15=rx12:tx11 +lane_to_serdes_map_nif_lane16=rx18:tx17 +lane_to_serdes_map_nif_lane17=rx16:tx16 +lane_to_serdes_map_nif_lane18=rx17:tx21 +lane_to_serdes_map_nif_lane19=rx19:tx19 +lane_to_serdes_map_nif_lane20=rx21:tx23 +lane_to_serdes_map_nif_lane21=rx22:tx20 +lane_to_serdes_map_nif_lane22=rx20:tx22 +lane_to_serdes_map_nif_lane23=rx23:tx18 +lane_to_serdes_map_nif_lane24=rx26:tx28 +lane_to_serdes_map_nif_lane25=rx30:tx30 +lane_to_serdes_map_nif_lane26=rx29:tx24 +lane_to_serdes_map_nif_lane27=rx31:tx31 +lane_to_serdes_map_nif_lane28=rx25:tx26 +lane_to_serdes_map_nif_lane29=rx24:tx29 +lane_to_serdes_map_nif_lane30=rx28:tx27 +lane_to_serdes_map_nif_lane31=rx27:tx25 +lane_to_serdes_map_nif_lane32=rx33:tx35 +lane_to_serdes_map_nif_lane33=rx32:tx34 +lane_to_serdes_map_nif_lane34=rx34:tx37 +lane_to_serdes_map_nif_lane35=rx35:tx33 +lane_to_serdes_map_nif_lane36=rx36:tx38 +lane_to_serdes_map_nif_lane37=rx39:tx36 +lane_to_serdes_map_nif_lane38=rx37:tx39 +lane_to_serdes_map_nif_lane39=rx38:tx32 +lane_to_serdes_map_nif_lane40=rx46:tx45 +lane_to_serdes_map_nif_lane41=rx47:tx47 +lane_to_serdes_map_nif_lane42=rx43:tx41 +lane_to_serdes_map_nif_lane43=rx45:tx46 +lane_to_serdes_map_nif_lane44=rx40:tx40 +lane_to_serdes_map_nif_lane45=rx44:tx44 +lane_to_serdes_map_nif_lane46=rx41:tx43 +lane_to_serdes_map_nif_lane47=rx42:tx42 +lane_to_serdes_map_nif_lane48=rx48:tx48 +lane_to_serdes_map_nif_lane49=rx50:tx51 +lane_to_serdes_map_nif_lane50=rx49:tx52 +lane_to_serdes_map_nif_lane51=rx53:tx50 +lane_to_serdes_map_nif_lane52=rx51:tx55 +lane_to_serdes_map_nif_lane53=rx55:tx49 +lane_to_serdes_map_nif_lane54=rx52:tx54 +lane_to_serdes_map_nif_lane55=rx54:tx53 +lane_to_serdes_map_nif_lane56=rx63:tx61 +lane_to_serdes_map_nif_lane57=rx61:tx63 +lane_to_serdes_map_nif_lane58=rx59:tx59 +lane_to_serdes_map_nif_lane59=rx62:tx62 +lane_to_serdes_map_nif_lane60=rx56:tx57 +lane_to_serdes_map_nif_lane61=rx57:tx56 +lane_to_serdes_map_nif_lane62=rx58:tx58 +lane_to_serdes_map_nif_lane63=rx60:tx60 +lane_to_serdes_map_nif_lane64=rx66:tx65 +lane_to_serdes_map_nif_lane65=rx64:tx64 +lane_to_serdes_map_nif_lane66=rx65:tx69 +lane_to_serdes_map_nif_lane67=rx67:tx67 +lane_to_serdes_map_nif_lane68=rx69:tx71 +lane_to_serdes_map_nif_lane69=rx70:tx68 +lane_to_serdes_map_nif_lane70=rx68:tx70 +lane_to_serdes_map_nif_lane71=rx71:tx66 +lane_to_serdes_map_nif_lane72=rx78:tx75 +lane_to_serdes_map_nif_lane73=rx73:tx78 +lane_to_serdes_map_nif_lane74=rx75:tx74 +lane_to_serdes_map_nif_lane75=rx72:tx79 +lane_to_serdes_map_nif_lane76=rx77:tx72 +lane_to_serdes_map_nif_lane77=rx79:tx76 +lane_to_serdes_map_nif_lane78=rx74:tx73 +lane_to_serdes_map_nif_lane79=rx76:tx77 +lane_to_serdes_map_nif_lane80=rx86:tx82 +lane_to_serdes_map_nif_lane81=rx87:tx80 +lane_to_serdes_map_nif_lane82=rx83:tx85 +lane_to_serdes_map_nif_lane83=rx85:tx81 +lane_to_serdes_map_nif_lane84=rx84:tx86 +lane_to_serdes_map_nif_lane85=rx82:tx83 +lane_to_serdes_map_nif_lane86=rx81:tx87 +lane_to_serdes_map_nif_lane87=rx80:tx84 +lane_to_serdes_map_nif_lane88=rx88:tx89 +lane_to_serdes_map_nif_lane89=rx89:tx88 +lane_to_serdes_map_nif_lane90=rx91:tx93 +lane_to_serdes_map_nif_lane91=rx90:tx91 +lane_to_serdes_map_nif_lane92=rx94:tx95 +lane_to_serdes_map_nif_lane93=rx92:tx92 +lane_to_serdes_map_nif_lane94=rx95:tx94 +lane_to_serdes_map_nif_lane95=rx93:tx90 +lane_to_serdes_map_nif_lane96=rx103:tx100 +lane_to_serdes_map_nif_lane97=rx101:tx103 +lane_to_serdes_map_nif_lane98=rx102:tx96 +lane_to_serdes_map_nif_lane99=rx98:tx102 +lane_to_serdes_map_nif_lane100=rx99:tx99 +lane_to_serdes_map_nif_lane101=rx96:tx97 +lane_to_serdes_map_nif_lane102=rx100:tx98 +lane_to_serdes_map_nif_lane103=rx97:tx101 +lane_to_serdes_map_nif_lane104=rx104:tx107 +lane_to_serdes_map_nif_lane105=rx106:tx105 +lane_to_serdes_map_nif_lane106=rx107:tx109 +lane_to_serdes_map_nif_lane107=rx105:tx106 +lane_to_serdes_map_nif_lane108=rx111:tx111 +lane_to_serdes_map_nif_lane109=rx109:tx104 +lane_to_serdes_map_nif_lane110=rx110:tx110 +lane_to_serdes_map_nif_lane111=rx108:tx108 +lane_to_serdes_map_nif_lane112=rx117:tx117 +lane_to_serdes_map_nif_lane113=rx118:tx119 +lane_to_serdes_map_nif_lane114=rx119:tx113 +lane_to_serdes_map_nif_lane115=rx115:tx118 +lane_to_serdes_map_nif_lane116=rx114:tx112 +lane_to_serdes_map_nif_lane117=rx112:tx116 +lane_to_serdes_map_nif_lane118=rx116:tx115 +lane_to_serdes_map_nif_lane119=rx113:tx114 +lane_to_serdes_map_nif_lane120=rx125:tx120 +lane_to_serdes_map_nif_lane121=rx121:tx123 +lane_to_serdes_map_nif_lane122=rx122:tx124 +lane_to_serdes_map_nif_lane123=rx120:tx122 +lane_to_serdes_map_nif_lane124=rx126:tx127 +lane_to_serdes_map_nif_lane125=rx127:tx121 +lane_to_serdes_map_nif_lane126=rx124:tx126 +lane_to_serdes_map_nif_lane127=rx123:tx125 +lane_to_serdes_map_nif_lane128=rx134:tx133 +lane_to_serdes_map_nif_lane129=rx135:tx134 +lane_to_serdes_map_nif_lane130=rx133:tx131 +lane_to_serdes_map_nif_lane131=rx131:tx135 +lane_to_serdes_map_nif_lane132=rx132:tx130 +lane_to_serdes_map_nif_lane133=rx128:tx132 +lane_to_serdes_map_nif_lane134=rx130:tx129 +lane_to_serdes_map_nif_lane135=rx129:tx128 +lane_to_serdes_map_nif_lane136=rx136:tx137 +lane_to_serdes_map_nif_lane137=rx138:tx136 +lane_to_serdes_map_nif_lane138=rx139:tx141 +lane_to_serdes_map_nif_lane139=rx137:tx139 +lane_to_serdes_map_nif_lane140=rx142:tx143 +lane_to_serdes_map_nif_lane141=rx143:tx140 +lane_to_serdes_map_nif_lane142=rx141:tx142 +lane_to_serdes_map_nif_lane143=rx140:tx138 + +######################### +### High Availability ### +######################### + +sw_state_max_size=750000000 + +#location of warmboot NV memory +#Allowed options for dnx are - 3:external storage in filesystem 4:driver will save the state directly in shared memory +stable_location=4 + +# Note that each unit should have a unique filename and that adapter does not play well with tmp and dev/shm folders. +stable_filename=/dev/shm/warmboot_data_0 +stable_filename.1=/dev/shm/warmboot_data_1 +stable_filename.2=/dev/shm/warmboot_data_2 + +#Maximum size for NVM used for WB storage, must be larger than sw_state_max_size.BCM8885X +stable_size=800000000 + +######################### +######################### +######################### + +tm_port_header_type_in_0=INJECTED_2_PP +tm_port_header_type_out_0=CPU + +tm_port_header_type_in_200=INJECTED_2_PP +tm_port_header_type_out_200=ETH +tm_port_header_type_in_201=INJECTED_2_PP +tm_port_header_type_out_201=ETH +tm_port_header_type_in_202=INJECTED_2_PP +tm_port_header_type_out_202=ETH +tm_port_header_type_in_203=INJECTED_2_PP +tm_port_header_type_out_203=ETH + +### RCY +sai_recycle_port_lane_base=200 +ucode_port_49=RCY0:core_0.49 +ucode_port_50=RCY1:core_1.50 +tm_port_header_type_out_49=ETH +tm_port_header_type_in_49=ETH +tm_port_header_type_out_50=ETH +tm_port_header_type_in_50=ETH +port_init_speed_49=400000 +port_init_speed_50=400000 +ucode_port_100.BCM8885X=RCY_MIRROR.0:core_0.100 +ucode_port_101.BCM8885X=RCY_MIRROR.1:core_0.101 +ucode_port_102.BCM8885X=RCY_MIRROR.2:core_0.102 +ucode_port_103.BCM8885X=RCY_MIRROR.3:core_0.103 +ucode_port_104.BCM8885X=RCY_MIRROR.4:core_0.104 +ucode_port_105.BCM8885X=RCY_MIRROR.5:core_0.105 +ucode_port_106.BCM8885X=RCY_MIRROR.6:core_0.106 +ucode_port_107.BCM8885X=RCY_MIRROR.7:core_0.107 +ucode_port_108.BCM8885X=RCY_MIRROR.8:core_0.108 +ucode_port_109.BCM8885X=RCY_MIRROR.9:core_0.109 +ucode_port_110.BCM8885X=RCY_MIRROR.10:core_0.110 +ucode_port_111.BCM8885X=RCY_MIRROR.11:core_0.111 +ucode_port_112.BCM8885X=RCY_MIRROR.12:core_0.112 +ucode_port_113.BCM8885X=RCY_MIRROR.13:core_0.113 +ucode_port_114.BCM8885X=RCY_MIRROR.14:core_0.114 +ucode_port_115.BCM8885X=RCY_MIRROR.15:core_0.115 +ucode_port_116.BCM8885X=RCY_MIRROR.16:core_0.116 +ucode_port_117.BCM8885X=RCY_MIRROR.17:core_0.117 +ucode_port_118.BCM8885X=RCY_MIRROR.18:core_0.118 +ucode_port_119.BCM8885X=RCY_MIRROR.19:core_0.119 +ucode_port_120.BCM8885X=RCY_MIRROR.0:core_1.120 +ucode_port_121.BCM8885X=RCY_MIRROR.1:core_1.121 +ucode_port_122.BCM8885X=RCY_MIRROR.2:core_1.122 +ucode_port_123.BCM8885X=RCY_MIRROR.3:core_1.123 +ucode_port_124.BCM8885X=RCY_MIRROR.4:core_1.124 +ucode_port_125.BCM8885X=RCY_MIRROR.5:core_1.125 +ucode_port_126.BCM8885X=RCY_MIRROR.6:core_1.126 +ucode_port_127.BCM8885X=RCY_MIRROR.7:core_1.127 +ucode_port_128.BCM8885X=RCY_MIRROR.8:core_1.128 +ucode_port_129.BCM8885X=RCY_MIRROR.9:core_1.129 +ucode_port_130.BCM8885X=RCY_MIRROR.10:core_1.130 +ucode_port_131.BCM8885X=RCY_MIRROR.11:core_1.131 +ucode_port_132.BCM8885X=RCY_MIRROR.12:core_1.132 +ucode_port_133.BCM8885X=RCY_MIRROR.13:core_1.133 +ucode_port_134.BCM8885X=RCY_MIRROR.14:core_1.134 +ucode_port_135.BCM8885X=RCY_MIRROR.15:core_1.135 +ucode_port_136.BCM8885X=RCY_MIRROR.16:core_1.136 +ucode_port_137.BCM8885X=RCY_MIRROR.17:core_1.137 +ucode_port_138.BCM8885X=RCY_MIRROR.18:core_1.138 +ucode_port_139.BCM8885X=RCY_MIRROR.19:core_1.139 + +#OLP port +tm_port_header_type_in_240=INJECTED_2 +tm_port_header_type_out_240=RAW + +# Set statically the region mode per region id +dtm_flow_mapping_mode_region_257=3 +dtm_flow_mapping_mode_region_258=3 +dtm_flow_mapping_mode_region_259=3 +dtm_flow_mapping_mode_region_260=3 +dtm_flow_mapping_mode_region_261=3 +dtm_flow_mapping_mode_region_262=3 +dtm_flow_mapping_mode_region_263=3 +dtm_flow_mapping_mode_region_264=3 +dtm_flow_mapping_mode_region_265=3 +dtm_flow_mapping_mode_region_266=7 +dtm_flow_mapping_mode_region_267=3 +dtm_flow_mapping_mode_region_268=3 +dtm_flow_mapping_mode_region_269=3 +dtm_flow_mapping_mode_region_270=3 +dtm_flow_mapping_mode_region_271=3 +dtm_flow_mapping_mode_region_272=3 +dtm_flow_mapping_mode_region_273=3 +dtm_flow_mapping_mode_region_274=3 +dtm_flow_mapping_mode_region_275=3 +dtm_flow_mapping_mode_region_276=3 +dtm_flow_mapping_mode_region_277=3 +dtm_flow_mapping_mode_region_278=3 +dtm_flow_mapping_mode_region_279=3 +dtm_flow_mapping_mode_region_280=3 +dtm_flow_mapping_mode_region_281=3 +dtm_flow_mapping_mode_region_282=3 +dtm_flow_mapping_mode_region_283=3 +dtm_flow_mapping_mode_region_284=3 +dtm_flow_mapping_mode_region_285=3 +dtm_flow_mapping_mode_region_286=3 +dtm_flow_mapping_mode_region_287=3 + +## Configure number of symmetric cores each region supports ## +dtm_flow_nof_remote_cores_region_1=2 +dtm_flow_nof_remote_cores_region_2=2 +dtm_flow_nof_remote_cores_region_3=2 +dtm_flow_nof_remote_cores_region_4=2 +dtm_flow_nof_remote_cores_region_5=2 +dtm_flow_nof_remote_cores_region_6=2 +dtm_flow_nof_remote_cores_region_7=2 +dtm_flow_nof_remote_cores_region_8=2 +dtm_flow_nof_remote_cores_region_9=2 +dtm_flow_nof_remote_cores_region_10=2 +dtm_flow_nof_remote_cores_region_11=2 +dtm_flow_nof_remote_cores_region_12=2 +dtm_flow_nof_remote_cores_region_13=2 +dtm_flow_nof_remote_cores_region_14=2 +dtm_flow_nof_remote_cores_region_15=2 +dtm_flow_nof_remote_cores_region_16=2 +dtm_flow_nof_remote_cores_region_17=2 +dtm_flow_nof_remote_cores_region_18=2 +dtm_flow_nof_remote_cores_region_19=2 +dtm_flow_nof_remote_cores_region_20=2 +dtm_flow_nof_remote_cores_region_21=2 +dtm_flow_nof_remote_cores_region_22=2 +dtm_flow_nof_remote_cores_region_23=2 +dtm_flow_nof_remote_cores_region_24=2 +dtm_flow_nof_remote_cores_region_25=2 +dtm_flow_nof_remote_cores_region_26=2 +dtm_flow_nof_remote_cores_region_27=2 +dtm_flow_nof_remote_cores_region_28=2 +dtm_flow_nof_remote_cores_region_29=2 +dtm_flow_nof_remote_cores_region_30=2 +dtm_flow_nof_remote_cores_region_31=2 +dtm_flow_nof_remote_cores_region_32=2 +dtm_flow_nof_remote_cores_region_33=2 +dtm_flow_nof_remote_cores_region_34=2 +dtm_flow_nof_remote_cores_region_35=2 +dtm_flow_nof_remote_cores_region_36=2 +dtm_flow_nof_remote_cores_region_37=2 +dtm_flow_nof_remote_cores_region_38=2 +dtm_flow_nof_remote_cores_region_39=2 +dtm_flow_nof_remote_cores_region_40=2 +dtm_flow_nof_remote_cores_region_41=2 +dtm_flow_nof_remote_cores_region_42=2 +dtm_flow_nof_remote_cores_region_43=2 +dtm_flow_nof_remote_cores_region_44=2 +dtm_flow_nof_remote_cores_region_45=2 +dtm_flow_nof_remote_cores_region_46=2 +dtm_flow_nof_remote_cores_region_47=2 +dtm_flow_nof_remote_cores_region_48=2 +dtm_flow_nof_remote_cores_region_49=2 +dtm_flow_nof_remote_cores_region_50=2 +dtm_flow_nof_remote_cores_region_51=2 +dtm_flow_nof_remote_cores_region_52=2 +dtm_flow_nof_remote_cores_region_53=2 +dtm_flow_nof_remote_cores_region_54=2 +dtm_flow_nof_remote_cores_region_55=2 +dtm_flow_nof_remote_cores_region_56=2 +dtm_flow_nof_remote_cores_region_57=2 +dtm_flow_nof_remote_cores_region_58=2 +dtm_flow_nof_remote_cores_region_59=2 +dtm_flow_nof_remote_cores_region_60=2 + +### MDB configuration ### +mdb_profile=balanced-exem + +### Descriptor-DMA configuration ### +dma_desc_aggregator_chain_length_max=1000 +dma_desc_aggregator_buff_size_kb=100 +dma_desc_aggregator_timeout_usec=1000 +dma_desc_aggregator_enable_specific_MDB_LPM=1 +dma_desc_aggregator_enable_specific_MDB_FEC=1 + +### Outlif configuarion ### +outlif_logical_to_physical_phase_map_1=S1 +outlif_logical_to_physical_phase_map_2=L1 +outlif_logical_to_physical_phase_map_3=XL +outlif_logical_to_physical_phase_map_4=L2 +outlif_logical_to_physical_phase_map_5=M1 +outlif_logical_to_physical_phase_map_6=M2 +outlif_logical_to_physical_phase_map_7=M3 +outlif_logical_to_physical_phase_map_8=S2 + +### Outlif data granularity configuration ### +outlif_physical_phase_data_granularity_S1=60 +outlif_physical_phase_data_granularity_S2=60 +outlif_physical_phase_data_granularity_M1=60 +outlif_physical_phase_data_granularity_M2=60 +outlif_physical_phase_data_granularity_M3=60 +outlif_physical_phase_data_granularity_L1=60 +outlif_physical_phase_data_granularity_L2=60 +outlif_physical_phase_data_granularity_XL=60 + +### Fabric configuration ### +# Enable link-training +port_init_cl72_sfi=1 +serdes_lane_config_cl72_auto_polarity_en=0 +serdes_lane_config_cl72_auto_polarity_en_sfi=1 +serdes_lane_config_cl72_restart_timeout_en=0 + +#SFI speed rate +port_init_speed_fabric=53125 + +## Fabric transmission mode +# Set the Connect mode to the Fabric +# Options: FE - presence of a Fabric device (single stage) +# SINGLE_FAP - stand-alone device +# MESH - devices in Mesh +# Note: If 'diag_chassis' is on, value will be override in dnx.soc +# to be FE instead of SINGLE_FAP. +appl_param_nof_devices.BCM8885X=2 +fabric_connect_mode=MESH +fabric_mesh_multicast_enable=1 +fabric_num_pipes=2 +fabric_pipe_map_uc=0 +fabric_pipe_map_mc=1 +system_contains_multiple_pipe_device=1 +fabric_logical_port_base=450 + +# Fabric lane mapping +lane_to_serdes_map_fabric_lane0=rx0:tx0 +lane_to_serdes_map_fabric_lane1=rx1:tx1 +lane_to_serdes_map_fabric_lane2=rx2:tx2 +lane_to_serdes_map_fabric_lane3=rx3:tx3 +lane_to_serdes_map_fabric_lane4=rx4:tx4 +lane_to_serdes_map_fabric_lane5=rx5:tx5 +lane_to_serdes_map_fabric_lane6=rx6:tx6 +lane_to_serdes_map_fabric_lane7=rx7:tx7 +lane_to_serdes_map_fabric_lane8=rx8:tx9 +lane_to_serdes_map_fabric_lane9=rx9:tx11 +lane_to_serdes_map_fabric_lane10=rx10:tx10 +lane_to_serdes_map_fabric_lane11=rx11:tx8 +lane_to_serdes_map_fabric_lane12=rx12:tx15 +lane_to_serdes_map_fabric_lane13=rx13:tx14 +lane_to_serdes_map_fabric_lane14=rx14:tx12 +lane_to_serdes_map_fabric_lane15=rx15:tx13 +lane_to_serdes_map_fabric_lane16=rx16:tx18 +lane_to_serdes_map_fabric_lane17=rx17:tx17 +lane_to_serdes_map_fabric_lane18=rx18:tx16 +lane_to_serdes_map_fabric_lane19=rx19:tx19 +lane_to_serdes_map_fabric_lane20=rx20:tx20 +lane_to_serdes_map_fabric_lane21=rx21:tx21 +lane_to_serdes_map_fabric_lane22=rx22:tx22 +lane_to_serdes_map_fabric_lane23=rx23:tx23 +lane_to_serdes_map_fabric_lane24=rx24:tx24 +lane_to_serdes_map_fabric_lane25=rx25:tx27 +lane_to_serdes_map_fabric_lane26=rx26:tx25 +lane_to_serdes_map_fabric_lane27=rx27:tx26 +lane_to_serdes_map_fabric_lane28=rx28:tx28 +lane_to_serdes_map_fabric_lane29=rx29:tx30 +lane_to_serdes_map_fabric_lane30=rx30:tx29 +lane_to_serdes_map_fabric_lane31=rx31:tx31 +lane_to_serdes_map_fabric_lane32=rx32:tx32 +lane_to_serdes_map_fabric_lane33=rx33:tx33 +lane_to_serdes_map_fabric_lane34=rx34:tx34 +lane_to_serdes_map_fabric_lane35=rx35:tx35 +lane_to_serdes_map_fabric_lane36=rx36:tx36 +lane_to_serdes_map_fabric_lane37=rx37:tx37 +lane_to_serdes_map_fabric_lane38=rx38:tx38 +lane_to_serdes_map_fabric_lane39=rx39:tx39 +lane_to_serdes_map_fabric_lane40=rx40:tx40 +lane_to_serdes_map_fabric_lane41=rx41:tx41 +lane_to_serdes_map_fabric_lane42=rx42:tx42 +lane_to_serdes_map_fabric_lane43=rx43:tx43 +lane_to_serdes_map_fabric_lane44=rx44:tx44 +lane_to_serdes_map_fabric_lane45=rx45:tx45 +lane_to_serdes_map_fabric_lane46=rx46:tx46 +lane_to_serdes_map_fabric_lane47=rx47:tx47 +lane_to_serdes_map_fabric_lane48=rx48:tx48 +lane_to_serdes_map_fabric_lane49=rx49:tx49 +lane_to_serdes_map_fabric_lane50=rx50:tx50 +lane_to_serdes_map_fabric_lane51=rx51:tx51 +lane_to_serdes_map_fabric_lane52=rx52:tx52 +lane_to_serdes_map_fabric_lane53=rx53:tx53 +lane_to_serdes_map_fabric_lane54=rx54:tx54 +lane_to_serdes_map_fabric_lane55=rx55:tx55 +lane_to_serdes_map_fabric_lane56=rx56:tx56 +lane_to_serdes_map_fabric_lane57=rx57:tx57 +lane_to_serdes_map_fabric_lane58=rx58:tx58 +lane_to_serdes_map_fabric_lane59=rx59:tx59 +lane_to_serdes_map_fabric_lane60=rx60:tx60 +lane_to_serdes_map_fabric_lane61=rx61:tx61 +lane_to_serdes_map_fabric_lane62=rx62:tx62 +lane_to_serdes_map_fabric_lane63=rx63:tx63 +lane_to_serdes_map_fabric_lane64=rx64:tx64 +lane_to_serdes_map_fabric_lane65=rx65:tx65 +lane_to_serdes_map_fabric_lane66=rx66:tx66 +lane_to_serdes_map_fabric_lane67=rx67:tx67 +lane_to_serdes_map_fabric_lane68=rx68:tx68 +lane_to_serdes_map_fabric_lane69=rx69:tx69 +lane_to_serdes_map_fabric_lane70=rx70:tx70 +lane_to_serdes_map_fabric_lane71=rx71:tx71 +lane_to_serdes_map_fabric_lane72=rx72:tx72 +lane_to_serdes_map_fabric_lane73=rx73:tx73 +lane_to_serdes_map_fabric_lane74=rx74:tx74 +lane_to_serdes_map_fabric_lane75=rx75:tx75 +lane_to_serdes_map_fabric_lane76=rx76:tx76 +lane_to_serdes_map_fabric_lane77=rx77:tx77 +lane_to_serdes_map_fabric_lane78=rx78:tx78 +lane_to_serdes_map_fabric_lane79=rx79:tx79 +lane_to_serdes_map_fabric_lane80=rx80:tx80 +lane_to_serdes_map_fabric_lane81=rx81:tx81 +lane_to_serdes_map_fabric_lane82=rx82:tx82 +lane_to_serdes_map_fabric_lane83=rx83:tx83 +lane_to_serdes_map_fabric_lane84=rx84:tx86 +lane_to_serdes_map_fabric_lane85=rx85:tx84 +lane_to_serdes_map_fabric_lane86=rx86:tx85 +lane_to_serdes_map_fabric_lane87=rx87:tx87 +lane_to_serdes_map_fabric_lane88=rx88:tx88 +lane_to_serdes_map_fabric_lane89=rx89:tx90 +lane_to_serdes_map_fabric_lane90=rx90:tx91 +lane_to_serdes_map_fabric_lane91=rx91:tx89 +lane_to_serdes_map_fabric_lane92=rx92:tx93 +lane_to_serdes_map_fabric_lane93=rx93:tx94 +lane_to_serdes_map_fabric_lane94=rx94:tx92 +lane_to_serdes_map_fabric_lane95=rx95:tx95 +lane_to_serdes_map_fabric_lane96=rx96:tx96 +lane_to_serdes_map_fabric_lane97=rx97:tx97 +lane_to_serdes_map_fabric_lane98=rx98:tx98 +lane_to_serdes_map_fabric_lane99=rx99:tx99 +lane_to_serdes_map_fabric_lane100=rx100:tx100 +lane_to_serdes_map_fabric_lane101=rx101:tx101 +lane_to_serdes_map_fabric_lane102=rx102:tx102 +lane_to_serdes_map_fabric_lane103=rx103:tx103 +lane_to_serdes_map_fabric_lane104=rx104:tx105 +lane_to_serdes_map_fabric_lane105=rx105:tx107 +lane_to_serdes_map_fabric_lane106=rx106:tx106 +lane_to_serdes_map_fabric_lane107=rx107:tx104 +lane_to_serdes_map_fabric_lane108=rx108:tx111 +lane_to_serdes_map_fabric_lane109=rx109:tx110 +lane_to_serdes_map_fabric_lane110=rx110:tx108 +lane_to_serdes_map_fabric_lane111=rx111:tx109 +lane_to_serdes_map_fabric_lane112=rx112:tx114 +lane_to_serdes_map_fabric_lane113=rx113:tx113 +lane_to_serdes_map_fabric_lane114=rx114:tx112 +lane_to_serdes_map_fabric_lane115=rx115:tx115 +lane_to_serdes_map_fabric_lane116=rx116:tx116 +lane_to_serdes_map_fabric_lane117=rx117:tx117 +lane_to_serdes_map_fabric_lane118=rx118:tx118 +lane_to_serdes_map_fabric_lane119=rx119:tx119 +lane_to_serdes_map_fabric_lane120=rx120:tx120 +lane_to_serdes_map_fabric_lane121=rx121:tx123 +lane_to_serdes_map_fabric_lane122=rx122:tx121 +lane_to_serdes_map_fabric_lane123=rx123:tx122 +lane_to_serdes_map_fabric_lane124=rx124:tx124 +lane_to_serdes_map_fabric_lane125=rx125:tx126 +lane_to_serdes_map_fabric_lane126=rx126:tx125 +lane_to_serdes_map_fabric_lane127=rx127:tx127 +lane_to_serdes_map_fabric_lane128=rx128:tx128 +lane_to_serdes_map_fabric_lane129=rx129:tx129 +lane_to_serdes_map_fabric_lane130=rx130:tx130 +lane_to_serdes_map_fabric_lane131=rx131:tx131 +lane_to_serdes_map_fabric_lane132=rx132:tx132 +lane_to_serdes_map_fabric_lane133=rx133:tx133 +lane_to_serdes_map_fabric_lane134=rx134:tx134 +lane_to_serdes_map_fabric_lane135=rx135:tx135 +lane_to_serdes_map_fabric_lane136=rx136:tx136 +lane_to_serdes_map_fabric_lane137=rx137:tx137 +lane_to_serdes_map_fabric_lane138=rx138:tx138 +lane_to_serdes_map_fabric_lane139=rx139:tx139 +lane_to_serdes_map_fabric_lane140=rx140:tx140 +lane_to_serdes_map_fabric_lane141=rx141:tx141 +lane_to_serdes_map_fabric_lane142=rx142:tx142 +lane_to_serdes_map_fabric_lane143=rx143:tx143 +lane_to_serdes_map_fabric_lane144=rx144:tx144 +lane_to_serdes_map_fabric_lane145=rx145:tx145 +lane_to_serdes_map_fabric_lane146=rx146:tx146 +lane_to_serdes_map_fabric_lane147=rx147:tx147 +lane_to_serdes_map_fabric_lane148=rx148:tx148 +lane_to_serdes_map_fabric_lane149=rx149:tx149 +lane_to_serdes_map_fabric_lane150=rx150:tx150 +lane_to_serdes_map_fabric_lane151=rx151:tx151 +lane_to_serdes_map_fabric_lane152=rx152:tx152 +lane_to_serdes_map_fabric_lane153=rx153:tx153 +lane_to_serdes_map_fabric_lane154=rx154:tx154 +lane_to_serdes_map_fabric_lane155=rx155:tx155 +lane_to_serdes_map_fabric_lane156=rx156:tx156 +lane_to_serdes_map_fabric_lane157=rx157:tx157 +lane_to_serdes_map_fabric_lane158=rx158:tx158 +lane_to_serdes_map_fabric_lane159=rx159:tx159 +lane_to_serdes_map_fabric_lane160=rx160:tx160 +lane_to_serdes_map_fabric_lane161=rx161:tx161 +lane_to_serdes_map_fabric_lane162=rx162:tx162 +lane_to_serdes_map_fabric_lane163=rx163:tx163 +lane_to_serdes_map_fabric_lane164=rx164:tx164 +lane_to_serdes_map_fabric_lane165=rx165:tx165 +lane_to_serdes_map_fabric_lane166=rx166:tx166 +lane_to_serdes_map_fabric_lane167=rx167:tx167 +lane_to_serdes_map_fabric_lane168=rx168:tx168 +lane_to_serdes_map_fabric_lane169=rx169:tx169 +lane_to_serdes_map_fabric_lane170=rx170:tx170 +lane_to_serdes_map_fabric_lane171=rx171:tx171 +lane_to_serdes_map_fabric_lane172=rx172:tx172 +lane_to_serdes_map_fabric_lane173=rx173:tx173 +lane_to_serdes_map_fabric_lane174=rx174:tx174 +lane_to_serdes_map_fabric_lane175=rx175:tx175 +lane_to_serdes_map_fabric_lane176=rx176:tx176 +lane_to_serdes_map_fabric_lane177=rx177:tx177 +lane_to_serdes_map_fabric_lane178=rx178:tx178 +lane_to_serdes_map_fabric_lane179=rx179:tx179 +lane_to_serdes_map_fabric_lane180=rx180:tx182 +lane_to_serdes_map_fabric_lane181=rx181:tx180 +lane_to_serdes_map_fabric_lane182=rx182:tx181 +lane_to_serdes_map_fabric_lane183=rx183:tx183 +lane_to_serdes_map_fabric_lane184=rx184:tx187 +lane_to_serdes_map_fabric_lane185=rx185:tx186 +lane_to_serdes_map_fabric_lane186=rx186:tx185 +lane_to_serdes_map_fabric_lane187=rx187:tx184 +lane_to_serdes_map_fabric_lane188=rx188:tx190 +lane_to_serdes_map_fabric_lane189=rx189:tx189 +lane_to_serdes_map_fabric_lane190=rx190:tx191 +lane_to_serdes_map_fabric_lane191=rx191:tx188 + +# +##Protocol trap look-up mode: +# Options: IN_LIF - Look-ups in the profile table are done by IN-LIF +# IN_PORT - Look-ups in the profile table are done by IN-PORT +protocol_traps_mode=IN_LIF + +# access definitions +schan_intr_enable=0 +tdma_intr_enable=0 +tslam_intr_enable=0 +miim_intr_enable=0 +schan_timeout_usec=300000 +tdma_timeout_usec=1000000 +tslam_timeout_usec=1000000 + +### Interrupts +appl_enable_intr_init=1 +polled_irq_mode=0 +# reduce CPU load, configure delay 100ms +polled_irq_delay=1000 + +# reduce the CPU load over adapter (caused by counter thread) +bcm_stat_interval=1000000 + +# shadow memory +mem_cache_enable_ecc=1 +mem_cache_enable_parity=1 + +# serdes_nif/fabric_clk_freq_in/out configuration +serdes_nif_clk_freq_in=2 +serdes_nif_clk_freq_out=1 +serdes_fabric_clk_freq_in=2 +serdes_fabric_clk_freq_out=1 + +dport_map_direct=1 + +rif_id_max=0x6000 + +phy_rx_polarity_flip_phy72=1 +phy_tx_polarity_flip_phy72=0 +phy_rx_polarity_flip_phy73=1 +phy_tx_polarity_flip_phy73=0 +phy_rx_polarity_flip_phy74=0 +phy_tx_polarity_flip_phy74=0 +phy_rx_polarity_flip_phy75=0 +phy_tx_polarity_flip_phy75=1 +phy_rx_polarity_flip_phy76=1 +phy_tx_polarity_flip_phy76=0 +phy_rx_polarity_flip_phy77=0 +phy_tx_polarity_flip_phy77=0 +phy_rx_polarity_flip_phy78=1 +phy_tx_polarity_flip_phy78=1 +phy_rx_polarity_flip_phy79=0 +phy_tx_polarity_flip_phy79=1 +phy_rx_polarity_flip_phy80=1 +phy_tx_polarity_flip_phy80=1 +phy_rx_polarity_flip_phy81=0 +phy_tx_polarity_flip_phy81=0 +phy_rx_polarity_flip_phy82=0 +phy_tx_polarity_flip_phy82=1 +phy_rx_polarity_flip_phy83=0 +phy_tx_polarity_flip_phy83=1 +phy_rx_polarity_flip_phy84=1 +phy_tx_polarity_flip_phy84=0 +phy_rx_polarity_flip_phy85=0 +phy_tx_polarity_flip_phy85=0 +phy_rx_polarity_flip_phy86=0 +phy_tx_polarity_flip_phy86=1 +phy_rx_polarity_flip_phy87=1 +phy_tx_polarity_flip_phy87=1 +phy_rx_polarity_flip_phy88=1 +phy_tx_polarity_flip_phy88=0 +phy_rx_polarity_flip_phy89=0 +phy_tx_polarity_flip_phy89=1 +phy_rx_polarity_flip_phy90=0 +phy_tx_polarity_flip_phy90=0 +phy_rx_polarity_flip_phy91=1 +phy_tx_polarity_flip_phy91=1 +phy_rx_polarity_flip_phy92=0 +phy_tx_polarity_flip_phy92=1 +phy_rx_polarity_flip_phy93=0 +phy_tx_polarity_flip_phy93=1 +phy_rx_polarity_flip_phy94=0 +phy_tx_polarity_flip_phy94=1 +phy_rx_polarity_flip_phy95=1 +phy_tx_polarity_flip_phy95=1 +phy_rx_polarity_flip_phy96=1 +phy_tx_polarity_flip_phy96=0 +phy_rx_polarity_flip_phy97=0 +phy_tx_polarity_flip_phy97=1 +phy_rx_polarity_flip_phy98=0 +phy_tx_polarity_flip_phy98=0 +phy_rx_polarity_flip_phy99=0 +phy_tx_polarity_flip_phy99=0 +phy_rx_polarity_flip_phy100=1 +phy_tx_polarity_flip_phy100=1 +phy_rx_polarity_flip_phy101=1 +phy_tx_polarity_flip_phy101=1 +phy_rx_polarity_flip_phy102=0 +phy_tx_polarity_flip_phy102=0 +phy_rx_polarity_flip_phy103=0 +phy_tx_polarity_flip_phy103=0 +phy_rx_polarity_flip_phy104=1 +phy_tx_polarity_flip_phy104=1 +phy_rx_polarity_flip_phy105=0 +phy_tx_polarity_flip_phy105=1 +phy_rx_polarity_flip_phy106=1 +phy_tx_polarity_flip_phy106=1 +phy_rx_polarity_flip_phy107=1 +phy_tx_polarity_flip_phy107=0 +phy_rx_polarity_flip_phy108=1 +phy_tx_polarity_flip_phy108=1 +phy_rx_polarity_flip_phy109=0 +phy_tx_polarity_flip_phy109=1 +phy_rx_polarity_flip_phy110=1 +phy_tx_polarity_flip_phy110=0 +phy_rx_polarity_flip_phy111=1 +phy_tx_polarity_flip_phy111=0 +phy_rx_polarity_flip_phy112=1 +phy_tx_polarity_flip_phy112=1 +phy_rx_polarity_flip_phy113=0 +phy_tx_polarity_flip_phy113=0 +phy_rx_polarity_flip_phy114=0 +phy_tx_polarity_flip_phy114=1 +phy_rx_polarity_flip_phy115=0 +phy_tx_polarity_flip_phy115=0 +phy_rx_polarity_flip_phy116=1 +phy_tx_polarity_flip_phy116=0 +phy_rx_polarity_flip_phy117=0 +phy_tx_polarity_flip_phy117=0 +phy_rx_polarity_flip_phy118=0 +phy_tx_polarity_flip_phy118=0 +phy_rx_polarity_flip_phy119=0 +phy_tx_polarity_flip_phy119=0 +phy_rx_polarity_flip_phy120=0 +phy_tx_polarity_flip_phy120=1 +phy_rx_polarity_flip_phy121=0 +phy_tx_polarity_flip_phy121=0 +phy_rx_polarity_flip_phy122=1 +phy_tx_polarity_flip_phy122=1 +phy_rx_polarity_flip_phy123=1 +phy_tx_polarity_flip_phy123=1 +phy_rx_polarity_flip_phy124=0 +phy_tx_polarity_flip_phy124=0 +phy_rx_polarity_flip_phy125=1 +phy_tx_polarity_flip_phy125=0 +phy_rx_polarity_flip_phy126=0 +phy_tx_polarity_flip_phy126=1 +phy_rx_polarity_flip_phy127=1 +phy_tx_polarity_flip_phy127=1 +phy_rx_polarity_flip_phy128=1 +phy_tx_polarity_flip_phy128=0 +phy_rx_polarity_flip_phy129=0 +phy_tx_polarity_flip_phy129=1 +phy_rx_polarity_flip_phy130=0 +phy_tx_polarity_flip_phy130=0 +phy_rx_polarity_flip_phy131=0 +phy_tx_polarity_flip_phy131=0 +phy_rx_polarity_flip_phy132=1 +phy_tx_polarity_flip_phy132=1 +phy_rx_polarity_flip_phy133=0 +phy_tx_polarity_flip_phy133=1 +phy_rx_polarity_flip_phy134=0 +phy_tx_polarity_flip_phy134=0 +phy_rx_polarity_flip_phy135=1 +phy_tx_polarity_flip_phy135=0 +phy_rx_polarity_flip_phy136=1 +phy_tx_polarity_flip_phy136=0 +phy_rx_polarity_flip_phy137=1 +phy_tx_polarity_flip_phy137=1 +phy_rx_polarity_flip_phy138=1 +phy_tx_polarity_flip_phy138=0 +phy_rx_polarity_flip_phy139=0 +phy_tx_polarity_flip_phy139=1 +phy_rx_polarity_flip_phy140=1 +phy_tx_polarity_flip_phy140=1 +phy_rx_polarity_flip_phy141=0 +phy_tx_polarity_flip_phy141=1 +phy_rx_polarity_flip_phy142=1 +phy_tx_polarity_flip_phy142=1 +phy_rx_polarity_flip_phy143=0 +phy_tx_polarity_flip_phy143=1 +phy_rx_polarity_flip_phy64=0 +phy_tx_polarity_flip_phy64=0 +phy_rx_polarity_flip_phy65=1 +phy_tx_polarity_flip_phy65=1 +phy_rx_polarity_flip_phy66=1 +phy_tx_polarity_flip_phy66=0 +phy_rx_polarity_flip_phy67=1 +phy_tx_polarity_flip_phy67=1 +phy_rx_polarity_flip_phy68=0 +phy_tx_polarity_flip_phy68=1 +phy_rx_polarity_flip_phy69=1 +phy_tx_polarity_flip_phy69=1 +phy_rx_polarity_flip_phy70=1 +phy_tx_polarity_flip_phy70=1 +phy_rx_polarity_flip_phy71=1 +phy_tx_polarity_flip_phy71=1 +phy_rx_polarity_flip_phy56=0 +phy_tx_polarity_flip_phy56=0 +phy_rx_polarity_flip_phy57=1 +phy_tx_polarity_flip_phy57=0 +phy_rx_polarity_flip_phy58=0 +phy_tx_polarity_flip_phy58=0 +phy_rx_polarity_flip_phy59=0 +phy_tx_polarity_flip_phy59=1 +phy_rx_polarity_flip_phy60=0 +phy_tx_polarity_flip_phy60=0 +phy_rx_polarity_flip_phy61=0 +phy_tx_polarity_flip_phy61=0 +phy_rx_polarity_flip_phy62=1 +phy_tx_polarity_flip_phy62=1 +phy_rx_polarity_flip_phy63=0 +phy_tx_polarity_flip_phy63=1 +phy_rx_polarity_flip_phy48=0 +phy_tx_polarity_flip_phy48=1 +phy_rx_polarity_flip_phy49=1 +phy_tx_polarity_flip_phy49=0 +phy_rx_polarity_flip_phy50=1 +phy_tx_polarity_flip_phy50=1 +phy_rx_polarity_flip_phy51=1 +phy_tx_polarity_flip_phy51=1 +phy_rx_polarity_flip_phy52=0 +phy_tx_polarity_flip_phy52=0 +phy_rx_polarity_flip_phy53=0 +phy_tx_polarity_flip_phy53=0 +phy_rx_polarity_flip_phy54=1 +phy_tx_polarity_flip_phy54=1 +phy_rx_polarity_flip_phy55=1 +phy_tx_polarity_flip_phy55=1 +phy_rx_polarity_flip_phy40=0 +phy_tx_polarity_flip_phy40=1 +phy_rx_polarity_flip_phy41=1 +phy_tx_polarity_flip_phy41=0 +phy_rx_polarity_flip_phy42=0 +phy_tx_polarity_flip_phy42=1 +phy_rx_polarity_flip_phy43=0 +phy_tx_polarity_flip_phy43=0 +phy_rx_polarity_flip_phy44=0 +phy_tx_polarity_flip_phy44=0 +phy_rx_polarity_flip_phy45=1 +phy_tx_polarity_flip_phy45=0 +phy_rx_polarity_flip_phy46=1 +phy_tx_polarity_flip_phy46=0 +phy_rx_polarity_flip_phy47=0 +phy_tx_polarity_flip_phy47=0 +phy_rx_polarity_flip_phy32=0 +phy_tx_polarity_flip_phy32=1 +phy_rx_polarity_flip_phy33=1 +phy_tx_polarity_flip_phy33=0 +phy_rx_polarity_flip_phy34=1 +phy_tx_polarity_flip_phy34=1 +phy_rx_polarity_flip_phy35=1 +phy_tx_polarity_flip_phy35=1 +phy_rx_polarity_flip_phy36=0 +phy_tx_polarity_flip_phy36=0 +phy_rx_polarity_flip_phy37=1 +phy_tx_polarity_flip_phy37=0 +phy_rx_polarity_flip_phy38=1 +phy_tx_polarity_flip_phy38=1 +phy_rx_polarity_flip_phy39=0 +phy_tx_polarity_flip_phy39=1 +phy_rx_polarity_flip_phy24=1 +phy_tx_polarity_flip_phy24=0 +phy_rx_polarity_flip_phy25=1 +phy_tx_polarity_flip_phy25=0 +phy_rx_polarity_flip_phy26=0 +phy_tx_polarity_flip_phy26=0 +phy_rx_polarity_flip_phy27=0 +phy_tx_polarity_flip_phy27=1 +phy_rx_polarity_flip_phy28=1 +phy_tx_polarity_flip_phy28=0 +phy_rx_polarity_flip_phy29=0 +phy_tx_polarity_flip_phy29=0 +phy_rx_polarity_flip_phy30=1 +phy_tx_polarity_flip_phy30=1 +phy_rx_polarity_flip_phy31=0 +phy_tx_polarity_flip_phy31=1 +phy_rx_polarity_flip_phy16=0 +phy_tx_polarity_flip_phy16=0 +phy_rx_polarity_flip_phy17=1 +phy_tx_polarity_flip_phy17=1 +phy_rx_polarity_flip_phy18=1 +phy_tx_polarity_flip_phy18=0 +phy_rx_polarity_flip_phy19=1 +phy_tx_polarity_flip_phy19=1 +phy_rx_polarity_flip_phy20=0 +phy_tx_polarity_flip_phy20=1 +phy_rx_polarity_flip_phy21=1 +phy_tx_polarity_flip_phy21=1 +phy_rx_polarity_flip_phy22=1 +phy_tx_polarity_flip_phy22=1 +phy_rx_polarity_flip_phy23=1 +phy_tx_polarity_flip_phy23=1 +phy_rx_polarity_flip_phy8=0 +phy_tx_polarity_flip_phy8=1 +phy_rx_polarity_flip_phy9=1 +phy_tx_polarity_flip_phy9=1 +phy_rx_polarity_flip_phy10=0 +phy_tx_polarity_flip_phy10=1 +phy_rx_polarity_flip_phy11=0 +phy_tx_polarity_flip_phy11=0 +phy_rx_polarity_flip_phy12=0 +phy_tx_polarity_flip_phy12=1 +phy_rx_polarity_flip_phy13=0 +phy_tx_polarity_flip_phy13=1 +phy_rx_polarity_flip_phy14=1 +phy_tx_polarity_flip_phy14=0 +phy_rx_polarity_flip_phy15=0 +phy_tx_polarity_flip_phy15=0 +phy_rx_polarity_flip_phy0=1 +phy_tx_polarity_flip_phy0=0 +phy_rx_polarity_flip_phy1=0 +phy_tx_polarity_flip_phy1=1 +phy_rx_polarity_flip_phy2=0 +phy_tx_polarity_flip_phy2=0 +phy_rx_polarity_flip_phy3=0 +phy_tx_polarity_flip_phy3=0 +phy_rx_polarity_flip_phy4=1 +phy_tx_polarity_flip_phy4=1 +phy_rx_polarity_flip_phy5=1 +phy_tx_polarity_flip_phy5=1 +phy_rx_polarity_flip_phy6=0 +phy_tx_polarity_flip_phy6=0 +phy_rx_polarity_flip_phy7=0 +phy_tx_polarity_flip_phy7=0 + +appl_param_nof_ports_per_modid=64 +xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 +xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=4 +sai_pfc_dlr_init_capability=0 +sai_default_cpu_tx_tc=7 +sai_disable_srcmacqedstmac_ctrl=1 diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/pg_profile_lookup.ini b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/pg_profile_lookup.ini new file mode 100644 index 0000000000..ba784705e0 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/pg_profile_lookup.ini @@ -0,0 +1,17 @@ +# PG lossless profiles. +# speed cable size xon xoff threshold xon_offset + 40000 300m 0 2560 69632 -6 181753 + 100000 300m 0 2560 110592 -6 363506 + 400000 300m 0 2560 315392 -5 1454025 + 40000 1000m 0 2560 114688 -6 181753 + 100000 1000m 0 2560 225280 -6 363506 + 400000 1000m 0 2560 778240 -5 1454025 + 40000 2000m 0 2560 184320 -6 181753 + 100000 2000m 0 2560 393216 -6 363506 + 400000 2000m 0 2560 1445888 -5 1454025 + 40000 80000m 0 2560 5369856 -6 181753 + 100000 80000m 0 2560 13357056 -6 363506 + 400000 80000m 0 2560 53305344 -5 1454025 + 40000 120000m 0 2560 8028160 -6 181753 + 100000 120000m 0 2560 20004864 -6 363506 + 400000 120000m 0 2560 79900672 -5 1454025 diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/port_config.ini b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/port_config.ini new file mode 100644 index 0000000000..39b6b1de02 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/port_config.ini @@ -0,0 +1,21 @@ +# name lanes alias index role speed asic_port_name core_id core_port_id num_voq +Ethernet0 72,73,74,75,76,77,78,79 Ethernet1/1 1 Ext 400000 Eth0 1 1 8 +Ethernet8 80,81,82,83,84,85,86,87 Ethernet2/1 2 Ext 400000 Eth8 1 2 8 +Ethernet16 88,89,90,91,92,93,94,95 Ethernet3/1 3 Ext 400000 Eth16 1 3 8 +Ethernet24 96,97,98,99,100,101,102,103 Ethernet4/1 4 Ext 400000 Eth24 1 4 8 +Ethernet32 104,105,106,107,108,109,110,111 Ethernet5/1 5 Ext 400000 Eth32 1 5 8 +Ethernet40 112,113,114,115,116,117,118,119 Ethernet6/1 6 Ext 400000 Eth40 1 6 8 +Ethernet48 120,121,122,123,124,125,126,127 Ethernet7/1 7 Ext 400000 Eth48 1 7 8 +Ethernet56 128,129,130,131,132,133,134,135 Ethernet8/1 8 Ext 400000 Eth56 1 8 8 +Ethernet64 136,137,138,139,140,141,142,143 Ethernet9/1 9 Ext 400000 Eth64 1 9 8 +Ethernet72 64,65,66,67,68,69,70,71 Ethernet10/1 10 Ext 400000 Eth72 0 10 8 +Ethernet80 56,57,58,59,60,61,62,63 Ethernet11/1 11 Ext 400000 Eth80 0 11 8 +Ethernet88 48,49,50,51,52,53,54,55 Ethernet12/1 12 Ext 400000 Eth88 0 12 8 +Ethernet96 40,41,42,43,44,45,46,47 Ethernet13/1 13 Ext 400000 Eth96 0 13 8 +Ethernet104 32,33,34,35,36,37,38,39 Ethernet14/1 14 Ext 400000 Eth104 0 14 8 +Ethernet112 24,25,26,27,28,29,30,31 Ethernet15/1 15 Ext 400000 Eth112 0 15 8 +Ethernet120 16,17,18,19,20,21,22,23 Ethernet16/1 16 Ext 400000 Eth120 0 16 8 +Ethernet128 8,9,10,11,12,13,14,15 Ethernet17/1 17 Ext 400000 Eth128 0 17 8 +Ethernet136 0,1,2,3,4,5,6,7 Ethernet18/1 18 Ext 400000 Eth136 0 18 8 +Ethernet-Rec0 249 Recirc0/0 37 Rec 400000 Rcy0 0 49 8 +Ethernet-IB0 250 Recirc0/1 38 Inb 400000 Rcy1 1 50 8 diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/qos.json.j2 b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/qos.json.j2 new file mode 100644 index 0000000000..411942ab52 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/qos.json.j2 @@ -0,0 +1,21 @@ +{%- macro generate_wred_profiles() %} + "WRED_PROFILE": { + "AZURE_LOSSLESS" : { + "wred_green_enable" : "true", + "wred_yellow_enable" : "true", + "wred_red_enable" : "true", + "ecn" : "ecn_all", + "green_max_threshold" : "10000000", + "green_min_threshold" : "2000000", + "yellow_max_threshold" : "10000000", + "yellow_min_threshold" : "2000000", + "red_max_threshold" : "10000000", + "red_min_threshold" : "2000000", + "green_drop_probability" : "5", + "yellow_drop_probability": "5", + "red_drop_probability" : "5" + } + }, +{%- endmacro %} + +{%- include 'qos_config.j2' %} diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/sai.profile b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/sai.profile new file mode 100644 index 0000000000..a84cf899d8 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/0/sai.profile @@ -0,0 +1 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/jr2p-a7280dra3-36-36x400G.config.bcm diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/buffers.json.j2 b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/buffers.json.j2 new file mode 120000 index 0000000000..a1d8e80782 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/buffers.json.j2 @@ -0,0 +1 @@ +../0/buffers.json.j2 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/buffers_defaults_t2.j2 b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/buffers_defaults_t2.j2 new file mode 100644 index 0000000000..323e909e22 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/buffers_defaults_t2.j2 @@ -0,0 +1,49 @@ +{%- set default_cable = '300m' %} + +{%- set ports2cable = { + 'torrouter_server' : '300m', + 'leafrouter_torrouter' : '300m', + 'spinerouter_leafrouter' : '2000m', + 'upperspinerouter_spinerouter' : '50m', + 'regionalhub_upperspinerouter': '120000m', + 'aznghub_upperspinerouter' : '120000m', + 'regionalhub_spinerouter': '120000m', + 'aznghub_spinerouter' : '120000m' + } +-%} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(144,288,8) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "6441610000", + "type": "both", + "mode": "dynamic", + "xoff": "792476467" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "xon_offset": "0", + "dynamic_th":"0" + }, + "egress_lossless_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "dynamic_th":"-1" + }, + "egress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "dynamic_th":"-4" + } + }, +{%- endmacro %} diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/context_config.json b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/context_config.json new file mode 120000 index 0000000000..3db0e8ed3d --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/context_config.json @@ -0,0 +1 @@ +../0/context_config.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/jr2p-a7280dra3-36-36x400G.config.bcm b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/jr2p-a7280dra3-36-36x400G.config.bcm new file mode 100644 index 0000000000..998c4e3320 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/jr2p-a7280dra3-36-36x400G.config.bcm @@ -0,0 +1,986 @@ +soc_family=BCM8885X +system_ref_core_clock_khz=1600000 + +dpp_db_path=/usr/share/bcm/db +programmability_ucode_relative_path.BCM8885X=pemla/ucode/standard_1/jer2pemla/u_code_db2pem.txt + +#################################################### +##Reference applications related properties - Start +#################################################### + +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +pmf_sexem3_stage=IPMF2 + +#################################################### +##Reference applications related properties - End +#################################################### + +# Jericho2-mode (description 0x1 used for Jericho 2 mode) +system_headers_mode=1 + +# HW mode to support 1024 16-member system wide LAGs +trunk_group_max_members=16 + +# Disable link-training +port_init_cl72=0 + +###Default interfaces for Jericho2Plus +#CPU interfaces +ucode_port_0=CPU.0:core_0.0 +ucode_port_200=CPU.8:core_1.200 +ucode_port_201=CPU.16:core_0.201 +ucode_port_202=CPU.24:core_1.202 +ucode_port_203=CPU.32:core_0.203 + +#NIF ETH interfaces on device +ucode_port_1=CDGE1:core_0.1 +ucode_port_2=CDGE0:core_0.2 +ucode_port_3=CDGE3:core_0.3 +ucode_port_4=CDGE2:core_0.4 +ucode_port_5=CDGE5:core_0.5 +ucode_port_6=CDGE4:core_0.6 +ucode_port_7=CDGE7:core_0.7 +ucode_port_8=CDGE6:core_0.8 +ucode_port_9=CDGE17:core_1.9 +ucode_port_10=CDGE8:core_0.10 +ucode_port_11=CDGE15:core_1.11 +ucode_port_12=CDGE16:core_1.12 +ucode_port_13=CDGE13:core_1.13 +ucode_port_14=CDGE14:core_1.14 +ucode_port_15=CDGE11:core_1.15 +ucode_port_16=CDGE12:core_1.16 +ucode_port_17=CDGE9:core_1.17 +ucode_port_18=CDGE10:core_1.18 + +#NIF default speeds +port_init_speed_xe=10000 +port_init_speed_xl=40000 +port_init_speed_le=50000 +port_init_speed_ce=100000 +port_init_speed_cc=200000 +port_init_speed_cd=400000 +port_init_speed_il=10312 + +port_priorities=8 + +#special ports +ucode_port_240=OLP:core_0.240 + +# NIF lane mapping +lane_to_serdes_map_nif_lane0=rx3:tx5 +lane_to_serdes_map_nif_lane1=rx7:tx0 +lane_to_serdes_map_nif_lane2=rx6:tx7 +lane_to_serdes_map_nif_lane3=rx5:tx3 +lane_to_serdes_map_nif_lane4=rx0:tx6 +lane_to_serdes_map_nif_lane5=rx4:tx4 +lane_to_serdes_map_nif_lane6=rx1:tx1 +lane_to_serdes_map_nif_lane7=rx2:tx2 +lane_to_serdes_map_nif_lane8=rx14:tx12 +lane_to_serdes_map_nif_lane9=rx9:tx8 +lane_to_serdes_map_nif_lane10=rx15:tx9 +lane_to_serdes_map_nif_lane11=rx10:tx10 +lane_to_serdes_map_nif_lane12=rx12:tx14 +lane_to_serdes_map_nif_lane13=rx8:tx11 +lane_to_serdes_map_nif_lane14=rx13:tx15 +lane_to_serdes_map_nif_lane15=rx11:tx13 +lane_to_serdes_map_nif_lane16=rx18:tx19 +lane_to_serdes_map_nif_lane17=rx22:tx22 +lane_to_serdes_map_nif_lane18=rx21:tx17 +lane_to_serdes_map_nif_lane19=rx23:tx16 +lane_to_serdes_map_nif_lane20=rx16:tx21 +lane_to_serdes_map_nif_lane21=rx19:tx18 +lane_to_serdes_map_nif_lane22=rx17:tx23 +lane_to_serdes_map_nif_lane23=rx20:tx20 +lane_to_serdes_map_nif_lane24=rx31:tx24 +lane_to_serdes_map_nif_lane25=rx26:tx30 +lane_to_serdes_map_nif_lane26=rx30:tx28 +lane_to_serdes_map_nif_lane27=rx25:tx29 +lane_to_serdes_map_nif_lane28=rx27:tx27 +lane_to_serdes_map_nif_lane29=rx24:tx31 +lane_to_serdes_map_nif_lane30=rx28:tx26 +lane_to_serdes_map_nif_lane31=rx29:tx25 +lane_to_serdes_map_nif_lane32=rx34:tx36 +lane_to_serdes_map_nif_lane33=rx38:tx33 +lane_to_serdes_map_nif_lane34=rx37:tx34 +lane_to_serdes_map_nif_lane35=rx39:tx32 +lane_to_serdes_map_nif_lane36=rx33:tx35 +lane_to_serdes_map_nif_lane37=rx36:tx37 +lane_to_serdes_map_nif_lane38=rx32:tx38 +lane_to_serdes_map_nif_lane39=rx35:tx39 +lane_to_serdes_map_nif_lane40=rx47:tx44 +lane_to_serdes_map_nif_lane41=rx42:tx46 +lane_to_serdes_map_nif_lane42=rx46:tx47 +lane_to_serdes_map_nif_lane43=rx40:tx42 +lane_to_serdes_map_nif_lane44=rx44:tx41 +lane_to_serdes_map_nif_lane45=rx41:tx45 +lane_to_serdes_map_nif_lane46=rx43:tx40 +lane_to_serdes_map_nif_lane47=rx45:tx43 +lane_to_serdes_map_nif_lane48=rx50:tx49 +lane_to_serdes_map_nif_lane49=rx55:tx54 +lane_to_serdes_map_nif_lane50=rx53:tx51 +lane_to_serdes_map_nif_lane51=rx54:tx48 +lane_to_serdes_map_nif_lane52=rx48:tx50 +lane_to_serdes_map_nif_lane53=rx51:tx53 +lane_to_serdes_map_nif_lane54=rx49:tx55 +lane_to_serdes_map_nif_lane55=rx52:tx52 +lane_to_serdes_map_nif_lane56=rx62:tx56 +lane_to_serdes_map_nif_lane57=rx58:tx62 +lane_to_serdes_map_nif_lane58=rx63:tx63 +lane_to_serdes_map_nif_lane59=rx56:tx61 +lane_to_serdes_map_nif_lane60=rx60:tx58 +lane_to_serdes_map_nif_lane61=rx57:tx60 +lane_to_serdes_map_nif_lane62=rx59:tx57 +lane_to_serdes_map_nif_lane63=rx61:tx59 +lane_to_serdes_map_nif_lane64=rx66:tx67 +lane_to_serdes_map_nif_lane65=rx70:tx64 +lane_to_serdes_map_nif_lane66=rx69:tx65 +lane_to_serdes_map_nif_lane67=rx71:tx68 +lane_to_serdes_map_nif_lane68=rx64:tx66 +lane_to_serdes_map_nif_lane69=rx67:tx70 +lane_to_serdes_map_nif_lane70=rx65:tx69 +lane_to_serdes_map_nif_lane71=rx68:tx71 +lane_to_serdes_map_nif_lane72=rx72:tx74 +lane_to_serdes_map_nif_lane73=rx78:tx78 +lane_to_serdes_map_nif_lane74=rx73:tx75 +lane_to_serdes_map_nif_lane75=rx77:tx76 +lane_to_serdes_map_nif_lane76=rx76:tx73 +lane_to_serdes_map_nif_lane77=rx79:tx79 +lane_to_serdes_map_nif_lane78=rx74:tx72 +lane_to_serdes_map_nif_lane79=rx75:tx77 +lane_to_serdes_map_nif_lane80=rx83:tx83 +lane_to_serdes_map_nif_lane81=rx80:tx81 +lane_to_serdes_map_nif_lane82=rx81:tx80 +lane_to_serdes_map_nif_lane83=rx82:tx84 +lane_to_serdes_map_nif_lane84=rx86:tx82 +lane_to_serdes_map_nif_lane85=rx84:tx85 +lane_to_serdes_map_nif_lane86=rx87:tx86 +lane_to_serdes_map_nif_lane87=rx85:tx87 +lane_to_serdes_map_nif_lane88=rx89:tx92 +lane_to_serdes_map_nif_lane89=rx93:tx89 +lane_to_serdes_map_nif_lane90=rx88:tx88 +lane_to_serdes_map_nif_lane91=rx94:tx91 +lane_to_serdes_map_nif_lane92=rx92:tx94 +lane_to_serdes_map_nif_lane93=rx95:tx90 +lane_to_serdes_map_nif_lane94=rx91:tx95 +lane_to_serdes_map_nif_lane95=rx90:tx93 +lane_to_serdes_map_nif_lane96=rx101:tx102 +lane_to_serdes_map_nif_lane97=rx96:tx99 +lane_to_serdes_map_nif_lane98=rx98:tx103 +lane_to_serdes_map_nif_lane99=rx97:tx100 +lane_to_serdes_map_nif_lane100=rx103:tx101 +lane_to_serdes_map_nif_lane101=rx99:tx98 +lane_to_serdes_map_nif_lane102=rx102:tx97 +lane_to_serdes_map_nif_lane103=rx100:tx96 +lane_to_serdes_map_nif_lane104=rx105:tx104 +lane_to_serdes_map_nif_lane105=rx109:tx106 +lane_to_serdes_map_nif_lane106=rx104:tx105 +lane_to_serdes_map_nif_lane107=rx111:tx107 +lane_to_serdes_map_nif_lane108=rx108:tx110 +lane_to_serdes_map_nif_lane109=rx110:tx108 +lane_to_serdes_map_nif_lane110=rx107:tx111 +lane_to_serdes_map_nif_lane111=rx106:tx109 +lane_to_serdes_map_nif_lane112=rx117:tx118 +lane_to_serdes_map_nif_lane113=rx112:tx119 +lane_to_serdes_map_nif_lane114=rx114:tx117 +lane_to_serdes_map_nif_lane115=rx113:tx116 +lane_to_serdes_map_nif_lane116=rx118:tx114 +lane_to_serdes_map_nif_lane117=rx115:tx115 +lane_to_serdes_map_nif_lane118=rx119:tx113 +lane_to_serdes_map_nif_lane119=rx116:tx112 +lane_to_serdes_map_nif_lane120=rx120:tx124 +lane_to_serdes_map_nif_lane121=rx125:tx122 +lane_to_serdes_map_nif_lane122=rx121:tx120 +lane_to_serdes_map_nif_lane123=rx126:tx125 +lane_to_serdes_map_nif_lane124=rx123:tx127 +lane_to_serdes_map_nif_lane125=rx127:tx123 +lane_to_serdes_map_nif_lane126=rx124:tx126 +lane_to_serdes_map_nif_lane127=rx122:tx121 +lane_to_serdes_map_nif_lane128=rx133:tx132 +lane_to_serdes_map_nif_lane129=rx129:tx135 +lane_to_serdes_map_nif_lane130=rx130:tx134 +lane_to_serdes_map_nif_lane131=rx128:tx128 +lane_to_serdes_map_nif_lane132=rx134:tx133 +lane_to_serdes_map_nif_lane133=rx132:tx131 +lane_to_serdes_map_nif_lane134=rx135:tx130 +lane_to_serdes_map_nif_lane135=rx131:tx129 +lane_to_serdes_map_nif_lane136=rx137:tx140 +lane_to_serdes_map_nif_lane137=rx141:tx139 +lane_to_serdes_map_nif_lane138=rx136:tx136 +lane_to_serdes_map_nif_lane139=rx142:tx138 +lane_to_serdes_map_nif_lane140=rx140:tx141 +lane_to_serdes_map_nif_lane141=rx143:tx137 +lane_to_serdes_map_nif_lane142=rx139:tx143 +lane_to_serdes_map_nif_lane143=rx138:tx142 + +######################### +### High Availability ### +######################### + +sw_state_max_size=750000000 + +#location of warmboot NV memory +#Allowed options for dnx are - 3:external storage in filesystem 4:driver will save the state directly in shared memory +stable_location=4 + +# Note that each unit should have a unique filename and that adapter does not play well with tmp and dev/shm folders. +stable_filename=/dev/shm/warmboot_data_0 +stable_filename.1=/dev/shm/warmboot_data_1 +stable_filename.2=/dev/shm/warmboot_data_2 + +#Maximum size for NVM used for WB storage, must be larger than sw_state_max_size.BCM8885X +stable_size=800000000 + +######################### +######################### +######################### + +tm_port_header_type_in_0=INJECTED_2_PP +tm_port_header_type_out_0=CPU + +tm_port_header_type_in_200=INJECTED_2_PP +tm_port_header_type_out_200=ETH +tm_port_header_type_in_201=INJECTED_2_PP +tm_port_header_type_out_201=ETH +tm_port_header_type_in_202=INJECTED_2_PP +tm_port_header_type_out_202=ETH +tm_port_header_type_in_203=INJECTED_2_PP +tm_port_header_type_out_203=ETH + +### RCY +sai_recycle_port_lane_base=200 +ucode_port_49=RCY0:core_0.49 +ucode_port_50=RCY1:core_1.50 +tm_port_header_type_out_49=ETH +tm_port_header_type_in_49=ETH +tm_port_header_type_out_50=ETH +tm_port_header_type_in_50=ETH +port_init_speed_49=400000 +port_init_speed_50=400000 +ucode_port_100.BCM8885X=RCY_MIRROR.0:core_0.100 +ucode_port_101.BCM8885X=RCY_MIRROR.1:core_0.101 +ucode_port_102.BCM8885X=RCY_MIRROR.2:core_0.102 +ucode_port_103.BCM8885X=RCY_MIRROR.3:core_0.103 +ucode_port_104.BCM8885X=RCY_MIRROR.4:core_0.104 +ucode_port_105.BCM8885X=RCY_MIRROR.5:core_0.105 +ucode_port_106.BCM8885X=RCY_MIRROR.6:core_0.106 +ucode_port_107.BCM8885X=RCY_MIRROR.7:core_0.107 +ucode_port_108.BCM8885X=RCY_MIRROR.8:core_0.108 +ucode_port_109.BCM8885X=RCY_MIRROR.9:core_0.109 +ucode_port_110.BCM8885X=RCY_MIRROR.10:core_0.110 +ucode_port_111.BCM8885X=RCY_MIRROR.11:core_0.111 +ucode_port_112.BCM8885X=RCY_MIRROR.12:core_0.112 +ucode_port_113.BCM8885X=RCY_MIRROR.13:core_0.113 +ucode_port_114.BCM8885X=RCY_MIRROR.14:core_0.114 +ucode_port_115.BCM8885X=RCY_MIRROR.15:core_0.115 +ucode_port_116.BCM8885X=RCY_MIRROR.16:core_0.116 +ucode_port_117.BCM8885X=RCY_MIRROR.17:core_0.117 +ucode_port_118.BCM8885X=RCY_MIRROR.18:core_0.118 +ucode_port_119.BCM8885X=RCY_MIRROR.19:core_0.119 +ucode_port_120.BCM8885X=RCY_MIRROR.0:core_1.120 +ucode_port_121.BCM8885X=RCY_MIRROR.1:core_1.121 +ucode_port_122.BCM8885X=RCY_MIRROR.2:core_1.122 +ucode_port_123.BCM8885X=RCY_MIRROR.3:core_1.123 +ucode_port_124.BCM8885X=RCY_MIRROR.4:core_1.124 +ucode_port_125.BCM8885X=RCY_MIRROR.5:core_1.125 +ucode_port_126.BCM8885X=RCY_MIRROR.6:core_1.126 +ucode_port_127.BCM8885X=RCY_MIRROR.7:core_1.127 +ucode_port_128.BCM8885X=RCY_MIRROR.8:core_1.128 +ucode_port_129.BCM8885X=RCY_MIRROR.9:core_1.129 +ucode_port_130.BCM8885X=RCY_MIRROR.10:core_1.130 +ucode_port_131.BCM8885X=RCY_MIRROR.11:core_1.131 +ucode_port_132.BCM8885X=RCY_MIRROR.12:core_1.132 +ucode_port_133.BCM8885X=RCY_MIRROR.13:core_1.133 +ucode_port_134.BCM8885X=RCY_MIRROR.14:core_1.134 +ucode_port_135.BCM8885X=RCY_MIRROR.15:core_1.135 +ucode_port_136.BCM8885X=RCY_MIRROR.16:core_1.136 +ucode_port_137.BCM8885X=RCY_MIRROR.17:core_1.137 +ucode_port_138.BCM8885X=RCY_MIRROR.18:core_1.138 +ucode_port_139.BCM8885X=RCY_MIRROR.19:core_1.139 + +#OLP port +tm_port_header_type_in_240=INJECTED_2 +tm_port_header_type_out_240=RAW + +# Set statically the region mode per region id +dtm_flow_mapping_mode_region_257=3 +dtm_flow_mapping_mode_region_258=3 +dtm_flow_mapping_mode_region_259=3 +dtm_flow_mapping_mode_region_260=3 +dtm_flow_mapping_mode_region_261=3 +dtm_flow_mapping_mode_region_262=3 +dtm_flow_mapping_mode_region_263=3 +dtm_flow_mapping_mode_region_264=3 +dtm_flow_mapping_mode_region_265=3 +dtm_flow_mapping_mode_region_266=7 +dtm_flow_mapping_mode_region_267=3 +dtm_flow_mapping_mode_region_268=3 +dtm_flow_mapping_mode_region_269=3 +dtm_flow_mapping_mode_region_270=3 +dtm_flow_mapping_mode_region_271=3 +dtm_flow_mapping_mode_region_272=3 +dtm_flow_mapping_mode_region_273=3 +dtm_flow_mapping_mode_region_274=3 +dtm_flow_mapping_mode_region_275=3 +dtm_flow_mapping_mode_region_276=3 +dtm_flow_mapping_mode_region_277=3 +dtm_flow_mapping_mode_region_278=3 +dtm_flow_mapping_mode_region_279=3 +dtm_flow_mapping_mode_region_280=3 +dtm_flow_mapping_mode_region_281=3 +dtm_flow_mapping_mode_region_282=3 +dtm_flow_mapping_mode_region_283=3 +dtm_flow_mapping_mode_region_284=3 +dtm_flow_mapping_mode_region_285=3 +dtm_flow_mapping_mode_region_286=3 +dtm_flow_mapping_mode_region_287=3 + +## Configure number of symmetric cores each region supports ## +dtm_flow_nof_remote_cores_region_1=2 +dtm_flow_nof_remote_cores_region_2=2 +dtm_flow_nof_remote_cores_region_3=2 +dtm_flow_nof_remote_cores_region_4=2 +dtm_flow_nof_remote_cores_region_5=2 +dtm_flow_nof_remote_cores_region_6=2 +dtm_flow_nof_remote_cores_region_7=2 +dtm_flow_nof_remote_cores_region_8=2 +dtm_flow_nof_remote_cores_region_9=2 +dtm_flow_nof_remote_cores_region_10=2 +dtm_flow_nof_remote_cores_region_11=2 +dtm_flow_nof_remote_cores_region_12=2 +dtm_flow_nof_remote_cores_region_13=2 +dtm_flow_nof_remote_cores_region_14=2 +dtm_flow_nof_remote_cores_region_15=2 +dtm_flow_nof_remote_cores_region_16=2 +dtm_flow_nof_remote_cores_region_17=2 +dtm_flow_nof_remote_cores_region_18=2 +dtm_flow_nof_remote_cores_region_19=2 +dtm_flow_nof_remote_cores_region_20=2 +dtm_flow_nof_remote_cores_region_21=2 +dtm_flow_nof_remote_cores_region_22=2 +dtm_flow_nof_remote_cores_region_23=2 +dtm_flow_nof_remote_cores_region_24=2 +dtm_flow_nof_remote_cores_region_25=2 +dtm_flow_nof_remote_cores_region_26=2 +dtm_flow_nof_remote_cores_region_27=2 +dtm_flow_nof_remote_cores_region_28=2 +dtm_flow_nof_remote_cores_region_29=2 +dtm_flow_nof_remote_cores_region_30=2 +dtm_flow_nof_remote_cores_region_31=2 +dtm_flow_nof_remote_cores_region_32=2 +dtm_flow_nof_remote_cores_region_33=2 +dtm_flow_nof_remote_cores_region_34=2 +dtm_flow_nof_remote_cores_region_35=2 +dtm_flow_nof_remote_cores_region_36=2 +dtm_flow_nof_remote_cores_region_37=2 +dtm_flow_nof_remote_cores_region_38=2 +dtm_flow_nof_remote_cores_region_39=2 +dtm_flow_nof_remote_cores_region_40=2 +dtm_flow_nof_remote_cores_region_41=2 +dtm_flow_nof_remote_cores_region_42=2 +dtm_flow_nof_remote_cores_region_43=2 +dtm_flow_nof_remote_cores_region_44=2 +dtm_flow_nof_remote_cores_region_45=2 +dtm_flow_nof_remote_cores_region_46=2 +dtm_flow_nof_remote_cores_region_47=2 +dtm_flow_nof_remote_cores_region_48=2 +dtm_flow_nof_remote_cores_region_49=2 +dtm_flow_nof_remote_cores_region_50=2 +dtm_flow_nof_remote_cores_region_51=2 +dtm_flow_nof_remote_cores_region_52=2 +dtm_flow_nof_remote_cores_region_53=2 +dtm_flow_nof_remote_cores_region_54=2 +dtm_flow_nof_remote_cores_region_55=2 +dtm_flow_nof_remote_cores_region_56=2 +dtm_flow_nof_remote_cores_region_57=2 +dtm_flow_nof_remote_cores_region_58=2 +dtm_flow_nof_remote_cores_region_59=2 +dtm_flow_nof_remote_cores_region_60=2 + +### MDB configuration ### +mdb_profile=balanced-exem + +### Descriptor-DMA configuration ### +dma_desc_aggregator_chain_length_max=1000 +dma_desc_aggregator_buff_size_kb=100 +dma_desc_aggregator_timeout_usec=1000 +dma_desc_aggregator_enable_specific_MDB_LPM=1 +dma_desc_aggregator_enable_specific_MDB_FEC=1 + +### Outlif configuarion ### +outlif_logical_to_physical_phase_map_1=S1 +outlif_logical_to_physical_phase_map_2=L1 +outlif_logical_to_physical_phase_map_3=XL +outlif_logical_to_physical_phase_map_4=L2 +outlif_logical_to_physical_phase_map_5=M1 +outlif_logical_to_physical_phase_map_6=M2 +outlif_logical_to_physical_phase_map_7=M3 +outlif_logical_to_physical_phase_map_8=S2 + +### Outlif data granularity configuration ### +outlif_physical_phase_data_granularity_S1=60 +outlif_physical_phase_data_granularity_S2=60 +outlif_physical_phase_data_granularity_M1=60 +outlif_physical_phase_data_granularity_M2=60 +outlif_physical_phase_data_granularity_M3=60 +outlif_physical_phase_data_granularity_L1=60 +outlif_physical_phase_data_granularity_L2=60 +outlif_physical_phase_data_granularity_XL=60 + +### Fabric configuration ### +# Enable link-training +port_init_cl72_sfi=1 +serdes_lane_config_cl72_auto_polarity_en=0 +serdes_lane_config_cl72_auto_polarity_en_sfi=1 +serdes_lane_config_cl72_restart_timeout_en=0 + +#SFI speed rate +port_init_speed_fabric=53125 + +## Fabric transmission mode +# Set the Connect mode to the Fabric +# Options: FE - presence of a Fabric device (single stage) +# SINGLE_FAP - stand-alone device +# MESH - devices in Mesh +# Note: If 'diag_chassis' is on, value will be override in dnx.soc +# to be FE instead of SINGLE_FAP. +appl_param_nof_devices.BCM8885X=2 +fabric_connect_mode=MESH +fabric_mesh_multicast_enable=1 +fabric_num_pipes=2 +fabric_pipe_map_uc=0 +fabric_pipe_map_mc=1 +system_contains_multiple_pipe_device=1 +fabric_logical_port_base=450 + +# Fabric lane mapping +lane_to_serdes_map_fabric_lane0=rx0:tx0 +lane_to_serdes_map_fabric_lane1=rx1:tx1 +lane_to_serdes_map_fabric_lane2=rx2:tx2 +lane_to_serdes_map_fabric_lane3=rx3:tx3 +lane_to_serdes_map_fabric_lane4=rx4:tx4 +lane_to_serdes_map_fabric_lane5=rx5:tx5 +lane_to_serdes_map_fabric_lane6=rx6:tx6 +lane_to_serdes_map_fabric_lane7=rx7:tx7 +lane_to_serdes_map_fabric_lane8=rx8:tx8 +lane_to_serdes_map_fabric_lane9=rx9:tx9 +lane_to_serdes_map_fabric_lane10=rx10:tx10 +lane_to_serdes_map_fabric_lane11=rx11:tx11 +lane_to_serdes_map_fabric_lane12=rx12:tx12 +lane_to_serdes_map_fabric_lane13=rx13:tx13 +lane_to_serdes_map_fabric_lane14=rx14:tx14 +lane_to_serdes_map_fabric_lane15=rx15:tx15 +lane_to_serdes_map_fabric_lane16=rx16:tx16 +lane_to_serdes_map_fabric_lane17=rx17:tx17 +lane_to_serdes_map_fabric_lane18=rx18:tx18 +lane_to_serdes_map_fabric_lane19=rx19:tx19 +lane_to_serdes_map_fabric_lane20=rx20:tx20 +lane_to_serdes_map_fabric_lane21=rx21:tx21 +lane_to_serdes_map_fabric_lane22=rx22:tx22 +lane_to_serdes_map_fabric_lane23=rx23:tx23 +lane_to_serdes_map_fabric_lane24=rx24:tx24 +lane_to_serdes_map_fabric_lane25=rx25:tx25 +lane_to_serdes_map_fabric_lane26=rx26:tx26 +lane_to_serdes_map_fabric_lane27=rx27:tx27 +lane_to_serdes_map_fabric_lane28=rx28:tx28 +lane_to_serdes_map_fabric_lane29=rx29:tx29 +lane_to_serdes_map_fabric_lane30=rx30:tx30 +lane_to_serdes_map_fabric_lane31=rx31:tx31 +lane_to_serdes_map_fabric_lane32=rx32:tx32 +lane_to_serdes_map_fabric_lane33=rx33:tx33 +lane_to_serdes_map_fabric_lane34=rx34:tx34 +lane_to_serdes_map_fabric_lane35=rx35:tx35 +lane_to_serdes_map_fabric_lane36=rx36:tx36 +lane_to_serdes_map_fabric_lane37=rx37:tx37 +lane_to_serdes_map_fabric_lane38=rx38:tx38 +lane_to_serdes_map_fabric_lane39=rx39:tx39 +lane_to_serdes_map_fabric_lane40=rx40:tx40 +lane_to_serdes_map_fabric_lane41=rx41:tx41 +lane_to_serdes_map_fabric_lane42=rx42:tx42 +lane_to_serdes_map_fabric_lane43=rx43:tx43 +lane_to_serdes_map_fabric_lane44=rx44:tx44 +lane_to_serdes_map_fabric_lane45=rx45:tx45 +lane_to_serdes_map_fabric_lane46=rx46:tx46 +lane_to_serdes_map_fabric_lane47=rx47:tx47 +lane_to_serdes_map_fabric_lane48=rx48:tx48 +lane_to_serdes_map_fabric_lane49=rx49:tx49 +lane_to_serdes_map_fabric_lane50=rx50:tx50 +lane_to_serdes_map_fabric_lane51=rx51:tx51 +lane_to_serdes_map_fabric_lane52=rx52:tx52 +lane_to_serdes_map_fabric_lane53=rx53:tx53 +lane_to_serdes_map_fabric_lane54=rx54:tx54 +lane_to_serdes_map_fabric_lane55=rx55:tx55 +lane_to_serdes_map_fabric_lane56=rx56:tx56 +lane_to_serdes_map_fabric_lane57=rx57:tx57 +lane_to_serdes_map_fabric_lane58=rx58:tx58 +lane_to_serdes_map_fabric_lane59=rx59:tx59 +lane_to_serdes_map_fabric_lane60=rx60:tx60 +lane_to_serdes_map_fabric_lane61=rx61:tx61 +lane_to_serdes_map_fabric_lane62=rx62:tx62 +lane_to_serdes_map_fabric_lane63=rx63:tx63 +lane_to_serdes_map_fabric_lane64=rx64:tx64 +lane_to_serdes_map_fabric_lane65=rx65:tx65 +lane_to_serdes_map_fabric_lane66=rx66:tx66 +lane_to_serdes_map_fabric_lane67=rx67:tx67 +lane_to_serdes_map_fabric_lane68=rx68:tx68 +lane_to_serdes_map_fabric_lane69=rx69:tx69 +lane_to_serdes_map_fabric_lane70=rx70:tx70 +lane_to_serdes_map_fabric_lane71=rx71:tx71 +lane_to_serdes_map_fabric_lane72=rx72:tx72 +lane_to_serdes_map_fabric_lane73=rx73:tx73 +lane_to_serdes_map_fabric_lane74=rx74:tx74 +lane_to_serdes_map_fabric_lane75=rx75:tx75 +lane_to_serdes_map_fabric_lane76=rx76:tx76 +lane_to_serdes_map_fabric_lane77=rx77:tx77 +lane_to_serdes_map_fabric_lane78=rx78:tx78 +lane_to_serdes_map_fabric_lane79=rx79:tx79 +lane_to_serdes_map_fabric_lane80=rx80:tx80 +lane_to_serdes_map_fabric_lane81=rx81:tx81 +lane_to_serdes_map_fabric_lane82=rx82:tx82 +lane_to_serdes_map_fabric_lane83=rx83:tx83 +lane_to_serdes_map_fabric_lane84=rx84:tx84 +lane_to_serdes_map_fabric_lane85=rx85:tx85 +lane_to_serdes_map_fabric_lane86=rx86:tx86 +lane_to_serdes_map_fabric_lane87=rx87:tx87 +lane_to_serdes_map_fabric_lane88=rx88:tx88 +lane_to_serdes_map_fabric_lane89=rx89:tx89 +lane_to_serdes_map_fabric_lane90=rx90:tx90 +lane_to_serdes_map_fabric_lane91=rx91:tx91 +lane_to_serdes_map_fabric_lane92=rx92:tx92 +lane_to_serdes_map_fabric_lane93=rx93:tx93 +lane_to_serdes_map_fabric_lane94=rx94:tx94 +lane_to_serdes_map_fabric_lane95=rx95:tx95 +lane_to_serdes_map_fabric_lane96=rx96:tx96 +lane_to_serdes_map_fabric_lane97=rx97:tx97 +lane_to_serdes_map_fabric_lane98=rx98:tx98 +lane_to_serdes_map_fabric_lane99=rx99:tx99 +lane_to_serdes_map_fabric_lane100=rx100:tx100 +lane_to_serdes_map_fabric_lane101=rx101:tx101 +lane_to_serdes_map_fabric_lane102=rx102:tx102 +lane_to_serdes_map_fabric_lane103=rx103:tx103 +lane_to_serdes_map_fabric_lane104=rx104:tx104 +lane_to_serdes_map_fabric_lane105=rx105:tx105 +lane_to_serdes_map_fabric_lane106=rx106:tx106 +lane_to_serdes_map_fabric_lane107=rx107:tx107 +lane_to_serdes_map_fabric_lane108=rx108:tx108 +lane_to_serdes_map_fabric_lane109=rx109:tx109 +lane_to_serdes_map_fabric_lane110=rx110:tx110 +lane_to_serdes_map_fabric_lane111=rx111:tx111 +lane_to_serdes_map_fabric_lane112=rx112:tx112 +lane_to_serdes_map_fabric_lane113=rx113:tx113 +lane_to_serdes_map_fabric_lane114=rx114:tx114 +lane_to_serdes_map_fabric_lane115=rx115:tx115 +lane_to_serdes_map_fabric_lane116=rx116:tx116 +lane_to_serdes_map_fabric_lane117=rx117:tx117 +lane_to_serdes_map_fabric_lane118=rx118:tx118 +lane_to_serdes_map_fabric_lane119=rx119:tx119 +lane_to_serdes_map_fabric_lane120=rx120:tx120 +lane_to_serdes_map_fabric_lane121=rx121:tx121 +lane_to_serdes_map_fabric_lane122=rx122:tx122 +lane_to_serdes_map_fabric_lane123=rx123:tx123 +lane_to_serdes_map_fabric_lane124=rx124:tx124 +lane_to_serdes_map_fabric_lane125=rx125:tx125 +lane_to_serdes_map_fabric_lane126=rx126:tx126 +lane_to_serdes_map_fabric_lane127=rx127:tx127 +lane_to_serdes_map_fabric_lane128=rx128:tx128 +lane_to_serdes_map_fabric_lane129=rx129:tx129 +lane_to_serdes_map_fabric_lane130=rx130:tx130 +lane_to_serdes_map_fabric_lane131=rx131:tx131 +lane_to_serdes_map_fabric_lane132=rx132:tx132 +lane_to_serdes_map_fabric_lane133=rx133:tx133 +lane_to_serdes_map_fabric_lane134=rx134:tx134 +lane_to_serdes_map_fabric_lane135=rx135:tx135 +lane_to_serdes_map_fabric_lane136=rx136:tx136 +lane_to_serdes_map_fabric_lane137=rx137:tx137 +lane_to_serdes_map_fabric_lane138=rx138:tx138 +lane_to_serdes_map_fabric_lane139=rx139:tx139 +lane_to_serdes_map_fabric_lane140=rx140:tx140 +lane_to_serdes_map_fabric_lane141=rx141:tx141 +lane_to_serdes_map_fabric_lane142=rx142:tx142 +lane_to_serdes_map_fabric_lane143=rx143:tx143 +lane_to_serdes_map_fabric_lane144=rx144:tx144 +lane_to_serdes_map_fabric_lane145=rx145:tx145 +lane_to_serdes_map_fabric_lane146=rx146:tx146 +lane_to_serdes_map_fabric_lane147=rx147:tx147 +lane_to_serdes_map_fabric_lane148=rx148:tx148 +lane_to_serdes_map_fabric_lane149=rx149:tx149 +lane_to_serdes_map_fabric_lane150=rx150:tx150 +lane_to_serdes_map_fabric_lane151=rx151:tx151 +lane_to_serdes_map_fabric_lane152=rx152:tx152 +lane_to_serdes_map_fabric_lane153=rx153:tx153 +lane_to_serdes_map_fabric_lane154=rx154:tx154 +lane_to_serdes_map_fabric_lane155=rx155:tx155 +lane_to_serdes_map_fabric_lane156=rx156:tx156 +lane_to_serdes_map_fabric_lane157=rx157:tx157 +lane_to_serdes_map_fabric_lane158=rx158:tx158 +lane_to_serdes_map_fabric_lane159=rx159:tx159 +lane_to_serdes_map_fabric_lane160=rx160:tx160 +lane_to_serdes_map_fabric_lane161=rx161:tx161 +lane_to_serdes_map_fabric_lane162=rx162:tx162 +lane_to_serdes_map_fabric_lane163=rx163:tx163 +lane_to_serdes_map_fabric_lane164=rx164:tx164 +lane_to_serdes_map_fabric_lane165=rx165:tx165 +lane_to_serdes_map_fabric_lane166=rx166:tx166 +lane_to_serdes_map_fabric_lane167=rx167:tx167 +lane_to_serdes_map_fabric_lane168=rx168:tx168 +lane_to_serdes_map_fabric_lane169=rx169:tx169 +lane_to_serdes_map_fabric_lane170=rx170:tx170 +lane_to_serdes_map_fabric_lane171=rx171:tx171 +lane_to_serdes_map_fabric_lane172=rx172:tx172 +lane_to_serdes_map_fabric_lane173=rx173:tx173 +lane_to_serdes_map_fabric_lane174=rx174:tx174 +lane_to_serdes_map_fabric_lane175=rx175:tx175 +lane_to_serdes_map_fabric_lane176=rx176:tx176 +lane_to_serdes_map_fabric_lane177=rx177:tx177 +lane_to_serdes_map_fabric_lane178=rx178:tx178 +lane_to_serdes_map_fabric_lane179=rx179:tx179 +lane_to_serdes_map_fabric_lane180=rx180:tx180 +lane_to_serdes_map_fabric_lane181=rx181:tx181 +lane_to_serdes_map_fabric_lane182=rx182:tx182 +lane_to_serdes_map_fabric_lane183=rx183:tx183 +lane_to_serdes_map_fabric_lane184=rx184:tx184 +lane_to_serdes_map_fabric_lane185=rx185:tx185 +lane_to_serdes_map_fabric_lane186=rx186:tx186 +lane_to_serdes_map_fabric_lane187=rx187:tx187 +lane_to_serdes_map_fabric_lane188=rx188:tx188 +lane_to_serdes_map_fabric_lane189=rx189:tx189 +lane_to_serdes_map_fabric_lane190=rx190:tx190 +lane_to_serdes_map_fabric_lane191=rx191:tx191 + +# +##Protocol trap look-up mode: +# Options: IN_LIF - Look-ups in the profile table are done by IN-LIF +# IN_PORT - Look-ups in the profile table are done by IN-PORT +protocol_traps_mode=IN_LIF + +# access definitions +schan_intr_enable=0 +tdma_intr_enable=0 +tslam_intr_enable=0 +miim_intr_enable=0 +schan_timeout_usec=300000 +tdma_timeout_usec=1000000 +tslam_timeout_usec=1000000 + +### Interrupts +appl_enable_intr_init=1 +polled_irq_mode=0 +# reduce CPU load, configure delay 100ms +polled_irq_delay=1000 + +# reduce the CPU load over adapter (caused by counter thread) +bcm_stat_interval=1000000 + +# shadow memory +mem_cache_enable_ecc=1 +mem_cache_enable_parity=1 + +# serdes_nif/fabric_clk_freq_in/out configuration +serdes_nif_clk_freq_in=2 +serdes_nif_clk_freq_out=1 +serdes_fabric_clk_freq_in=2 +serdes_fabric_clk_freq_out=1 + +dport_map_direct=1 + +rif_id_max=0x6000 + +phy_rx_polarity_flip_phy8=0 +phy_tx_polarity_flip_phy8=0 +phy_rx_polarity_flip_phy9=1 +phy_tx_polarity_flip_phy9=0 +phy_rx_polarity_flip_phy10=1 +phy_tx_polarity_flip_phy10=0 +phy_rx_polarity_flip_phy11=1 +phy_tx_polarity_flip_phy11=1 +phy_rx_polarity_flip_phy12=0 +phy_tx_polarity_flip_phy12=0 +phy_rx_polarity_flip_phy13=0 +phy_tx_polarity_flip_phy13=0 +phy_rx_polarity_flip_phy14=1 +phy_tx_polarity_flip_phy14=0 +phy_rx_polarity_flip_phy15=1 +phy_tx_polarity_flip_phy15=1 +phy_rx_polarity_flip_phy0=0 +phy_tx_polarity_flip_phy0=0 +phy_rx_polarity_flip_phy1=1 +phy_tx_polarity_flip_phy1=1 +phy_rx_polarity_flip_phy2=0 +phy_tx_polarity_flip_phy2=0 +phy_rx_polarity_flip_phy3=0 +phy_tx_polarity_flip_phy3=1 +phy_rx_polarity_flip_phy4=1 +phy_tx_polarity_flip_phy4=1 +phy_rx_polarity_flip_phy5=1 +phy_tx_polarity_flip_phy5=1 +phy_rx_polarity_flip_phy6=0 +phy_tx_polarity_flip_phy6=0 +phy_rx_polarity_flip_phy7=0 +phy_tx_polarity_flip_phy7=1 +phy_rx_polarity_flip_phy24=0 +phy_tx_polarity_flip_phy24=1 +phy_rx_polarity_flip_phy25=1 +phy_tx_polarity_flip_phy25=0 +phy_rx_polarity_flip_phy26=1 +phy_tx_polarity_flip_phy26=1 +phy_rx_polarity_flip_phy27=1 +phy_tx_polarity_flip_phy27=0 +phy_rx_polarity_flip_phy28=0 +phy_tx_polarity_flip_phy28=1 +phy_rx_polarity_flip_phy29=0 +phy_tx_polarity_flip_phy29=1 +phy_rx_polarity_flip_phy30=1 +phy_tx_polarity_flip_phy30=0 +phy_rx_polarity_flip_phy31=1 +phy_tx_polarity_flip_phy31=1 +phy_rx_polarity_flip_phy16=0 +phy_tx_polarity_flip_phy16=0 +phy_rx_polarity_flip_phy17=1 +phy_tx_polarity_flip_phy17=0 +phy_rx_polarity_flip_phy18=0 +phy_tx_polarity_flip_phy18=1 +phy_rx_polarity_flip_phy19=1 +phy_tx_polarity_flip_phy19=0 +phy_rx_polarity_flip_phy20=1 +phy_tx_polarity_flip_phy20=1 +phy_rx_polarity_flip_phy21=1 +phy_tx_polarity_flip_phy21=0 +phy_rx_polarity_flip_phy22=1 +phy_tx_polarity_flip_phy22=0 +phy_rx_polarity_flip_phy23=1 +phy_tx_polarity_flip_phy23=0 +phy_rx_polarity_flip_phy40=1 +phy_tx_polarity_flip_phy40=1 +phy_rx_polarity_flip_phy41=0 +phy_tx_polarity_flip_phy41=0 +phy_rx_polarity_flip_phy42=1 +phy_tx_polarity_flip_phy42=1 +phy_rx_polarity_flip_phy43=1 +phy_tx_polarity_flip_phy43=0 +phy_rx_polarity_flip_phy44=1 +phy_tx_polarity_flip_phy44=1 +phy_rx_polarity_flip_phy45=1 +phy_tx_polarity_flip_phy45=1 +phy_rx_polarity_flip_phy46=1 +phy_tx_polarity_flip_phy46=1 +phy_rx_polarity_flip_phy47=0 +phy_tx_polarity_flip_phy47=0 +phy_rx_polarity_flip_phy32=1 +phy_tx_polarity_flip_phy32=1 +phy_rx_polarity_flip_phy33=0 +phy_tx_polarity_flip_phy33=0 +phy_rx_polarity_flip_phy34=1 +phy_tx_polarity_flip_phy34=1 +phy_rx_polarity_flip_phy35=1 +phy_tx_polarity_flip_phy35=0 +phy_rx_polarity_flip_phy36=0 +phy_tx_polarity_flip_phy36=0 +phy_rx_polarity_flip_phy37=0 +phy_tx_polarity_flip_phy37=0 +phy_rx_polarity_flip_phy38=1 +phy_tx_polarity_flip_phy38=1 +phy_rx_polarity_flip_phy39=1 +phy_tx_polarity_flip_phy39=0 +phy_rx_polarity_flip_phy56=0 +phy_tx_polarity_flip_phy56=1 +phy_rx_polarity_flip_phy57=1 +phy_tx_polarity_flip_phy57=1 +phy_rx_polarity_flip_phy58=1 +phy_tx_polarity_flip_phy58=1 +phy_rx_polarity_flip_phy59=1 +phy_tx_polarity_flip_phy59=0 +phy_rx_polarity_flip_phy60=0 +phy_tx_polarity_flip_phy60=1 +phy_rx_polarity_flip_phy61=0 +phy_tx_polarity_flip_phy61=1 +phy_rx_polarity_flip_phy62=1 +phy_tx_polarity_flip_phy62=1 +phy_rx_polarity_flip_phy63=1 +phy_tx_polarity_flip_phy63=0 +phy_rx_polarity_flip_phy48=1 +phy_tx_polarity_flip_phy48=1 +phy_rx_polarity_flip_phy49=0 +phy_tx_polarity_flip_phy49=0 +phy_rx_polarity_flip_phy50=1 +phy_tx_polarity_flip_phy50=1 +phy_rx_polarity_flip_phy51=1 +phy_tx_polarity_flip_phy51=0 +phy_rx_polarity_flip_phy52=0 +phy_tx_polarity_flip_phy52=0 +phy_rx_polarity_flip_phy53=0 +phy_tx_polarity_flip_phy53=0 +phy_rx_polarity_flip_phy54=1 +phy_tx_polarity_flip_phy54=1 +phy_rx_polarity_flip_phy55=1 +phy_tx_polarity_flip_phy55=0 +phy_rx_polarity_flip_phy136=0 +phy_tx_polarity_flip_phy136=0 +phy_rx_polarity_flip_phy137=1 +phy_tx_polarity_flip_phy137=1 +phy_rx_polarity_flip_phy138=0 +phy_tx_polarity_flip_phy138=0 +phy_rx_polarity_flip_phy139=0 +phy_tx_polarity_flip_phy139=1 +phy_rx_polarity_flip_phy140=0 +phy_tx_polarity_flip_phy140=0 +phy_rx_polarity_flip_phy141=0 +phy_tx_polarity_flip_phy141=0 +phy_rx_polarity_flip_phy142=0 +phy_tx_polarity_flip_phy142=0 +phy_rx_polarity_flip_phy143=1 +phy_tx_polarity_flip_phy143=1 +phy_rx_polarity_flip_phy64=0 +phy_tx_polarity_flip_phy64=0 +phy_rx_polarity_flip_phy65=1 +phy_tx_polarity_flip_phy65=0 +phy_rx_polarity_flip_phy66=0 +phy_tx_polarity_flip_phy66=1 +phy_rx_polarity_flip_phy67=1 +phy_tx_polarity_flip_phy67=0 +phy_rx_polarity_flip_phy68=1 +phy_tx_polarity_flip_phy68=0 +phy_rx_polarity_flip_phy69=1 +phy_tx_polarity_flip_phy69=0 +phy_rx_polarity_flip_phy70=1 +phy_tx_polarity_flip_phy70=1 +phy_rx_polarity_flip_phy71=1 +phy_tx_polarity_flip_phy71=0 +phy_rx_polarity_flip_phy120=1 +phy_tx_polarity_flip_phy120=0 +phy_rx_polarity_flip_phy121=0 +phy_tx_polarity_flip_phy121=1 +phy_rx_polarity_flip_phy122=0 +phy_tx_polarity_flip_phy122=0 +phy_rx_polarity_flip_phy123=0 +phy_tx_polarity_flip_phy123=1 +phy_rx_polarity_flip_phy124=1 +phy_tx_polarity_flip_phy124=0 +phy_rx_polarity_flip_phy125=1 +phy_tx_polarity_flip_phy125=0 +phy_rx_polarity_flip_phy126=0 +phy_tx_polarity_flip_phy126=1 +phy_rx_polarity_flip_phy127=0 +phy_tx_polarity_flip_phy127=0 +phy_rx_polarity_flip_phy128=0 +phy_tx_polarity_flip_phy128=0 +phy_rx_polarity_flip_phy129=1 +phy_tx_polarity_flip_phy129=1 +phy_rx_polarity_flip_phy130=0 +phy_tx_polarity_flip_phy130=0 +phy_rx_polarity_flip_phy131=0 +phy_tx_polarity_flip_phy131=1 +phy_rx_polarity_flip_phy132=1 +phy_tx_polarity_flip_phy132=1 +phy_rx_polarity_flip_phy133=1 +phy_tx_polarity_flip_phy133=1 +phy_rx_polarity_flip_phy134=0 +phy_tx_polarity_flip_phy134=0 +phy_rx_polarity_flip_phy135=0 +phy_tx_polarity_flip_phy135=1 +phy_rx_polarity_flip_phy104=1 +phy_tx_polarity_flip_phy104=0 +phy_rx_polarity_flip_phy105=0 +phy_tx_polarity_flip_phy105=0 +phy_rx_polarity_flip_phy106=0 +phy_tx_polarity_flip_phy106=0 +phy_rx_polarity_flip_phy107=0 +phy_tx_polarity_flip_phy107=1 +phy_rx_polarity_flip_phy108=1 +phy_tx_polarity_flip_phy108=0 +phy_rx_polarity_flip_phy109=1 +phy_tx_polarity_flip_phy109=0 +phy_rx_polarity_flip_phy110=0 +phy_tx_polarity_flip_phy110=0 +phy_rx_polarity_flip_phy111=0 +phy_tx_polarity_flip_phy111=1 +phy_rx_polarity_flip_phy112=1 +phy_tx_polarity_flip_phy112=1 +phy_rx_polarity_flip_phy113=0 +phy_tx_polarity_flip_phy113=1 +phy_rx_polarity_flip_phy114=1 +phy_tx_polarity_flip_phy114=0 +phy_rx_polarity_flip_phy115=0 +phy_tx_polarity_flip_phy115=1 +phy_rx_polarity_flip_phy116=0 +phy_tx_polarity_flip_phy116=1 +phy_rx_polarity_flip_phy117=0 +phy_tx_polarity_flip_phy117=1 +phy_rx_polarity_flip_phy118=0 +phy_tx_polarity_flip_phy118=0 +phy_rx_polarity_flip_phy119=0 +phy_tx_polarity_flip_phy119=1 +phy_rx_polarity_flip_phy88=0 +phy_tx_polarity_flip_phy88=0 +phy_rx_polarity_flip_phy89=1 +phy_tx_polarity_flip_phy89=0 +phy_rx_polarity_flip_phy90=0 +phy_tx_polarity_flip_phy90=0 +phy_rx_polarity_flip_phy91=0 +phy_tx_polarity_flip_phy91=1 +phy_rx_polarity_flip_phy92=0 +phy_tx_polarity_flip_phy92=1 +phy_rx_polarity_flip_phy93=0 +phy_tx_polarity_flip_phy93=1 +phy_rx_polarity_flip_phy94=0 +phy_tx_polarity_flip_phy94=0 +phy_rx_polarity_flip_phy95=1 +phy_tx_polarity_flip_phy95=0 +phy_rx_polarity_flip_phy96=0 +phy_tx_polarity_flip_phy96=1 +phy_rx_polarity_flip_phy97=1 +phy_tx_polarity_flip_phy97=0 +phy_rx_polarity_flip_phy98=0 +phy_tx_polarity_flip_phy98=0 +phy_rx_polarity_flip_phy99=0 +phy_tx_polarity_flip_phy99=1 +phy_rx_polarity_flip_phy100=1 +phy_tx_polarity_flip_phy100=1 +phy_rx_polarity_flip_phy101=1 +phy_tx_polarity_flip_phy101=1 +phy_rx_polarity_flip_phy102=0 +phy_tx_polarity_flip_phy102=0 +phy_rx_polarity_flip_phy103=0 +phy_tx_polarity_flip_phy103=1 +phy_rx_polarity_flip_phy72=0 +phy_tx_polarity_flip_phy72=1 +phy_rx_polarity_flip_phy73=1 +phy_tx_polarity_flip_phy73=0 +phy_rx_polarity_flip_phy74=1 +phy_tx_polarity_flip_phy74=1 +phy_rx_polarity_flip_phy75=1 +phy_tx_polarity_flip_phy75=0 +phy_rx_polarity_flip_phy76=0 +phy_tx_polarity_flip_phy76=1 +phy_rx_polarity_flip_phy77=0 +phy_tx_polarity_flip_phy77=1 +phy_rx_polarity_flip_phy78=1 +phy_tx_polarity_flip_phy78=0 +phy_rx_polarity_flip_phy79=1 +phy_tx_polarity_flip_phy79=1 +phy_rx_polarity_flip_phy80=0 +phy_tx_polarity_flip_phy80=1 +phy_rx_polarity_flip_phy81=1 +phy_tx_polarity_flip_phy81=0 +phy_rx_polarity_flip_phy82=0 +phy_tx_polarity_flip_phy82=1 +phy_rx_polarity_flip_phy83=0 +phy_tx_polarity_flip_phy83=0 +phy_rx_polarity_flip_phy84=1 +phy_tx_polarity_flip_phy84=0 +phy_rx_polarity_flip_phy85=1 +phy_tx_polarity_flip_phy85=0 +phy_rx_polarity_flip_phy86=0 +phy_tx_polarity_flip_phy86=1 +phy_rx_polarity_flip_phy87=0 +phy_tx_polarity_flip_phy87=0 + +appl_param_nof_ports_per_modid=64 +xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 +xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=2 +sai_pfc_dlr_init_capability=0 +sai_default_cpu_tx_tc=7 +sai_disable_srcmacqedstmac_ctrl=1 diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/pg_profile_lookup.ini b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/pg_profile_lookup.ini new file mode 120000 index 0000000000..61f0da8b31 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/pg_profile_lookup.ini @@ -0,0 +1 @@ +../0/pg_profile_lookup.ini \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/port_config.ini b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/port_config.ini new file mode 100644 index 0000000000..a8ce7b8f57 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/port_config.ini @@ -0,0 +1,21 @@ +# name lanes alias index role speed asic_port_name core_id core_port_id num_voq +Ethernet144 8,9,10,11,12,13,14,15 Ethernet19/1 19 Ext 400000 Eth0 0 1 8 +Ethernet152 0,1,2,3,4,5,6,7 Ethernet20/1 20 Ext 400000 Eth8 0 2 8 +Ethernet160 24,25,26,27,28,29,30,31 Ethernet21/1 21 Ext 400000 Eth16 0 3 8 +Ethernet168 16,17,18,19,20,21,22,23 Ethernet22/1 22 Ext 400000 Eth24 0 4 8 +Ethernet176 40,41,42,43,44,45,46,47 Ethernet23/1 23 Ext 400000 Eth32 0 5 8 +Ethernet184 32,33,34,35,36,37,38,39 Ethernet24/1 24 Ext 400000 Eth40 0 6 8 +Ethernet192 56,57,58,59,60,61,62,63 Ethernet25/1 25 Ext 400000 Eth48 0 7 8 +Ethernet200 48,49,50,51,52,53,54,55 Ethernet26/1 26 Ext 400000 Eth56 0 8 8 +Ethernet208 136,137,138,139,140,141,142,143 Ethernet27/1 27 Ext 400000 Eth64 1 9 8 +Ethernet216 64,65,66,67,68,69,70,71 Ethernet28/1 28 Ext 400000 Eth72 0 10 8 +Ethernet224 120,121,122,123,124,125,126,127 Ethernet29/1 29 Ext 400000 Eth80 1 11 8 +Ethernet232 128,129,130,131,132,133,134,135 Ethernet30/1 30 Ext 400000 Eth88 1 12 8 +Ethernet240 104,105,106,107,108,109,110,111 Ethernet31/1 31 Ext 400000 Eth96 1 13 8 +Ethernet248 112,113,114,115,116,117,118,119 Ethernet32/1 32 Ext 400000 Eth104 1 14 8 +Ethernet256 88,89,90,91,92,93,94,95 Ethernet33/1 33 Ext 400000 Eth112 1 15 8 +Ethernet264 96,97,98,99,100,101,102,103 Ethernet34/1 34 Ext 400000 Eth120 1 16 8 +Ethernet272 72,73,74,75,76,77,78,79 Ethernet35/1 35 Ext 400000 Eth128 1 17 8 +Ethernet280 80,81,82,83,84,85,86,87 Ethernet36/1 36 Ext 400000 Eth136 1 18 8 +Ethernet-Rec1 249 Recirc1/0 39 Rec 400000 Rcy0 0 49 8 +Ethernet-IB1 250 Recirc1/1 40 Inb 400000 Rcy1 1 50 8 diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/qos.json.j2 b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/qos.json.j2 new file mode 120000 index 0000000000..f84452fa4e --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/qos.json.j2 @@ -0,0 +1 @@ +../0/qos.json.j2 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/sai.profile b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/sai.profile new file mode 100644 index 0000000000..a84cf899d8 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/Arista-7280DR3A-36/1/sai.profile @@ -0,0 +1 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/jr2p-a7280dra3-36-36x400G.config.bcm diff --git a/device/arista/x86_64-arista_7280dr3a_36/asic.conf b/device/arista/x86_64-arista_7280dr3a_36/asic.conf new file mode 100644 index 0000000000..b6fdea0c00 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/asic.conf @@ -0,0 +1,3 @@ +NUM_ASIC=2 +DEV_ID_ASIC_0=09:00.0 +DEV_ID_ASIC_1=03:00.0 diff --git a/device/arista/x86_64-arista_7280dr3a_36/chassis_db.json b/device/arista/x86_64-arista_7280dr3a_36/chassis_db.json new file mode 100644 index 0000000000..ef4c689c21 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/chassis_db.json @@ -0,0 +1,17 @@ +{ + "SYSTEM_PORTCHANNEL|ASIC0|PortChannel1": { + "lag_id": "1" + }, + + "SYSTEM_PORTCHANNEL|ASIC1|PortChannel2": { + "lag_id": "2" + }, + + "SYSTEM_INTERFACE|ASIC0|PortChannel1": { + "vrf_name": "" + }, + + "SYSTEM_INTERFACE|ASIC1|PortChannel2": { + "vrf_name": "" + } +} diff --git a/device/arista/x86_64-arista_7280dr3a_36/chassisdb.conf b/device/arista/x86_64-arista_7280dr3a_36/chassisdb.conf new file mode 100644 index 0000000000..cec65ace2f --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/chassisdb.conf @@ -0,0 +1,5 @@ +start_chassis_db=1 +chassis_db_address=240.127.1.1 + +lag_id_start=1 +lag_id_end=1023 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3a_36/default_sku b/device/arista/x86_64-arista_7280dr3a_36/default_sku new file mode 100644 index 0000000000..35c9861462 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/default_sku @@ -0,0 +1 @@ +Arista-7280DR3A-36 t2 diff --git a/device/arista/x86_64-arista_7280dr3a_36/media_settings.json b/device/arista/x86_64-arista_7280dr3a_36/media_settings.json new file mode 100644 index 0000000000..a5d9fb1a5a --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/media_settings.json @@ -0,0 +1,11236 @@ +{ + "PORT_MEDIA_SETTINGS": { + "1": { + "COPPER25": { + "main": { + "lane0": "0x6d", + "lane1": "0x6d", + "lane2": "0x6d", + "lane3": "0x6d", + "lane4": "0x6d", + "lane5": "0x6d", + "lane6": "0x6d", + "lane7": "0x6d" + }, + "post1": { + "lane0": "0xfffffffc", + "lane1": "0xfffffffc", + "lane2": "0xfffffffc", + "lane3": "0xfffffffc", + "lane4": "0xfffffffc", + "lane5": "0xfffffffc", + "lane6": "0xfffffffc", + "lane7": "0xfffffffc" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "pre1": { + "lane0": "0xfffffff2", + "lane1": "0xfffffff2", + "lane2": "0xfffffff2", + "lane3": "0xfffffff2", + "lane4": "0xfffffff2", + "lane5": "0xfffffff2", + "lane6": "0xfffffff2", + "lane7": "0xfffffff2" + }, + "pre2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + } + }, + "OPTICAL25": { + "main": { + "lane0": "0x5d", + "lane1": "0x5c", + "lane2": "0x5d", + "lane3": "0x5d", + "lane4": "0x5c", + "lane5": "0x5c", + "lane6": "0x5d", + "lane7": "0x5d" + }, + "post1": { + "lane0": "0xffffffed", + "lane1": "0xffffffee", + "lane2": "0xffffffed", + "lane3": "0xffffffed", + "lane4": "0xffffffee", + "lane5": "0xffffffee", + "lane6": "0xffffffed", + "lane7": "0xffffffed" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "pre1": { + "lane0": "0xfffffff8", + "lane1": "0xfffffff8", + "lane2": "0xfffffff8", + "lane3": "0xfffffff8", + "lane4": "0xfffffff8", + "lane5": "0xfffffff8", + "lane6": "0xfffffff8", + "lane7": "0xfffffff8" + }, + "pre2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + } + }, + "OPTICAL50": { + "main": { + "lane0": "0x91", + "lane1": "0x91", + "lane2": "0x91", + "lane3": "0x91", + "lane4": "0x91", + "lane5": "0x91", + "lane6": "0x91", + "lane7": "0x91" + }, + "post1": { + "lane0": "0xfffffffb", + "lane1": "0xfffffffb", + "lane2": "0xfffffffb", + "lane3": "0xfffffffb", + "lane4": "0xfffffffb", + "lane5": "0xfffffffb", + "lane6": "0xfffffffb", + "lane7": "0xfffffffb" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0xfffffffe", + "lane1": "0xfffffffe", + "lane2": "0xfffffffe", + "lane3": "0xfffffffe", + "lane4": "0xfffffffe", + "lane5": "0xfffffffe", + "lane6": "0xfffffffe", + "lane7": "0xfffffffe" + }, + "pre1": { + "lane0": "0xfffffff0", + "lane1": "0xfffffff0", + "lane2": "0xfffffff0", + "lane3": "0xfffffff0", + "lane4": "0xfffffff0", + "lane5": "0xfffffff0", + "lane6": "0xfffffff0", + "lane7": "0xfffffff0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2", + "lane4": "0x2", + "lane5": "0x2", + "lane6": "0x2", + "lane7": "0x2" + } + }, + "QSFP-DD-active_cable_media_interface": { + "main": { + "lane0": "0x91", + "lane1": "0x91", + "lane2": "0x91", + "lane3": "0x91", + "lane4": "0x91", + "lane5": "0x91", + "lane6": "0x91", + "lane7": "0x91" + }, + "post1": { + "lane0": "0xfffffffb", + "lane1": "0xfffffffb", + "lane2": "0xfffffffb", + "lane3": "0xfffffffb", + "lane4": "0xfffffffb", + "lane5": "0xfffffffb", + "lane6": "0xfffffffb", + "lane7": "0xfffffffb" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0xfffffffe", + "lane1": "0xfffffffe", + "lane2": "0xfffffffe", + "lane3": "0xfffffffe", + "lane4": "0xfffffffe", + "lane5": "0xfffffffe", + "lane6": "0xfffffffe", + "lane7": "0xfffffffe" + }, + "pre1": { + "lane0": "0xfffffff0", + "lane1": "0xfffffff0", + "lane2": "0xfffffff0", + "lane3": "0xfffffff0", + "lane4": "0xfffffff0", + "lane5": "0xfffffff0", + "lane6": "0xfffffff0", + "lane7": "0xfffffff0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2", + "lane4": "0x2", + "lane5": "0x2", + "lane6": "0x2", + "lane7": "0x2" + } + }, + "passive_copper_media_interface": { + "main": { + "lane0": "0x84", + "lane1": "0x84", + "lane2": "0x84", + "lane3": "0x84", + "lane4": "0x84", + "lane5": "0x84", + "lane6": "0x84", + "lane7": "0x84" + }, + "post1": { + "lane0": "0xfffffffc", + "lane1": "0xfffffffc", + "lane2": "0xfffffffc", + "lane3": "0xfffffffc", + "lane4": "0xfffffffc", + "lane5": "0xfffffffc", + "lane6": "0xfffffffc", + "lane7": "0xfffffffc" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "pre1": { + "lane0": "0xffffffe4", + "lane1": "0xffffffe4", + "lane2": "0xffffffe4", + "lane3": "0xffffffe4", + "lane4": "0xffffffe4", + "lane5": "0xffffffe4", + "lane6": "0xffffffe4", + "lane7": "0xffffffe4" + }, + "pre2": { + "lane0": "0x6", + "lane1": "0x6", + "lane2": "0x6", + "lane3": "0x6", + "lane4": "0x6", + "lane5": "0x6", + "lane6": "0x6", + "lane7": "0x6" + } + } + }, + "2": { + "COPPER25": { + "main": { + "lane0": "0x6d", + "lane1": "0x6d", + "lane2": "0x6d", + "lane3": "0x6d", + "lane4": "0x6d", + "lane5": "0x6d", + "lane6": "0x6d", + "lane7": "0x6d" + }, + "post1": { + "lane0": "0xfffffffc", + "lane1": "0xfffffffc", + "lane2": "0xfffffffc", + "lane3": "0xfffffffc", + "lane4": "0xfffffffc", + "lane5": "0xfffffffc", + "lane6": "0xfffffffc", + "lane7": "0xfffffffc" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "pre1": { + "lane0": "0xfffffff2", + "lane1": "0xfffffff2", + "lane2": "0xfffffff2", + "lane3": "0xfffffff2", + "lane4": "0xfffffff2", + "lane5": "0xfffffff2", + "lane6": "0xfffffff2", + "lane7": "0xfffffff2" + }, + "pre2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + } + }, + "OPTICAL25": { + "main": { + "lane0": "0x5d", + "lane1": "0x5c", + "lane2": "0x5d", + "lane3": "0x5d", + "lane4": "0x5c", + "lane5": "0x5c", + "lane6": "0x5d", + "lane7": "0x5d" + }, + "post1": { + "lane0": "0xffffffed", + "lane1": "0xffffffee", + "lane2": "0xffffffed", + "lane3": "0xffffffed", + "lane4": "0xffffffee", + "lane5": "0xffffffee", + "lane6": "0xffffffed", + "lane7": "0xffffffed" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "pre1": { + "lane0": "0xfffffff8", + "lane1": "0xfffffff8", + "lane2": "0xfffffff8", + "lane3": "0xfffffff8", + "lane4": "0xfffffff8", + "lane5": "0xfffffff8", + "lane6": "0xfffffff8", + "lane7": "0xfffffff8" + }, + "pre2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + } + }, + "OPTICAL50": { + "main": { + "lane0": "0x96", + "lane1": "0x96", + "lane2": "0x96", + "lane3": "0x96", + "lane4": "0x96", + "lane5": "0x96", + "lane6": "0x96", + "lane7": "0x96" + }, + "post1": { + "lane0": "0x0", + "lane1": "0xfffffff9", + "lane2": "0x0", + "lane3": "0xfffffff9", + "lane4": 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"lane5": "0x96", + "lane6": "0x96", + "lane7": "0x96" + }, + "post1": { + "lane0": "0x0", + "lane1": "0xfffffff9", + "lane2": "0x0", + "lane3": "0xfffffff9", + "lane4": "0xfffffff9", + "lane5": "0xfffffff9", + "lane6": "0xfffffff9", + "lane7": "0xfffffff9" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0xfffffffd", + "lane1": "0xfffffffe", + "lane2": "0xfffffffd", + "lane3": "0xfffffffe", + "lane4": "0xfffffffe", + "lane5": "0xfffffffe", + "lane6": "0xfffffffe", + "lane7": "0xfffffffe" + }, + "pre1": { + "lane0": "0xfffffff0", + "lane1": "0xfffffff5", + "lane2": "0xfffffff0", + "lane3": "0xfffffff5", + "lane4": "0xfffffff5", + "lane5": "0xfffffff5", + "lane6": "0xfffffff5", + "lane7": "0xfffffff5" + }, + "pre2": { + "lane0": "0x1", + "lane1": "0x0", + "lane2": "0x1", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + } + }, + "QSFP-DD-active_cable_media_interface": { + "main": { + "lane0": "0x96", + "lane1": "0x96", + "lane2": "0x96", + "lane3": "0x96", + "lane4": "0x96", + "lane5": "0x96", + "lane6": "0x96", + "lane7": "0x96" + }, + "post1": { + "lane0": "0x0", + "lane1": "0xfffffff9", + "lane2": "0x0", + "lane3": "0xfffffff9", + "lane4": "0xfffffff9", + "lane5": "0xfffffff9", + "lane6": "0xfffffff9", + "lane7": "0xfffffff9" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0xfffffffd", + "lane1": "0xfffffffe", + "lane2": "0xfffffffd", + "lane3": "0xfffffffe", + "lane4": "0xfffffffe", + "lane5": "0xfffffffe", + "lane6": "0xfffffffe", + "lane7": "0xfffffffe" + }, + "pre1": { + "lane0": "0xfffffff0", + "lane1": "0xfffffff5", + "lane2": "0xfffffff0", + "lane3": "0xfffffff5", + "lane4": "0xfffffff5", + "lane5": "0xfffffff5", + "lane6": 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"lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "pre1": { + "lane0": "0xfffffff2", + "lane1": "0xfffffff2", + "lane2": "0xfffffff2", + "lane3": "0xfffffff2", + "lane4": "0xfffffff2", + "lane5": "0xfffffff2", + "lane6": "0xfffffff2", + "lane7": "0xfffffff2" + }, + "pre2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + } + }, + "OPTICAL25": { + "main": { + "lane0": "0x5d", + "lane1": "0x5c", + "lane2": "0x5d", + "lane3": "0x5c", + "lane4": "0x5d", + "lane5": "0x5d", + "lane6": "0x5d", + "lane7": "0x5c" + }, + "post1": { + "lane0": "0xffffffed", + "lane1": "0xffffffee", + "lane2": "0xffffffed", + "lane3": "0xffffffee", + "lane4": "0xffffffed", + "lane5": "0xffffffed", + "lane6": "0xffffffed", + "lane7": "0xffffffee" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "pre1": { + "lane0": "0xfffffff8", + "lane1": "0xfffffff8", + "lane2": "0xfffffff8", + "lane3": "0xfffffff8", + "lane4": "0xfffffff8", + "lane5": "0xfffffff8", + "lane6": "0xfffffff8", + "lane7": "0xfffffff8" + }, + "pre2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + } + }, + "OPTICAL50": { + "main": { + "lane0": "0x91", + "lane1": "0x91", + "lane2": "0x91", + "lane3": "0x91", + "lane4": "0x91", + "lane5": "0x91", + "lane6": "0x91", + "lane7": "0x91" + }, + "post1": { + "lane0": "0xfffffffb", + "lane1": "0xfffffffb", + "lane2": "0xfffffffb", + "lane3": "0xfffffffb", + "lane4": "0xfffffffb", + "lane5": "0xfffffffb", + "lane6": "0xfffffffb", + "lane7": "0xfffffffb" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0xfffffffe", + "lane1": "0xfffffffe", + "lane2": "0xfffffffe", + "lane3": "0xfffffffe", + "lane4": "0xfffffffe", + "lane5": "0xfffffffe", + "lane6": "0xfffffffe", + "lane7": "0xfffffffe" + }, + "pre1": { + "lane0": "0xfffffff0", + "lane1": "0xfffffff0", + "lane2": "0xfffffff0", + "lane3": "0xfffffff0", + "lane4": "0xfffffff0", + "lane5": "0xfffffff0", + "lane6": "0xfffffff0", + "lane7": "0xfffffff0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2", + "lane4": "0x2", + "lane5": "0x2", + "lane6": "0x2", + "lane7": "0x2" + } + }, + "QSFP-DD-active_cable_media_interface": { + "main": { + "lane0": "0x91", + "lane1": "0x91", + "lane2": "0x91", + "lane3": "0x91", + "lane4": "0x91", + "lane5": "0x91", + "lane6": "0x91", + "lane7": "0x91" + }, + "post1": { + "lane0": "0xfffffffb", + "lane1": "0xfffffffb", + "lane2": "0xfffffffb", + "lane3": "0xfffffffb", + "lane4": "0xfffffffb", + "lane5": "0xfffffffb", + "lane6": "0xfffffffb", + "lane7": "0xfffffffb" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0xfffffffe", + "lane1": "0xfffffffe", + "lane2": "0xfffffffe", + "lane3": "0xfffffffe", + "lane4": "0xfffffffe", + "lane5": "0xfffffffe", + "lane6": "0xfffffffe", + "lane7": "0xfffffffe" + }, + "pre1": { + "lane0": "0xfffffff0", + "lane1": "0xfffffff0", + "lane2": "0xfffffff0", + "lane3": "0xfffffff0", + "lane4": "0xfffffff0", + "lane5": "0xfffffff0", + "lane6": "0xfffffff0", + "lane7": "0xfffffff0" + }, + "pre2": { + "lane0": "0x2", + "lane1": "0x2", + "lane2": "0x2", + "lane3": "0x2", + "lane4": "0x2", + "lane5": "0x2", + "lane6": "0x2", + "lane7": "0x2" + } + }, + "passive_copper_media_interface": { + "main": { + "lane0": "0x84", + "lane1": "0x84", + "lane2": "0x84", + "lane3": "0x84", + "lane4": "0x84", + "lane5": "0x84", + "lane6": "0x84", + "lane7": "0x84" + }, + "post1": { + "lane0": "0xfffffffc", + "lane1": "0xfffffffc", + "lane2": "0xfffffffc", + "lane3": "0xfffffffc", + "lane4": "0xfffffffc", + "lane5": "0xfffffffc", + "lane6": "0xfffffffc", + "lane7": "0xfffffffc" + }, + "post2": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "post3": { + "lane0": "0x0", + "lane1": "0x0", + "lane2": "0x0", + "lane3": "0x0", + "lane4": "0x0", + "lane5": "0x0", + "lane6": "0x0", + "lane7": "0x0" + }, + "pre1": { + "lane0": "0xffffffe4", + "lane1": "0xffffffe4", + "lane2": "0xffffffe4", + "lane3": "0xffffffe4", + "lane4": "0xffffffe4", + "lane5": "0xffffffe4", + "lane6": "0xffffffe4", + "lane7": "0xffffffe4" + }, + "pre2": { + "lane0": "0x6", + "lane1": "0x6", + "lane2": "0x6", + "lane3": "0x6", + "lane4": "0x6", + "lane5": "0x6", + "lane6": "0x6", + "lane7": "0x6" + } + } + } + } +} diff --git a/device/arista/x86_64-arista_7280dr3a_36/pcie.yaml b/device/arista/x86_64-arista_7280dr3a_36/pcie.yaml new file mode 120000 index 0000000000..df18a601d8 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/pcie.yaml @@ -0,0 +1 @@ +../x86_64-arista_common/pcie.yaml \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3a_36/platform.json b/device/arista/x86_64-arista_7280dr3a_36/platform.json new file mode 100644 index 0000000000..60099ed7a3 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/platform.json @@ -0,0 +1,251 @@ +{ + "chassis": { + "name": "DCS-7280DR3A-36", + "components": [ + { + "name": "Aboot()" + }, + { + "name": "Scd(addr=0000:00:18.7)" + }, + { + "name": "Adm1266(addr=10-004f)" + }, + { + "name": "Ucd90320(addr=14-0011)" + }, + { + "name": "Scd(addr=0000:01:00.0)" + }, + { + "name": "CormorantSysCpld(addr=13-0023)" + } + ], + "fans": [], + "fan_drawers": [ + { + "name": "slot1", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan1", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "slot2", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan2", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "slot3", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan3", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "slot4", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan4", + "status_led": { + "controllable": false + } + } + ] + } + ], + "psus": [ + { + "name": "psu1", + "fans": [ + { + "name": "psu1/1", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "psu2", + "fans": [ + { + "name": "psu2/1", + "status_led": { + "controllable": false + } + } + ] + } + ], + "thermals": [ + { + "name": "CPU" + }, + { + "name": "CPU board" + }, + { + "name": "Back-panel" + }, + { + "name": "JE0 Front Side" + }, + { + "name": "Air Inlet" + }, + { + "name": "Board Temp" + }, + { + "name": "JE1_C Diode" + }, + { + "name": "JE0_C Diode" + } + ], + "sfps": [ + { + "name": "osfp1" + }, + { + "name": "osfp2" + }, + { + "name": "osfp3" + }, + { + "name": "osfp4" + }, + { + "name": "osfp5" + }, + { + "name": "osfp6" + }, + { + "name": "osfp7" + }, + { + "name": "osfp8" + }, + { + "name": "osfp9" + }, + { + "name": "osfp10" + }, + { + "name": "osfp11" + }, + { + "name": "osfp12" + }, + { + "name": "osfp13" + }, + { + "name": "osfp14" + }, + { + "name": "osfp15" + }, + { + "name": "osfp16" + }, + { + "name": "osfp17" + }, + { + "name": "osfp18" + }, + { + "name": "osfp19" + }, + { + "name": "osfp20" + }, + { + "name": "osfp21" + }, + { + "name": "osfp22" + }, + { + "name": "osfp23" + }, + { + "name": "osfp24" + }, + { + "name": "osfp25" + }, + { + "name": "osfp26" + }, + { + "name": "osfp27" + }, + { + "name": "osfp28" + }, + { + "name": "osfp29" + }, + { + "name": "osfp30" + }, + { + "name": "osfp31" + }, + { + "name": "osfp32" + }, + { + "name": "osfp33" + }, + { + "name": "osfp34" + }, + { + "name": "osfp35" + }, + { + "name": "osfp36" + }, + { + "name": "osfp37" + }, + { + "name": "osfp38" + } + ] + }, + "interfaces": {} +} diff --git a/device/arista/x86_64-arista_7280dr3a_36/platform_asic b/device/arista/x86_64-arista_7280dr3a_36/platform_asic new file mode 100644 index 0000000000..9ba24ca3e7 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/platform_asic @@ -0,0 +1 @@ +broadcom-dnx diff --git a/device/arista/x86_64-arista_7280dr3a_36/platform_components.json b/device/arista/x86_64-arista_7280dr3a_36/platform_components.json new file mode 100644 index 0000000000..0e6ea83787 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/platform_components.json @@ -0,0 +1,8 @@ +{ + "chassis": { + "DCS-7280DR3A-36": { + "component": { + } + } + } +} diff --git a/device/arista/x86_64-arista_7280dr3a_36/platform_env.conf b/device/arista/x86_64-arista_7280dr3a_36/platform_env.conf new file mode 100644 index 0000000000..3eb1e2c503 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/platform_env.conf @@ -0,0 +1,4 @@ +SYNCD_SHM_SIZE=512m +dmasize=64M +usemsi=1 +disaggregated_chassis=1 diff --git a/device/arista/x86_64-arista_7280dr3a_36/platform_reboot b/device/arista/x86_64-arista_7280dr3a_36/platform_reboot new file mode 120000 index 0000000000..7f94a49e38 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/platform_reboot @@ -0,0 +1 @@ +../x86_64-arista_common/platform_reboot \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3a_36/plugins b/device/arista/x86_64-arista_7280dr3a_36/plugins new file mode 120000 index 0000000000..789a45fcac --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/plugins @@ -0,0 +1 @@ +../x86_64-arista_common/plugins \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3a_36/pmon_daemon_control.json b/device/arista/x86_64-arista_7280dr3a_36/pmon_daemon_control.json new file mode 120000 index 0000000000..51d5ab7b00 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/pmon_daemon_control.json @@ -0,0 +1 @@ +../x86_64-arista_common/pmon_daemon_control.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3a_36/sensors.conf b/device/arista/x86_64-arista_7280dr3a_36/sensors.conf new file mode 100644 index 0000000000..1e8a379fa4 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/sensors.conf @@ -0,0 +1,7 @@ +chip "nvme-pci-0500" + ignore temp2 + ignore temp3 + ignore temp4 + ignore temp5 + ignore temp6 + ignore temp7 diff --git a/device/arista/x86_64-arista_7280dr3a_36/system_health_monitoring_config.json b/device/arista/x86_64-arista_7280dr3a_36/system_health_monitoring_config.json new file mode 120000 index 0000000000..1185f771fa --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/system_health_monitoring_config.json @@ -0,0 +1 @@ +../x86_64-arista_common/system_health_monitoring_config.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3a_36/thermal_policy.json b/device/arista/x86_64-arista_7280dr3a_36/thermal_policy.json new file mode 120000 index 0000000000..0991dc7f36 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3a_36/thermal_policy.json @@ -0,0 +1 @@ +../x86_64-arista_common/thermal_policy.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36/Arista-7280DR3AK-36 b/device/arista/x86_64-arista_7280dr3ak_36/Arista-7280DR3AK-36 new file mode 120000 index 0000000000..165a05dbc8 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/Arista-7280DR3AK-36 @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/Arista-7280DR3A-36 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36/asic.conf b/device/arista/x86_64-arista_7280dr3ak_36/asic.conf new file mode 100644 index 0000000000..b6fdea0c00 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/asic.conf @@ -0,0 +1,3 @@ +NUM_ASIC=2 +DEV_ID_ASIC_0=09:00.0 +DEV_ID_ASIC_1=03:00.0 diff --git a/device/arista/x86_64-arista_7280dr3ak_36/chassis_db.json b/device/arista/x86_64-arista_7280dr3ak_36/chassis_db.json new file mode 120000 index 0000000000..727fe612fc --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/chassis_db.json @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/chassis_db.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36/chassisdb.conf b/device/arista/x86_64-arista_7280dr3ak_36/chassisdb.conf new file mode 120000 index 0000000000..c32473489c --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/chassisdb.conf @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/chassisdb.conf \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36/default_sku b/device/arista/x86_64-arista_7280dr3ak_36/default_sku new file mode 100644 index 0000000000..b748b69df7 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/default_sku @@ -0,0 +1 @@ +Arista-7280DR3AK-36 t2 diff --git a/device/arista/x86_64-arista_7280dr3ak_36/media_settings.json b/device/arista/x86_64-arista_7280dr3ak_36/media_settings.json new file mode 120000 index 0000000000..c85fdb3185 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/media_settings.json @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/media_settings.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36/pcie.yaml b/device/arista/x86_64-arista_7280dr3ak_36/pcie.yaml new file mode 120000 index 0000000000..df18a601d8 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/pcie.yaml @@ -0,0 +1 @@ +../x86_64-arista_common/pcie.yaml \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36/platform.json b/device/arista/x86_64-arista_7280dr3ak_36/platform.json new file mode 100644 index 0000000000..5c839549e9 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/platform.json @@ -0,0 +1,251 @@ +{ + "chassis": { + "name": "DCS-7280DR3AK-36", + "components": [ + { + "name": "Aboot()" + }, + { + "name": "Scd(addr=0000:00:18.7)" + }, + { + "name": "Adm1266(addr=10-004f)" + }, + { + "name": "Ucd90320(addr=14-0011)" + }, + { + "name": "Scd(addr=0000:01:00.0)" + }, + { + "name": "CormorantSysCpld(addr=13-0023)" + } + ], + "fans": [], + "fan_drawers": [ + { + "name": "slot1", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan1", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "slot2", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan2", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "slot3", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan3", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "slot4", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan4", + "status_led": { + "controllable": false + } + } + ] + } + ], + "psus": [ + { + "name": "psu1", + "fans": [ + { + "name": "psu1/1", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "psu2", + "fans": [ + { + "name": "psu2/1", + "status_led": { + "controllable": false + } + } + ] + } + ], + "thermals": [ + { + "name": "CPU" + }, + { + "name": "CPU board" + }, + { + "name": "Back-panel" + }, + { + "name": "JE0 Front Side" + }, + { + "name": "Air Inlet" + }, + { + "name": "Board Temp" + }, + { + "name": "JE1_C Diode" + }, + { + "name": "JE0_C Diode" + } + ], + "sfps": [ + { + "name": "osfp1" + }, + { + "name": "osfp2" + }, + { + "name": "osfp3" + }, + { + "name": "osfp4" + }, + { + "name": "osfp5" + }, + { + "name": "osfp6" + }, + { + "name": "osfp7" + }, + { + "name": "osfp8" + }, + { + "name": "osfp9" + }, + { + "name": "osfp10" + }, + { + "name": "osfp11" + }, + { + "name": "osfp12" + }, + { + "name": "osfp13" + }, + { + "name": "osfp14" + }, + { + "name": "osfp15" + }, + { + "name": "osfp16" + }, + { + "name": "osfp17" + }, + { + "name": "osfp18" + }, + { + "name": "osfp19" + }, + { + "name": "osfp20" + }, + { + "name": "osfp21" + }, + { + "name": "osfp22" + }, + { + "name": "osfp23" + }, + { + "name": "osfp24" + }, + { + "name": "osfp25" + }, + { + "name": "osfp26" + }, + { + "name": "osfp27" + }, + { + "name": "osfp28" + }, + { + "name": "osfp29" + }, + { + "name": "osfp30" + }, + { + "name": "osfp31" + }, + { + "name": "osfp32" + }, + { + "name": "osfp33" + }, + { + "name": "osfp34" + }, + { + "name": "osfp35" + }, + { + "name": "osfp36" + }, + { + "name": "osfp37" + }, + { + "name": "osfp38" + } + ] + }, + "interfaces": {} +} diff --git a/device/arista/x86_64-arista_7280dr3ak_36/platform_asic b/device/arista/x86_64-arista_7280dr3ak_36/platform_asic new file mode 100644 index 0000000000..9ba24ca3e7 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/platform_asic @@ -0,0 +1 @@ +broadcom-dnx diff --git a/device/arista/x86_64-arista_7280dr3ak_36/platform_components.json b/device/arista/x86_64-arista_7280dr3ak_36/platform_components.json new file mode 100644 index 0000000000..9af6bc9763 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/platform_components.json @@ -0,0 +1,8 @@ +{ + "chassis": { + "DCS-7280DR3AK-36": { + "component": { + } + } + } +} diff --git a/device/arista/x86_64-arista_7280dr3ak_36/platform_env.conf b/device/arista/x86_64-arista_7280dr3ak_36/platform_env.conf new file mode 120000 index 0000000000..c72dc74350 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/platform_env.conf @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/platform_env.conf \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36/platform_reboot b/device/arista/x86_64-arista_7280dr3ak_36/platform_reboot new file mode 120000 index 0000000000..7f94a49e38 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/platform_reboot @@ -0,0 +1 @@ +../x86_64-arista_common/platform_reboot \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36/plugins b/device/arista/x86_64-arista_7280dr3ak_36/plugins new file mode 120000 index 0000000000..789a45fcac --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/plugins @@ -0,0 +1 @@ +../x86_64-arista_common/plugins \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36/pmon_daemon_control.json b/device/arista/x86_64-arista_7280dr3ak_36/pmon_daemon_control.json new file mode 120000 index 0000000000..51d5ab7b00 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/pmon_daemon_control.json @@ -0,0 +1 @@ +../x86_64-arista_common/pmon_daemon_control.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36/sensors.conf b/device/arista/x86_64-arista_7280dr3ak_36/sensors.conf new file mode 100644 index 0000000000..1e8a379fa4 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/sensors.conf @@ -0,0 +1,7 @@ +chip "nvme-pci-0500" + ignore temp2 + ignore temp3 + ignore temp4 + ignore temp5 + ignore temp6 + ignore temp7 diff --git a/device/arista/x86_64-arista_7280dr3ak_36/system_health_monitoring_config.json b/device/arista/x86_64-arista_7280dr3ak_36/system_health_monitoring_config.json new file mode 120000 index 0000000000..1185f771fa --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/system_health_monitoring_config.json @@ -0,0 +1 @@ +../x86_64-arista_common/system_health_monitoring_config.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36/thermal_policy.json b/device/arista/x86_64-arista_7280dr3ak_36/thermal_policy.json new file mode 120000 index 0000000000..0991dc7f36 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36/thermal_policy.json @@ -0,0 +1 @@ +../x86_64-arista_common/thermal_policy.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/Arista-7280DR3AK-36S b/device/arista/x86_64-arista_7280dr3ak_36s/Arista-7280DR3AK-36S new file mode 120000 index 0000000000..165a05dbc8 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/Arista-7280DR3AK-36S @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/Arista-7280DR3A-36 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/asic.conf b/device/arista/x86_64-arista_7280dr3ak_36s/asic.conf new file mode 100644 index 0000000000..b6fdea0c00 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/asic.conf @@ -0,0 +1,3 @@ +NUM_ASIC=2 +DEV_ID_ASIC_0=09:00.0 +DEV_ID_ASIC_1=03:00.0 diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/chassis_db.json b/device/arista/x86_64-arista_7280dr3ak_36s/chassis_db.json new file mode 120000 index 0000000000..727fe612fc --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/chassis_db.json @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/chassis_db.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/chassisdb.conf b/device/arista/x86_64-arista_7280dr3ak_36s/chassisdb.conf new file mode 120000 index 0000000000..c32473489c --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/chassisdb.conf @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/chassisdb.conf \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/default_sku b/device/arista/x86_64-arista_7280dr3ak_36s/default_sku new file mode 100644 index 0000000000..28486f8c21 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/default_sku @@ -0,0 +1 @@ +Arista-7280DR3AK-36S t2 diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/media_settings.json b/device/arista/x86_64-arista_7280dr3ak_36s/media_settings.json new file mode 120000 index 0000000000..c85fdb3185 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/media_settings.json @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/media_settings.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/pcie.yaml b/device/arista/x86_64-arista_7280dr3ak_36s/pcie.yaml new file mode 120000 index 0000000000..df18a601d8 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/pcie.yaml @@ -0,0 +1 @@ +../x86_64-arista_common/pcie.yaml \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/platform.json b/device/arista/x86_64-arista_7280dr3ak_36s/platform.json new file mode 100644 index 0000000000..2e1029161a --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/platform.json @@ -0,0 +1,251 @@ +{ + "chassis": { + "name": "DCS-7280DR3AK-36S", + "components": [ + { + "name": "Aboot()" + }, + { + "name": "Scd(addr=0000:00:18.7)" + }, + { + "name": "Adm1266(addr=10-004f)" + }, + { + "name": "Ucd90320(addr=14-0011)" + }, + { + "name": "Scd(addr=0000:01:00.0)" + }, + { + "name": "CormorantSysCpld(addr=13-0023)" + } + ], + "fans": [], + "fan_drawers": [ + { + "name": "slot1", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan1", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "slot2", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan2", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "slot3", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan3", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "slot4", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan4", + "status_led": { + "controllable": false + } + } + ] + } + ], + "psus": [ + { + "name": "psu1", + "fans": [ + { + "name": "psu1/1", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "psu2", + "fans": [ + { + "name": "psu2/1", + "status_led": { + "controllable": false + } + } + ] + } + ], + "thermals": [ + { + "name": "CPU" + }, + { + "name": "CPU board" + }, + { + "name": "Back-panel" + }, + { + "name": "JE0 Front Side" + }, + { + "name": "Air Inlet" + }, + { + "name": "Board Temp" + }, + { + "name": "JE1_C Diode" + }, + { + "name": "JE0_C Diode" + } + ], + "sfps": [ + { + "name": "osfp1" + }, + { + "name": "osfp2" + }, + { + "name": "osfp3" + }, + { + "name": "osfp4" + }, + { + "name": "osfp5" + }, + { + "name": "osfp6" + }, + { + "name": "osfp7" + }, + { + "name": "osfp8" + }, + { + "name": "osfp9" + }, + { + "name": "osfp10" + }, + { + "name": "osfp11" + }, + { + "name": "osfp12" + }, + { + "name": "osfp13" + }, + { + "name": "osfp14" + }, + { + "name": "osfp15" + }, + { + "name": "osfp16" + }, + { + "name": "osfp17" + }, + { + "name": "osfp18" + }, + { + "name": "osfp19" + }, + { + "name": "osfp20" + }, + { + "name": "osfp21" + }, + { + "name": "osfp22" + }, + { + "name": "osfp23" + }, + { + "name": "osfp24" + }, + { + "name": "osfp25" + }, + { + "name": "osfp26" + }, + { + "name": "osfp27" + }, + { + "name": "osfp28" + }, + { + "name": "osfp29" + }, + { + "name": "osfp30" + }, + { + "name": "osfp31" + }, + { + "name": "osfp32" + }, + { + "name": "osfp33" + }, + { + "name": "osfp34" + }, + { + "name": "osfp35" + }, + { + "name": "osfp36" + }, + { + "name": "osfp37" + }, + { + "name": "osfp38" + } + ] + }, + "interfaces": {} +} diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/platform_asic b/device/arista/x86_64-arista_7280dr3ak_36s/platform_asic new file mode 100644 index 0000000000..9ba24ca3e7 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/platform_asic @@ -0,0 +1 @@ +broadcom-dnx diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/platform_components.json b/device/arista/x86_64-arista_7280dr3ak_36s/platform_components.json new file mode 100644 index 0000000000..b6f7240330 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/platform_components.json @@ -0,0 +1,8 @@ +{ + "chassis": { + "DCS-7280DR3AK-36S": { + "component": { + } + } + } +} diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/platform_env.conf b/device/arista/x86_64-arista_7280dr3ak_36s/platform_env.conf new file mode 120000 index 0000000000..c72dc74350 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/platform_env.conf @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/platform_env.conf \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/platform_reboot b/device/arista/x86_64-arista_7280dr3ak_36s/platform_reboot new file mode 120000 index 0000000000..7f94a49e38 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/platform_reboot @@ -0,0 +1 @@ +../x86_64-arista_common/platform_reboot \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/plugins b/device/arista/x86_64-arista_7280dr3ak_36s/plugins new file mode 120000 index 0000000000..789a45fcac --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/plugins @@ -0,0 +1 @@ +../x86_64-arista_common/plugins \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/pmon_daemon_control.json b/device/arista/x86_64-arista_7280dr3ak_36s/pmon_daemon_control.json new file mode 120000 index 0000000000..51d5ab7b00 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/pmon_daemon_control.json @@ -0,0 +1 @@ +../x86_64-arista_common/pmon_daemon_control.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/sensors.conf b/device/arista/x86_64-arista_7280dr3ak_36s/sensors.conf new file mode 100644 index 0000000000..1e8a379fa4 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/sensors.conf @@ -0,0 +1,7 @@ +chip "nvme-pci-0500" + ignore temp2 + ignore temp3 + ignore temp4 + ignore temp5 + ignore temp6 + ignore temp7 diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/system_health_monitoring_config.json b/device/arista/x86_64-arista_7280dr3ak_36s/system_health_monitoring_config.json new file mode 120000 index 0000000000..1185f771fa --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/system_health_monitoring_config.json @@ -0,0 +1 @@ +../x86_64-arista_common/system_health_monitoring_config.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3ak_36s/thermal_policy.json b/device/arista/x86_64-arista_7280dr3ak_36s/thermal_policy.json new file mode 120000 index 0000000000..0991dc7f36 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3ak_36s/thermal_policy.json @@ -0,0 +1 @@ +../x86_64-arista_common/thermal_policy.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3am_36/Arista-7280DR3AM-36 b/device/arista/x86_64-arista_7280dr3am_36/Arista-7280DR3AM-36 new file mode 120000 index 0000000000..165a05dbc8 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/Arista-7280DR3AM-36 @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/Arista-7280DR3A-36 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3am_36/asic.conf b/device/arista/x86_64-arista_7280dr3am_36/asic.conf new file mode 100644 index 0000000000..b6fdea0c00 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/asic.conf @@ -0,0 +1,3 @@ +NUM_ASIC=2 +DEV_ID_ASIC_0=09:00.0 +DEV_ID_ASIC_1=03:00.0 diff --git a/device/arista/x86_64-arista_7280dr3am_36/chassis_db.json b/device/arista/x86_64-arista_7280dr3am_36/chassis_db.json new file mode 120000 index 0000000000..727fe612fc --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/chassis_db.json @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/chassis_db.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3am_36/chassisdb.conf b/device/arista/x86_64-arista_7280dr3am_36/chassisdb.conf new file mode 120000 index 0000000000..c32473489c --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/chassisdb.conf @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/chassisdb.conf \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3am_36/default_sku b/device/arista/x86_64-arista_7280dr3am_36/default_sku new file mode 100644 index 0000000000..fae2c752a7 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/default_sku @@ -0,0 +1 @@ +Arista-7280DR3AM-36 t2 diff --git a/device/arista/x86_64-arista_7280dr3am_36/media_settings.json b/device/arista/x86_64-arista_7280dr3am_36/media_settings.json new file mode 120000 index 0000000000..c85fdb3185 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/media_settings.json @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/media_settings.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3am_36/pcie.yaml b/device/arista/x86_64-arista_7280dr3am_36/pcie.yaml new file mode 120000 index 0000000000..df18a601d8 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/pcie.yaml @@ -0,0 +1 @@ +../x86_64-arista_common/pcie.yaml \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3am_36/platform.json b/device/arista/x86_64-arista_7280dr3am_36/platform.json new file mode 100644 index 0000000000..9689db66a5 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/platform.json @@ -0,0 +1,251 @@ +{ + "chassis": { + "name": "DCS-7280DR3AM-36", + "components": [ + { + "name": "Aboot()" + }, + { + "name": "Scd(addr=0000:00:18.7)" + }, + { + "name": "Adm1266(addr=10-004f)" + }, + { + "name": "Ucd90320(addr=14-0011)" + }, + { + "name": "Scd(addr=0000:01:00.0)" + }, + { + "name": "CormorantSysCpld(addr=13-0023)" + } + ], + "fans": [], + "fan_drawers": [ + { + "name": "slot1", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan1", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "slot2", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan2", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "slot3", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan3", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "slot4", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "fan4", + "status_led": { + "controllable": false + } + } + ] + } + ], + "psus": [ + { + "name": "psu1", + "fans": [ + { + "name": "psu1/1", + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "psu2", + "fans": [ + { + "name": "psu2/1", + "status_led": { + "controllable": false + } + } + ] + } + ], + "thermals": [ + { + "name": "CPU" + }, + { + "name": "CPU board" + }, + { + "name": "Back-panel" + }, + { + "name": "JE0 Front Side" + }, + { + "name": "Air Inlet" + }, + { + "name": "Board Temp" + }, + { + "name": "JE1_C Diode" + }, + { + "name": "JE0_C Diode" + } + ], + "sfps": [ + { + "name": "osfp1" + }, + { + "name": "osfp2" + }, + { + "name": "osfp3" + }, + { + "name": "osfp4" + }, + { + "name": "osfp5" + }, + { + "name": "osfp6" + }, + { + "name": "osfp7" + }, + { + "name": "osfp8" + }, + { + "name": "osfp9" + }, + { + "name": "osfp10" + }, + { + "name": "osfp11" + }, + { + "name": "osfp12" + }, + { + "name": "osfp13" + }, + { + "name": "osfp14" + }, + { + "name": "osfp15" + }, + { + "name": "osfp16" + }, + { + "name": "osfp17" + }, + { + "name": "osfp18" + }, + { + "name": "osfp19" + }, + { + "name": "osfp20" + }, + { + "name": "osfp21" + }, + { + "name": "osfp22" + }, + { + "name": "osfp23" + }, + { + "name": "osfp24" + }, + { + "name": "osfp25" + }, + { + "name": "osfp26" + }, + { + "name": "osfp27" + }, + { + "name": "osfp28" + }, + { + "name": "osfp29" + }, + { + "name": "osfp30" + }, + { + "name": "osfp31" + }, + { + "name": "osfp32" + }, + { + "name": "osfp33" + }, + { + "name": "osfp34" + }, + { + "name": "osfp35" + }, + { + "name": "osfp36" + }, + { + "name": "osfp37" + }, + { + "name": "osfp38" + } + ] + }, + "interfaces": {} +} diff --git a/device/arista/x86_64-arista_7280dr3am_36/platform_asic b/device/arista/x86_64-arista_7280dr3am_36/platform_asic new file mode 100644 index 0000000000..9ba24ca3e7 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/platform_asic @@ -0,0 +1 @@ +broadcom-dnx diff --git a/device/arista/x86_64-arista_7280dr3am_36/platform_components.json b/device/arista/x86_64-arista_7280dr3am_36/platform_components.json new file mode 100644 index 0000000000..afbb5102a0 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/platform_components.json @@ -0,0 +1,8 @@ +{ + "chassis": { + "DCS-7280DR3AM-36": { + "component": { + } + } + } +} diff --git a/device/arista/x86_64-arista_7280dr3am_36/platform_env.conf b/device/arista/x86_64-arista_7280dr3am_36/platform_env.conf new file mode 120000 index 0000000000..c72dc74350 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/platform_env.conf @@ -0,0 +1 @@ +../x86_64-arista_7280dr3a_36/platform_env.conf \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3am_36/platform_reboot b/device/arista/x86_64-arista_7280dr3am_36/platform_reboot new file mode 120000 index 0000000000..7f94a49e38 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/platform_reboot @@ -0,0 +1 @@ +../x86_64-arista_common/platform_reboot \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3am_36/plugins b/device/arista/x86_64-arista_7280dr3am_36/plugins new file mode 120000 index 0000000000..789a45fcac --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/plugins @@ -0,0 +1 @@ +../x86_64-arista_common/plugins \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3am_36/pmon_daemon_control.json b/device/arista/x86_64-arista_7280dr3am_36/pmon_daemon_control.json new file mode 120000 index 0000000000..51d5ab7b00 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/pmon_daemon_control.json @@ -0,0 +1 @@ +../x86_64-arista_common/pmon_daemon_control.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3am_36/sensors.conf b/device/arista/x86_64-arista_7280dr3am_36/sensors.conf new file mode 100644 index 0000000000..1e8a379fa4 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/sensors.conf @@ -0,0 +1,7 @@ +chip "nvme-pci-0500" + ignore temp2 + ignore temp3 + ignore temp4 + ignore temp5 + ignore temp6 + ignore temp7 diff --git a/device/arista/x86_64-arista_7280dr3am_36/system_health_monitoring_config.json b/device/arista/x86_64-arista_7280dr3am_36/system_health_monitoring_config.json new file mode 120000 index 0000000000..1185f771fa --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/system_health_monitoring_config.json @@ -0,0 +1 @@ +../x86_64-arista_common/system_health_monitoring_config.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7280dr3am_36/thermal_policy.json b/device/arista/x86_64-arista_7280dr3am_36/thermal_policy.json new file mode 120000 index 0000000000..0991dc7f36 --- /dev/null +++ b/device/arista/x86_64-arista_7280dr3am_36/thermal_policy.json @@ -0,0 +1 @@ +../x86_64-arista_common/thermal_policy.json \ No newline at end of file diff --git a/files/Aboot/boot0.j2 b/files/Aboot/boot0.j2 index 55cf98680d..4902084431 100644 --- a/files/Aboot/boot0.j2 +++ b/files/Aboot/boot0.j2 @@ -571,6 +571,18 @@ write_platform_specific_cmdline() { if [ "$sid" = "BlackhawkTH4DD" ] || [ "$sid" = "BlackhawkTh4Dd" ]; then aboot_machine=arista_7060dx5_32 fi + if [ "$sid" = "QuartzDd" ]; then + aboot_machine=arista_7280dr3a_36 + fi + if [ "$sid" = "QuartzDdBk" ]; then + aboot_machine=arista_7280dr3ak_36 + fi + if [ "$sid" = "QuartzDdBkS" ]; then + aboot_machine=arista_7280dr3ak_36s + fi + if [ "$sid" = "QuartzDdMs" ]; then + aboot_machine=arista_7280dr3am_36 + fi if [ "$sid" = "Smartsville" ]; then aboot_machine=arista_7280cr3_32p4 fi @@ -653,6 +665,9 @@ write_platform_specific_cmdline() { cmdline_add usb-storage.delay_use=0 cmdline_add reassign_prefmem fi + if in_array "$platform" "cormorant"; then + read_system_eeprom + fi if in_array "$platform" "rook" "sprucefish"; then cmdline_add iommu=on cmdline_add intel_iommu=on diff --git a/src/sonic-device-data/tests/permitted_list b/src/sonic-device-data/tests/permitted_list index ff0f433b09..566e491d26 100644 --- a/src/sonic-device-data/tests/permitted_list +++ b/src/sonic-device-data/tests/permitted_list @@ -353,3 +353,11 @@ flowtracker_ipfix_observation_domain_id flowtracker_num_unique_user_entry_keys sai_mmu_tc_to_pg_config sai_hostif_netif_iff_up_set +appl_param_active_links_thr_high +appl_param_active_links_thr_low +appl_param_nof_devices +fabric_mesh_multicast_enable +fabric_num_pipes +fabric_pipe_map_uc +fabric_pipe_map_mc +system_contains_multiple_pipe_device