precomputed.pil

// General/shared precomputed columns.
namespace precomputed;

// From 0 and incrementing up to the size of the circuit (2^21).
pol constant clk;

// 1 only at row 0.
pol constant first_row;

// AND/OR/XOR of all 8-bit numbers.
// The tables are "stacked". First AND, then OR, then XOR.
// Note: think if we can avoid the selector.
pol constant sel_bitwise; // 1 in the first 3 * 256 rows.
pol constant bitwise_op_id; // identifies if operation is AND/OR/XOR.
pol constant bitwise_input_a; // column of all 8-bit numbers.
pol constant bitwise_input_b; // column of all 8-bit numbers.
pol constant bitwise_output; // output = a AND/OR/XOR b.

// Boolean selectors for 8-bit and 16-bit range checks.
// We reuse clk for the actual values.
pol constant sel_range_8;  // 1 in the first 2^8 rows [0, 2^8)
pol constant sel_range_16; // 1 in the first 2^16 rows [0, 2^16)

// All the powers of 2 from 0 to 255
// For a given row, the exponent is clk (value = 2^clk)
// Populated for the first 256 rows [0, 255]
pol constant power_of_2;

// SHA256 Round Params Lookup
pol constant sel_sha256_compression;
pol constant sha256_compression_round_constant;

// Unary representation of a number, from 0 to 64.
// Example: 0 -> 0
//          1 -> 1
//          2 -> 11
//          3 -> 111
// You get it. It can be extended up to 254 bits if needed.
pol constant sel_unary;
pol constant as_unary;

// A mapping between a non-FF MemoryTag value and their respective byte lengths:
// {U1: 1, U8: 1, U16: 2, ... , U128: 16}
// The enum values of MemoryTag are present in column clk.
pol constant sel_integral_tag; // Toggle row with clk == U1,U8,U16,...,U128
pol constant integral_tag_length; // Columns for the byte length 1,1,2,...,16;

// Remark: A potential optimization may consist in using sel_bitwise instead of sel_integral_mem_tag.
//         However, it would extend this lookup table with pairs such as (0,0), (7,0), (8,0) which is
//         not without any danger.


// Selectors for operands decomposition into bytes (required by instr_fetching.pil)
// This table is populated by a map generated by a cpp test defined in op_decomposition.test.cpp.
pol constant sel_op_dc_0;
pol constant sel_op_dc_1;
pol constant sel_op_dc_2;
pol constant sel_op_dc_3;
pol constant sel_op_dc_4;
pol constant sel_op_dc_5;
pol constant sel_op_dc_6;
pol constant sel_op_dc_7;
pol constant sel_op_dc_8;
pol constant sel_op_dc_9;
pol constant sel_op_dc_10;
pol constant sel_op_dc_11;
pol constant sel_op_dc_12;
pol constant sel_op_dc_13;
pol constant sel_op_dc_14;
pol constant sel_op_dc_15;
pol constant sel_op_dc_16;
pol constant sel_op_dc_17;

pol constant exec_opcode;

// Toggle the rows which index (clk) is equal to a wire opcode
// Is used to lookup into the wire instruction spec table which contains the operand decomposition
// selectors as well as exec_opcode
pol constant sel_range_wire_opcode;