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Brian Zhu
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vpp: add interface to force non-afbc path [1/1]
PD#SWPL-7035 Problem: When DI switched to use VD AFBC, need vpp force to non-afbc first. Otherwise, display willl flash. Solution: Provide new interface to request the vpp release afbc hardware first. Then return the current afbc status. Verify: verified on x301 Change-Id: Ibb2b897db7d2f2c40006433d63709988992c84f1 Signed-off-by: Brian Zhu <[email protected]>
1 parent 4a45686 commit b8d9145

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4 files changed

+182
-27
lines changed

4 files changed

+182
-27
lines changed

‎drivers/amlogic/media/video_sink/video.c‎

Lines changed: 169 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -467,6 +467,8 @@ static bool hist_test_flag;
467467
static unsigned long hist_buffer_addr;
468468
static u32 hist_print_count;
469469

470+
static atomic_t gAfbc_request = ATOMIC_INIT(0);
471+
470472
#define MAX_ZOOM_RATIO 300
471473

472474
#define VPP_PREBLEND_VD_V_END_LIMIT 2304
@@ -1177,6 +1179,65 @@ static int noneseamless_play_clone_rate = 5;
11771179

11781180
#define CONFIG_AM_VOUT
11791181

1182+
static s32 is_afbc_for_vpp(u8 id)
1183+
{
1184+
s32 ret = -1;
1185+
u32 val;
1186+
1187+
if ((id >= MAX_VD_LAYERS)
1188+
|| legacy_vpp)
1189+
return ret;
1190+
1191+
if (id == 0)
1192+
val = READ_VCBUS_REG(
1193+
VD1_AFBCD0_MISC_CTRL);
1194+
else
1195+
val = READ_VCBUS_REG(
1196+
VD2_AFBCD1_MISC_CTRL);
1197+
1198+
if ((val & (1 << 10)) && (val & (1 << 12))
1199+
&& !(val & (1 << 9)))
1200+
ret = 1;
1201+
else
1202+
ret = 0;
1203+
return ret;
1204+
}
1205+
1206+
s32 di_request_afbc_hw(u8 id, bool on)
1207+
{
1208+
u32 cur_afbc_request;
1209+
u32 next_request = 0;
1210+
s32 ret = -1;
1211+
1212+
if (id >= MAX_VD_LAYERS)
1213+
return ret;
1214+
1215+
if (!glayer_info[id].afbc_support || legacy_vpp)
1216+
return ret;
1217+
1218+
next_request = 1 << id;
1219+
cur_afbc_request = atomic_read(&gAfbc_request);
1220+
if (on) {
1221+
if (cur_afbc_request & next_request)
1222+
return is_afbc_for_vpp(id);
1223+
1224+
atomic_add(next_request, &gAfbc_request);
1225+
ret = 1;
1226+
} else {
1227+
if ((cur_afbc_request & next_request) == 0)
1228+
return is_afbc_for_vpp(id);
1229+
1230+
atomic_sub(next_request, &gAfbc_request);
1231+
ret = 1;
1232+
}
1233+
if (id == 0)
1234+
video_property_changed = 1;
1235+
else
1236+
pip_property_changed = 1;
1237+
return ret;
1238+
}
1239+
EXPORT_SYMBOL(di_request_afbc_hw);
1240+
11801241
void safe_disble_videolayer(void)
11811242
{
11821243
#ifdef CONFIG_AMLOGIC_POST_PROCESS_MANAGER_PPSCALER
@@ -1977,7 +2038,8 @@ static void zoom_get_vert_pos(struct vframe_s *vf, u32 vpp_3d_mode, u32 *ls,
19772038
}
19782039

19792040
#endif
1980-
static void zoom_display_horz(struct vframe_s *vf, int hscale)
2041+
static void zoom_display_horz(
2042+
struct vframe_s *vf, int hscale, bool no_compress)
19812043
{
19822044
u32 ls = 0, le = 0, rs = 0, re = 0;
19832045
#ifdef TV_REVERSE
@@ -2017,7 +2079,8 @@ static void zoom_display_horz(struct vframe_s *vf, int hscale)
20172079
(((zoom_end_x_lines / 2 - zoom_start_x_lines / 2 +
20182080
1) >> hscale) << VD1_FMT_CHROMA_WIDTH_BIT));
20192081

2020-
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) {
2082+
if (!no_compress &&
2083+
vf && (vf->type & VIDTYPE_COMPRESS)) {
20212084
int l_aligned;
20222085
int r_aligned;
20232086
int h_skip = cur_frame_par->hscale_skip_count + 1;
@@ -2197,7 +2260,8 @@ static void vd2_zoom_display_horz(struct vframe_s *vf, int hscale)
21972260
<< VD1_FMT_CHROMA_WIDTH_BIT));
21982261
}
21992262

2200-
static void zoom_display_vert(struct vframe_s *vf)
2263+
static void zoom_display_vert(
2264+
struct vframe_s *vf, int vscale, bool no_compress)
22012265
{
22022266

22032267
u32 ls = 0, le = 0, rs = 0, re = 0;
@@ -2300,12 +2364,13 @@ static void zoom_display_vert(struct vframe_s *vf)
23002364
}
23012365
}
23022366

2303-
if (get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) {
2367+
if (!no_compress &&
2368+
vf && (vf->type & VIDTYPE_COMPRESS)) {
23042369
int t_aligned;
23052370
int b_aligned;
23062371
int ori_t_aligned;
23072372
int ori_b_aligned;
2308-
int v_skip = cur_frame_par->vscale_skip_count + 1;
2373+
int v_skip = vscale + 1;
23092374
int c_skip = 2;
23102375

23112376
/* After TL1, afbc supports 420/422/444*/
@@ -2605,7 +2670,7 @@ static void vsync_video_pattern(void)
26052670
}
26062671
#endif
26072672

2608-
static inline void vd1_path_select(bool afbc)
2673+
static inline void vd1_path_select(bool afbc, bool di_afbc)
26092674
{
26102675
u32 misc_off = cur_dev->vpp_off;
26112676

@@ -2619,13 +2684,13 @@ static inline void vd1_path_select(bool afbc)
26192684
/* vd1 -> dolby -> vpp top */
26202685
(0 << 14) |
26212686
/* axi sel: vd1 mif or afbc */
2622-
((afbc ? 1 : 0) << 12) |
2687+
(((afbc || di_afbc) ? 1 : 0) << 12) |
26232688
/* data sel: vd1 & afbc0 (not osd4) */
26242689
(0 << 11) |
26252690
/* data sel: afbc0 or vd1 */
26262691
((afbc ? 1 : 0) << 10) |
26272692
/* afbc0 to vd1 (not di) */
2628-
(0 << 9) |
2693+
((di_afbc ? 1 : 0) << 9) |
26292694
/* vd1 mif to vpp (not di) */
26302695
(0 << 8) |
26312696
/* afbc0 gclk ctrl */
@@ -2669,7 +2734,7 @@ static inline void vd1_path_select(bool afbc)
26692734
}
26702735
}
26712736

2672-
static inline void vd2_path_select(bool afbc)
2737+
static inline void vd2_path_select(bool afbc, bool di_afbc)
26732738
{
26742739
u32 misc_off = cur_dev->vpp_off;
26752740

@@ -2683,13 +2748,13 @@ static inline void vd2_path_select(bool afbc)
26832748
/* TODO: vd2 -> dolby -> vpp top ?? */
26842749
(0 << 14) |
26852750
/* axi sel: vd2 mif */
2686-
((afbc ? 1 : 0) << 12) |
2751+
(((afbc || di_afbc) ? 1 : 0) << 12) |
26872752
/* data sel: vd2 & afbc1 (not osd4) */
26882753
(0 << 11) |
26892754
/* data sel: afbc1 */
26902755
((afbc ? 1 : 0) << 10) |
26912756
/* afbc1 to vd2 (not di) */
2692-
(0 << 9) |
2757+
((di_afbc ? 1 : 0) << 9) |
26932758
/* vd2 mif to vpp (not di) */
26942759
(0 << 8) |
26952760
/* afbc1 gclk ctrl */
@@ -3268,6 +3333,7 @@ static void pip_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
32683333
u32 u, v;
32693334
u32 type, bit_mode = 0;
32703335
u8 burst_len = 1;
3336+
u32 canvas_w;
32713337

32723338
if (!vf || !frame_par) {
32733339
pr_err("pip_set_dcu vf is NULL\n");
@@ -3394,12 +3460,25 @@ static void pip_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
33943460
VD2_AFBCDEC_IQUANT_ENABLE, 0);
33953461
}
33963462

3397-
vd2_path_select(true);
3463+
vd2_path_select(true, false);
33983464
VSYNC_WR_MPEG_REG(VD2_IF0_GEN_REG +
33993465
cur_dev->viu_off, 0);
34003466
return;
34013467
}
34023468

3469+
/* vd mif burst len is 2 as default */
3470+
burst_len = 2;
3471+
if (vf->canvas0Addr != (u32)-1)
3472+
canvas_w = canvas_get_width(
3473+
vf->canvas0Addr & 0xff);
3474+
else
3475+
canvas_w = vf->canvas0_config[0].width;
3476+
3477+
if (canvas_w % 32)
3478+
burst_len = 0;
3479+
else if (canvas_w % 64)
3480+
burst_len = 1;
3481+
34033482
if ((vf->bitdepth & BITDEPTH_Y10) &&
34043483
(!frame_par->nocomp)) {
34053484
if (vf->type & VIDTYPE_VIU_444) {
@@ -3413,11 +3492,14 @@ static void pip_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
34133492
} else {
34143493
bit_mode = 0;
34153494
}
3416-
vd2_path_select(false);
3495+
vd2_path_select(false, false);
34173496
if (!legacy_vpp) {
34183497
VSYNC_WR_MPEG_REG_BITS(
34193498
G12_VD2_IF0_GEN_REG3,
34203499
(bit_mode & 0x3), 8, 2);
3500+
VSYNC_WR_MPEG_REG_BITS(
3501+
G12_VD2_IF0_GEN_REG3,
3502+
(burst_len & 0x3), 1, 2);
34213503
} else {
34223504
VSYNC_WR_MPEG_REG_BITS(
34233505
VD2_IF0_GEN_REG3 + cur_dev->viu_off,
@@ -3678,6 +3760,13 @@ static void vsync_toggle_frame(struct vframe_s *vf, int line)
36783760
frame_count++;
36793761
toggle_count++;
36803762

3763+
if (vf && !(vf->type & VIDTYPE_COMPRESS)
3764+
&& glayer_info[0].need_no_compress) {
3765+
atomic_sub(1, &gAfbc_request);
3766+
glayer_info[0].need_no_compress = false;
3767+
force_toggle = true;
3768+
}
3769+
36813770
if (vf->type & VIDTYPE_MVC)
36823771
is_mvc = true;
36833772

@@ -3877,7 +3966,7 @@ static void vsync_toggle_frame(struct vframe_s *vf, int line)
38773966

38783967
/* switch buffer */
38793968
post_canvas = vf->canvas0Addr;
3880-
if ((get_cpu_type() >= MESON_CPU_MAJOR_ID_GXBB) &&
3969+
if (!glayer_info[0].need_no_compress &&
38813970
(vf->type & VIDTYPE_COMPRESS)) {
38823971
VSYNC_WR_MPEG_REG(AFBC_HEAD_BADDR, vf->compHeadAddr>>4);
38833972
VSYNC_WR_MPEG_REG(AFBC_BODY_BADDR, vf->compBodyAddr>>4);
@@ -4360,15 +4449,30 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
43604449
AFBCDEC_IQUANT_ENABLE, 0);
43614450
}
43624451

4363-
vd1_path_select(true);
4452+
vd1_path_select(true, false);
43644453

43654454
VSYNC_WR_MPEG_REG(
43664455
VD1_IF0_GEN_REG + cur_dev->viu_off, 0);
43674456
return;
43684457

43694458
} else {
4459+
u32 canvas_w;
4460+
4461+
/* vd mif burst len is 2 as default */
4462+
burst_len = 2;
4463+
if (vf->canvas0Addr != (u32)-1)
4464+
canvas_w = canvas_get_width(
4465+
vf->canvas0Addr & 0xff);
4466+
else
4467+
canvas_w = vf->canvas0_config[0].width;
4468+
4469+
if (canvas_w % 32)
4470+
burst_len = 0;
4471+
else if (canvas_w % 64)
4472+
burst_len = 1;
4473+
43704474
if ((vf->bitdepth & BITDEPTH_Y10) &&
4371-
(!frame_par->nocomp)) {
4475+
(!frame_par->nocomp)) {
43724476
if (vf->type & VIDTYPE_VIU_444) {
43734477
bit_mode = 2;
43744478
} else {
@@ -4384,10 +4488,17 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
43844488
VSYNC_WR_MPEG_REG_BITS(
43854489
G12_VD1_IF0_GEN_REG3,
43864490
(bit_mode & 0x3), 8, 2);
4387-
if (is_mvc)
4491+
VSYNC_WR_MPEG_REG_BITS(
4492+
G12_VD1_IF0_GEN_REG3,
4493+
(burst_len & 0x3), 1, 2);
4494+
if (is_mvc) {
43884495
VSYNC_WR_MPEG_REG_BITS(
43894496
G12_VD2_IF0_GEN_REG3,
43904497
(bit_mode & 0x3), 8, 2);
4498+
VSYNC_WR_MPEG_REG_BITS(
4499+
G12_VD2_IF0_GEN_REG3,
4500+
(burst_len & 0x3), 1, 2);
4501+
}
43914502
} else {
43924503
VSYNC_WR_MPEG_REG_BITS(
43934504
VD1_IF0_GEN_REG3 +
@@ -4409,8 +4520,14 @@ static void viu_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
44094520
DI_POST_WR_REG_BITS(DI_IF0_GEN_REG3,
44104521
(bit_mode & 0x3), 8, 2);
44114522
#endif
4412-
vd1_path_select(false);
4413-
VSYNC_WR_MPEG_REG(AFBC_ENABLE, 0);
4523+
if (glayer_info[0].need_no_compress
4524+
|| (vf->type & VIDTYPE_PRE_DI_AFBC)) {
4525+
vd1_path_select(false, true);
4526+
} else {
4527+
vd1_path_select(false, false);
4528+
VSYNC_WR_MPEG_REG(
4529+
AFBC_ENABLE, 0);
4530+
}
44144531
}
44154532
}
44164533

@@ -4904,13 +5021,28 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
49045021
VD2_AFBCDEC_IQUANT_ENABLE, 0);
49055022
}
49065023

4907-
vd2_path_select(true);
5024+
vd2_path_select(true, false);
49085025
VSYNC_WR_MPEG_REG(VD2_IF0_GEN_REG +
49095026
cur_dev->viu_off, 0);
49105027
return;
49115028
} else {
5029+
u32 canvas_w;
5030+
5031+
/* vd mif burst len is 2 as default */
5032+
burst_len = 2;
5033+
if (vf->canvas0Addr != (u32)-1)
5034+
canvas_w = canvas_get_width(
5035+
vf->canvas0Addr & 0xff);
5036+
else
5037+
canvas_w = vf->canvas0_config[0].width;
5038+
5039+
if (canvas_w % 32)
5040+
burst_len = 0;
5041+
else if (canvas_w % 64)
5042+
burst_len = 1;
5043+
49125044
if ((vf->bitdepth & BITDEPTH_Y10) &&
4913-
(!frame_par->nocomp)) {
5045+
(!frame_par->nocomp)) {
49145046
if (vf->type & VIDTYPE_VIU_444) {
49155047
bit_mode = 2;
49165048
} else {
@@ -4922,11 +5054,14 @@ static void vd2_set_dcu(struct vpp_frame_par_s *frame_par, struct vframe_s *vf)
49225054
} else {
49235055
bit_mode = 0;
49245056
}
4925-
vd2_path_select(false);
5057+
vd2_path_select(false, false);
49265058
if (!legacy_vpp) {
49275059
VSYNC_WR_MPEG_REG_BITS(
49285060
G12_VD2_IF0_GEN_REG3,
49295061
(bit_mode & 0x3), 8, 2);
5062+
VSYNC_WR_MPEG_REG_BITS(
5063+
G12_VD2_IF0_GEN_REG3,
5064+
(burst_len & 0x3), 1, 2);
49305065
} else {
49315066
VSYNC_WR_MPEG_REG_BITS(
49325067
VD2_IF0_GEN_REG3 + cur_dev->viu_off,
@@ -6405,6 +6540,12 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
64056540
static struct vframe_s *pause_vf;
64066541
int force_flush = 0;
64076542
static u32 interrupt_count;
6543+
u32 next_afbc_request = atomic_read(&gAfbc_request);
6544+
6545+
glayer_info[0].need_no_compress =
6546+
(next_afbc_request & 1) ? true : false;
6547+
glayer_info[1].need_no_compress =
6548+
(next_afbc_request & 2) ? true : false;
64086549

64096550
if (debug_flag & DEBUG_FLAG_VSYNC_DONONE)
64106551
return IRQ_HANDLED;
@@ -7583,11 +7724,14 @@ static irqreturn_t vsync_isr_in(int irq, void *dev_id)
75837724
cur_frame_par->VPP_hd_start_lines_;
75847725
zoom_end_x_lines = cur_frame_par->VPP_hd_end_lines_;
75857726
zoom_display_horz(cur_dispbuf,
7586-
cur_frame_par->hscale_skip_count);
7727+
cur_frame_par->hscale_skip_count,
7728+
cur_frame_par->nocomp);
75877729

75887730
zoom_start_y_lines = zoom_start_y;
75897731
zoom_end_y_lines = zoom_end_y;
7590-
zoom_display_vert(cur_dispbuf);
7732+
zoom_display_vert(cur_dispbuf,
7733+
cur_frame_par->vscale_skip_count,
7734+
cur_frame_par->nocomp);
75917735
if (is_dolby_vision_enable() && cur_dispbuf2) {
75927736
zoom2_start_x_lines = ori2_start_x_lines;
75937737
zoom2_end_x_lines = ori2_end_x_lines;
@@ -8754,6 +8898,7 @@ static int video_receiver_event_fun(int type, void *data, void *private_data)
87548898
/*alternative mode,passing two buffer in one frame */
87558899
if (platform_type == 1) {
87568900
if ((process_3d_type & MODE_3D_FA) &&
8901+
cur_dispbuf &&
87578902
!cur_dispbuf->trans_fmt)
87588903
vf_notify_receiver_by_name("deinterlace",
87598904
VFRAME_EVENT_PROVIDER_SET_3D_VFRAME_INTERLEAVE,

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