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    19 repositories

    • siliconcompiler

      Public
      Modular hardware build system
      asicfpgahls
      asicfpgahlsvhdledartlverilogmakesynthesiscmos
      Python
      •
      Apache License 2.0
      •127•1.2k•32•6•Updated Jun 9, 2026Jun 9, 2026

    • scgallery

      Public
      SiliconCompiler Design Gallery
      Verilog
      •
      Apache License 2.0
      •9•65•0•2•Updated Jun 8, 2026Jun 8, 2026

    • sc-leflib

      Public
      C++
      •
      Apache License 2.0
      •1•5•0•1•Updated Jun 8, 2026Jun 8, 2026

    • lambdapdk

      Public
      Library of open source PDKs
      SourcePawn
      •
      Apache License 2.0
      •10•77•2•0•Updated Jun 6, 2026Jun 6, 2026

    • lambdalib

      Public
      Verilog hardware abstraction library
      Python
      •
      MIT License
      •8•53•3•3•Updated May 24, 2026May 24, 2026

    • fpga-timing-coverage-suite

      Public
      Python
      •
      MIT License
      •1•5•0•0•Updated May 4, 2026May 4, 2026

    • logik

      Public
      A configurable RTL to bitstream FPGA toolchain
      Python
      •
      Apache License 2.0
      •8•61•2•0•Updated Apr 24, 2026Apr 24, 2026

    • logiklib

      Public
      Library of FPGA architectures
      Python
      •
      Apache License 2.0
      •3•33•0•1•Updated Apr 13, 2026Apr 13, 2026

    • zerosoc

      Public
      Demo SoC for SiliconCompiler.
      SystemVerilog
      •10•64•5•0•Updated Mar 29, 2026Mar 29, 2026

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •1.1k•0•0•0•Updated May 7, 2025May 7, 2025

    • sc-surelog

      Public archive
      Python
      •
      Apache License 2.0
      •0•1•0•0•Updated Mar 10, 2025Mar 10, 2025

    • OpenROAD-flow-scripts

      Public archive
      Verilog
      •
      Other
      •497•0•0•0•Updated Dec 11, 2023Dec 11, 2023

    • fossi-foundation.github.io

      Public archive
      FOSSi Foundation Website
      HTML
      •45•0•0•0•Updated Mar 2, 2023Mar 2, 2023

    • Surelog

      Public archive
      SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-…
      C++
      •
      Apache License 2.0
      •82•0•0•0•Updated Nov 7, 2022Nov 7, 2022

    • sc-education

      Public
      Educational material
      1•3•0•0•Updated Jul 14, 2022Jul 14, 2022

    • cva6

      Public archive
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      C++
      •
      Other
      •957•1•0•0•Updated Jul 10, 2022Jul 10, 2022

    • common_cells

      Public archive
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •199•0•0•0•Updated Jun 30, 2022Jun 30, 2022

    • caravel_wrapper_heartbeat_example

      Public archive
      This repository is a clone of efabless' "caravel_user_project" template. It contains a netlist and GDS file produced by a SiliconCompiler build flow, in a forma…
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated May 18, 2022May 18, 2022

    • sc-rfcs

      Public
      RFCs for changes to SiliconCompiler
      Apache License 2.0
      •0•7•0•0•Updated Oct 29, 2021Oct 29, 2021
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