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    • Modular hardware build system
      Python
      Apache License 2.0
      1271.2k326Updated Jun 9, 2026Jun 9, 2026
    • scgallery

      Public
      SiliconCompiler Design Gallery
      Verilog
      Apache License 2.0
      96502Updated Jun 8, 2026Jun 8, 2026
    • sc-leflib

      Public
      C++
      Apache License 2.0
      1501Updated Jun 8, 2026Jun 8, 2026
    • lambdapdk

      Public
      Library of open source PDKs
      SourcePawn
      Apache License 2.0
      107720Updated Jun 6, 2026Jun 6, 2026
    • lambdalib

      Public
      Verilog hardware abstraction library
      Python
      MIT License
      85333Updated May 24, 2026May 24, 2026
    • Python
      MIT License
      1500Updated May 4, 2026May 4, 2026
    • logik

      Public
      A configurable RTL to bitstream FPGA toolchain
      Python
      Apache License 2.0
      86120Updated Apr 24, 2026Apr 24, 2026
    • logiklib

      Public
      Library of FPGA architectures
      Python
      Apache License 2.0
      33301Updated Apr 13, 2026Apr 13, 2026
    • zerosoc

      Public
      Demo SoC for SiliconCompiler.
      SystemVerilog
      106450Updated Mar 29, 2026Mar 29, 2026
    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      ISC License
      1.1k000Updated May 7, 2025May 7, 2025
    • sc-surelog

      Public archive
      Python
      Apache License 2.0
      0100Updated Mar 10, 2025Mar 10, 2025
    • OpenROAD-flow-scripts

      Public archive
      Verilog
      Other
      497000Updated Dec 11, 2023Dec 11, 2023
    • FOSSi Foundation Website
      HTML
      45000Updated Mar 2, 2023Mar 2, 2023
    • Surelog

      Public archive
      SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-…
      C++
      Apache License 2.0
      82000Updated Nov 7, 2022Nov 7, 2022
    • Educational material
      1300Updated Jul 14, 2022Jul 14, 2022
    • cva6

      Public archive
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      C++
      Other
      957100Updated Jul 10, 2022Jul 10, 2022
    • common_cells

      Public archive
      Common SystemVerilog components
      SystemVerilog
      Other
      199000Updated Jun 30, 2022Jun 30, 2022
    • This repository is a clone of efabless' "caravel_user_project" template. It contains a netlist and GDS file produced by a SiliconCompiler build flow, in a forma…
      Verilog
      Apache License 2.0
      0000Updated May 18, 2022May 18, 2022
    • sc-rfcs

      Public
      RFCs for changes to SiliconCompiler
      Apache License 2.0
      0700Updated Oct 29, 2021Oct 29, 2021
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