Describe the bug
The extension incorrectly highlights "undefined module" errors for multiple user-defined modules, as well as various IP core instantiations (such as ila and vio). As shown in the screenshot, although the file DAC1220_control.v exists in the same directory, the linter fails to recognize the module.
Please note that this issue is not isolated to DAC1220_control. Multiple other modules within the project, as well as several Xilinx IP core instantiations (e.g., ila_0, vio_0), are also being falsely flagged as undefined. This indicates a systemic path resolution or file parsing failure when handling both user source files and generated IP core dependencies.
Environment (please complete the following information):
- OS: Windows 11
- VS Code version: 1.127.0
- Extension version: mshr-h.veriloghdl 1.28.1
- color themes, lint tools, etc.: Default theme, default linter (likely iverilog)
Steps to reproduce
Steps to reproduce the behavior:
- Open the Verilog project folder containing both user-defined modules and generated IP cores in VS Code.
- Locate the
DAC1220_control.v file and other IP core definition files (e.g., ila_0.v, vio_0.v) in the project directory.
- In the top-level module (e.g.,
top_module.v), instantiate the DAC1220_control module as well as the IP cores (ila, vio).
- Observe that multiple module names are underlined with red squiggly error lines, indicating "undefined module" errors, despite their respective
.v files being present in the project.
Expected behavior
The extension should properly resolve and parse all user-defined modules and IP core dependencies located in the project directory. It should recognize the instantiated modules and not display "undefined module" errors for user modules or common IP cores.
Actual behavior
As shown in the attached screenshot, the linter fails to resolve the DAC1220_control module, resulting in a false positive red error underline. Furthermore, the same "undefined module" error occurs for multiple other modules and for IP core instantiations (like ila and vio) throughout the codebase, suggesting a broader scanning or parsing failure.
Additional context
- The issue appears to stem from the linter's path resolution. It fails to automatically include the project root directory (or the necessary IP core directories) in the
-I (include) paths.
- For IP cores like
ila and vio, the extension likely needs to handle generated netlists or specific black-box definitions, which it currently fails to resolve.
- Please let me know if adjusting any configuration settings (like
verilog.linting.includePath or specific IP core search paths) could resolve this, or if this behavior indicates a missing feature in the extension's design.
Describe the bug
The extension incorrectly highlights "undefined module" errors for multiple user-defined modules, as well as various IP core instantiations (such as
ilaandvio). As shown in the screenshot, although the fileDAC1220_control.vexists in the same directory, the linter fails to recognize the module.Please note that this issue is not isolated to
DAC1220_control. Multiple other modules within the project, as well as several Xilinx IP core instantiations (e.g.,ila_0,vio_0), are also being falsely flagged as undefined. This indicates a systemic path resolution or file parsing failure when handling both user source files and generated IP core dependencies.Environment (please complete the following information):
Steps to reproduce
Steps to reproduce the behavior:
DAC1220_control.vfile and other IP core definition files (e.g.,ila_0.v,vio_0.v) in the project directory.top_module.v), instantiate theDAC1220_controlmodule as well as the IP cores (ila,vio)..vfiles being present in the project.Expected behavior
The extension should properly resolve and parse all user-defined modules and IP core dependencies located in the project directory. It should recognize the instantiated modules and not display "undefined module" errors for user modules or common IP cores.
Actual behavior
As shown in the attached screenshot, the linter fails to resolve the
DAC1220_controlmodule, resulting in a false positive red error underline. Furthermore, the same "undefined module" error occurs for multiple other modules and for IP core instantiations (likeilaandvio) throughout the codebase, suggesting a broader scanning or parsing failure.Additional context
-I(include) paths.ilaandvio, the extension likely needs to handle generated netlists or specific black-box definitions, which it currently fails to resolve.verilog.linting.includePathor specific IP core search paths) could resolve this, or if this behavior indicates a missing feature in the extension's design.